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Albert James
Albert James Van Norstrand, Round Rock, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080201563 | Apparatus for Improving Single Thread Performance through Speculative Processing - An apparatus is provided for using multiple thread contexts to improve processing performance of a single thread. When an exceptional instruction is encountered, the exceptional instruction and any predicted instructions are reloaded into a buffer of a first thread context. A state of the register file at the time of encountering the exceptional instruction is maintained in a register file of the first thread context. The instructions in the pipeline are executed speculatively using a second register file in a second thread context. During speculative execution, cache misses may cause loading of data to the cache may be performed. Results of the speculative execution are written to the second register file. When a stopping condition is met, contents of the first register file are copied to the second register file and the reloaded instructions are released to the execution pipeline. | 08-21-2008 |
| 20090077352 | PERFORMANCE OF AN IN-ORDER PROCESSOR BY NO LONGER REQUIRING A UNIFORM COMPLETION POINT ACROSS DIFFERENT EXECUTION PIPELINES - A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines. | 03-19-2009 |
Albert James Van Norstrand, Jr., Round Rock, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090070609 | POWER THROTTLING APPARATUS - Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same. | 03-12-2009 |
| 20090198959 | SCALABLE LINK STACK CONTROL METHOD WITH FULL SUPPORT FOR SPECULATIVE OPERATIONS - A computer implemented method, a processor chip, a computer program product, and a data processing system managing a link stack. The data processing system utilizes speculative pushes onto and pops from the link stack. The link stack comprises a set of entries, and each entry comprises a set of state bits. A speculative push of a first instruction is received onto the data stack, and the first instruction is stored into a first entry of the set of entries. A first bit is set to indicate that the first instruction is a valid instruction. A second bit is set to indicate that the first instruction has been speculatively pushed onto the link stack. The link stack pointer control is updated to indicate that the first entry is a top-of-data stack entry. | 08-06-2009 |
Albert James Youngwerth, Jr., Boise, ID US
| Patent application number | Description | Published |
|---|---|---|
| 20090242351 | Automatic Clutch Employing Expanding Friction Disk and an Adjustable Pressure Plate - An apparatus and system are disclosed for automatic centrifugal engagement of a clutch incorporating a friction disk that expands when rotated above a threshold speed. The apparatus may include a clutch basket, a clutch pack capable of coupling the clutch basket with a center clutch, a pressure plate that may be easily adjusted to create a gap between the pressure plate and the clutch pack and an expanding friction disk assembly that may take the place of one or more friction disks. The assembly expands under centrifugal force to provide automatic engagement of the clutch. A mechanism is provided to manually override the automatic engagement of the clutch with a clutch lever and with improved operational performance of the clutch lever versus previous automatic clutch systems. | 10-01-2009 |
| 20100307886 | Clutch Apparatus Employing Dual Concentric Clutches - A clutch apparatus is disclosed having concentrically spaced inner and outer clutches. The inner and outer clutches are coupled for rotation via a coupling ring. The present invention is well suited to a configuration wherein one of the clutches is dynamically actuated and one of the clutches is manually disengageable by the operator using a clutch lever. In this configuration, the operation of the clutch lever by the operator is unaffected by the dynamically actuated clutch. The concentric configuration of the clutches is beneficial in allowing the improved clutch to occupy a similar space compared to a traditional clutch mechanism. | 12-09-2010 |