Albasini
Alfio Albasini, Riazzino CH
Patent application number | Description | Published |
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20110028877 | ORTHOTIC SYSTEM FOR AN ANKLE JOINT - The invention relates to an orthopedic brace system for bracing a joint with a dimensionally stable, flexible base body ( | 02-03-2011 |
20110137220 | KNEE-JOINT ORTHOSIS - In a knee-joint orthosis for guiding the patella of a patient during the transition from an extended position to a flexed position of the knee joint and vice versa, with a fastening means ( | 06-09-2011 |
20120109031 | SUPPORT BANDAGE - The invention relates to a support bandage ( | 05-03-2012 |
Guido Albasini, Voghera IT
Patent application number | Description | Published |
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20090040806 | Reading circuit and method in a data-storage system - A reading circuit for reading a datum stored in a storage material. In the reading circuit, a generating stage generates a read electrical quantity to be applied to the storage material, and a sensing stage is configured to generate an output electrical quantity that is indicative of a charge variation associated to the datum stored, and that occurs in the storage material due to application of the read electrical quantity; in particular, the sensing stage uses a charge-sensing amplifier electrically connected to the storage material. | 02-12-2009 |
Guido Gabriele Albasini, Voghera IT
Patent application number | Description | Published |
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20080211580 | LOW NOISE AC DIFFERENTIAL AMPLIFIER WITH REDUCED LOW CORNER FREQUENCY AND CURRENT CONSUMPTION - An integrated amplifier may include a transconductance stage including a differential pair of input transistors of a first type of conductivity, respective resistive loads coupled to said input transistors, and a first bias circuit coupled to the input transistors. The first bias circuit may include a second differential pair of bias transistors having first conduction terminals coupled in common and second conduction terminals coupled to respective conduction terminals of the input transistors. The first bias circuit may also include respective second bias circuits coupled to the bias transistors to enable the input transistors in a conduction state with the input transistors being biased by a same respective bias current that flows through the respective input transistors. The first bias circuit may also include a capacitive network coupled to the bias transistors to define with the input transistors a feedback loop. | 09-04-2008 |
20110193601 | FRACTIONAL TYPE PHASE-LOCKED LOOP CIRCUIT WITH COMPENSATION OF PHASE ERRORS - A fractional-type phase-locked loop circuit is proposed for synthesising an output signal multiplying a frequency of a reference signal by a fractional conversion factor, the circuit including means for generating a modulation value, means for generating a feedback signal dividing the frequency of the output signal by a dividing ratio, the dividing ratio being modulated according to the modulation value for providing the conversion factor on the average, means for generating a control signal indicative of a phase difference between the reference signal and the feedback signal, means for controlling the frequency of the output signal according to the control signal, and means for compensating a phase error caused by the modulation of the dividing ratio; in the circuit of an embodiment of the invention, the means for compensating includes means for calculating an incremental value, indicative of an incremental phase error, according to the conversion factor and the modulation value, means for calculating a correction value accumulating the incremental value, and means for conditioning the control signal according to the correction value. | 08-11-2011 |