Patent application number | Description | Published |
20140040299 | Automated Method of Detecting Pattern Matches between Converged Infrastructure Models and an Operating Converged Infrastructure - A first technique is provided for automatically building multiple signature patterns representative of corresponding converged infrastructures (CIs), and a second technique is provided for automatically detecting pattern matches between one or more of the multiple signature patterns (and thus the model CIs) built using the first technique and an operating converged infrastructure (CI). Each of the signature patterns includes a compilation of component signatures representative of model compute, storage, and network components of the corresponding model CI. The second technique includes collecting component signatures from, and representative of, each of compute, storage, and network components of an operating converged infrastructure (CI), and pattern matching each of the collected component signatures against one or more of the signature patterns that represent the model CIs. The second technique also includes declaring match results based on the pattern matching. | 02-06-2014 |
20140108937 | Model-Based Configuration Capture and Replay in a Converged Infrastructure System to Support Remote Troubleshooting - Configuration models are accessed, each configuration model defining configuration attributes to be collected from a respective one of compute, storage, and network components of a converged infrastructure and collecting actual configuration attributes from each of the compute, storage, and network components of the converged infrastructure in accordance with the configuration models. A policy is accessed that defines configuration attribute rules corresponding to each of the configuration attributes collected from the compute, storage, and network components and comparing the collected configuration attributes to the configuration attribute rules for each of the compute, storage, and network components. Results of the comparing are reported, including which of the collected configuration attributes violate the corresponding configuration rules. | 04-17-2014 |
20140109097 | Automated Technique to Configure and Provision Components of a Converged Infrastructure - A technique to provision a converted infrastructure (CI) includes generating task definitions to configure respective ones of compute, storage, and network components of a converged infrastructure (CI) when invoked. Each task definition includes a task identifier (ID), one or more component configuration commands, and one or more task arguments through which one or more corresponding component configuration parameters are passed to corresponding ones of the one or more component commands. The technique further includes automatically invoking each of the task definitions by task ID according to an ordered sequence in order to configure the CI. The automatically invoking includes providing the one or more component configuration commands and the corresponding one or more passed configuration parameters of each invoked task definition to the respective ones of the CI components. | 04-17-2014 |
Patent application number | Description | Published |
20130277854 | 3D INTEGRATED CIRCUIT SYSTEM WITH CONNECTING VIA STRUCTURE AND METHOD FOR FORMING THE SAME - A method of forming an integrated circuit device includes providing a substrate including an active device, forming a through silicon via into the substrate, forming a device contact to the active device, forming a conductive layer over the through silicon via and the device contact, and forming a connecting via structure for electrically connecting the conductive layer with the through silicon via. An integrated circuit device includes a through silicon via formed into a substrate silicon material, a conductive layer formed over the through silicon via, and a connecting via structure formed between the conductive layer and the through silicon via for electrically connecting the conductive layer with the through silicon via. The connecting via structure comprises a first series of via bars intersected with a second series of via bars. | 10-24-2013 |
20140051233 | METHODS OF THINNING AND/OR DICING SEMICONDUCTING SUBSTRATES HAVING INTEGRATED CIRCUIT PRODUCTS FORMED THEREON - One illustrative method disclosed herein includes forming a plurality of die above a crystalline semiconducting substrate, irradiating and cooling an edge region of the substrate to form an amorphous region in the edge region of the substrate and, after forming the amorphous region, performing at least one process operation to reduce the thickness of the substrate. | 02-20-2014 |
20140070405 | STACKED SEMICONDUCTOR DEVICES WITH A GLASS WINDOW WAFER HAVING AN ENGINEERED COEFFICIENT OF THERMAL EXPANSION AND METHODS OF MAKING SAME - One illustrative device disclosed herein includes a device substrate having a plurality of first die formed adjacent a front side of the device substrate, a glass window wafer attached to a back side of the device substrate, wherein the glass window wafer has a plurality of openings formed therein and a coefficient of thermal expansion that is within plus or minus 200-500% of the coefficient of thermal expansion of the device wafer, and a plurality of second die, each of which is positioned in one of the openings in the glass window wafer and electrically coupled to one of the first die. | 03-13-2014 |
20150076706 | THROUGH-SILICON VIA UNIT CELL AND METHODS OF USE - Exemplary embodiments of the present invention provide a V0 via unit cell with multiple keep out zones. The keep out zones are oriented concentrically and provide support for multiple sizes of through-silicon vias (TSVs). An off-center alignment between the V0 via unit cell and a probe pad is used to improve contact between the V0 vias and a probe pad. During a chip redesign, the TSV size may be changed without the need to revise the V0 mask. | 03-19-2015 |
Patent application number | Description | Published |
20080301402 | Method and System for Stealing Interrupt Vectors - A system for stealing interrupt vectors from an operating system. Custom interrupt handler extensions are copied into an allocated block of memory from a kernel module. Also, operating system interrupt handlers are copied into a reserved space in the allocated block of memory from an interrupt vector memory location. In response to copying the operating system interrupt handlers into the reserved space in the allocated block of memory, custom interrupt handlers from the kernel module are copied over the operating system interrupt handlers in the interrupt vector memory location. The custom interrupt handlers after being copied into the interrupt vector memory location handle all interrupts received by the operating system. | 12-04-2008 |
20110153306 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROCESSOR VERIFICATION USING ABSTRACT TEST CASE - According to one aspect of the present disclosure a method and technique for processor verification using an abstract test case is disclosed. The method comprises identifying a format for an abstract instruction of an abstract test case, selecting an instruction from an instruction pool corresponding to the identified format, and generating a real test case for processor verification by modifying the abstract instruction based on the instruction selected from the instruction pool. | 06-23-2011 |
20110246696 | Interrupt Vector Piggybacking - A hypervisor receives an interrupt that includes a target address and, in turn, branches to an administrating interrupt vector. Next, the administrating interrupt vector determines whether to branch to a piggyback interrupt handler corresponding to a piggyback interrupt vector. Based upon the determination, the hypervisor either branches to the piggyback interrupt handler or to an administrating interrupt handler that corresponds to the administrating interrupt vector. | 10-06-2011 |
20120084538 | Methodology and Framework for Run-Time Coverage Measurement of Architectural Events of a Microprocessor - A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all architectural events discernable from the instructions and architectural state changes are tracked and recorded. A mechanism to ensure capturing of maskable events is also provided. A feedback driven test-generation approach is enabled by the runtime coverage measurement. The runtime coverage measurement system presents a live view of the comprehensive architectural event coverage to the user/tester. The methodology can be implemented on an operating system environment and also as a standalone/bare-metal tool. | 04-05-2012 |
20120324208 | Effective Validation of Execution Units Within a Processor - A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated. | 12-20-2012 |
20130111032 | CLOUD OPTIMIZATION USING WORKLOAD ANALYSIS | 05-02-2013 |
20130111035 | CLOUD OPTIMIZATION USING WORKLOAD ANALYSIS | 05-02-2013 |
20130117588 | Run-Time Task-Level Dynamic Energy Management - A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator. | 05-09-2013 |
20130297258 | Smart Multiplexing of Performance Counters for Performance Measurement - The present disclosure includes, but is not limited to, a method, system and computer-usable medium for improving performance measurement by analyzing the various events in a multiplexing counting mode and configuring the sampling time accordingly to more effectively performing the sampling. In certain embodiments, when groups of operations are identified for sampling, the present disclosure generates a time sampling table for these groups of operations. The time sampling table is dynamically altered during the runtime of the application to alter the sampling interval of each group. The sampling interval of each group can be increased or decreased based on a threshold of occurrence of the event. This disclosure provides more accurate performance measurement of important events and facilitates a determination of how important events impact application performance. | 11-07-2013 |
20140059383 | Effective Validation of Execution Units Within a Processor - A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated. | 02-27-2014 |
20140075219 | Run-Time Task-Level Dynamic Energy Management - A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator. | 03-13-2014 |
20140173222 | Validating Cache Coherency Protocol Within a Processor - A mechanism is provided for effectively validating cache coherency within a processor. For each node in a set of nodes, responsive to a node in a set of nodes being a controlling node, at least one action is performed on each controlled node mapped to the controlling node. After performing the at least one action on each controlled node mapped to the controlling node or responsive to the node failing to be a controlling node, a self-modifying branch test pattern is executed based on the selected execution pattern in the condition register through the set of nodes. Responsive to the self-modifying branch test pattern ending, values output from the execution unit during execution of the self-modifying branch test pattern are compared to a set of expected results. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated. | 06-19-2014 |
20150127984 | Tightly-Coupled Context-Aware Irritator Thread Creation for Verification of Microprocessors - A mechanism is provided for context-aware irritation of a micro-processor. At each executed phase in a set of phases of a test case being executed on a set of micro-processors, a determination is made of a set of characteristics associated with the given executed phase of the test case. Based on the set of determined set of characteristics associated with the given executed phase, a determination is made of an irritation to be executed alongside the given executed phase of the test case. The determined irritation is then executed alongside the given executed phase of the test case. | 05-07-2015 |