Patent application number | Description | Published |
20090103345 | Three-dimensional memory module architectures - Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module comprises at least one memory-controller layer stacked with at least one memory layer. Fine pitched through vias (e.g., through silicon vias) extend approximately perpendicular to a surface of the at least one memory controller through the stack providing electronic communication between the at least one memory controller and the at least one memory layers. Additionally, the memory-controller layer includes at least one external interface configured to transmit data to and from the memory module. Furthermore, the memory module can include an optical layer. The optical layer can be included in the stack and has a bus waveguide to transmit data to and from the at least one memory controller. The external interface can be an optical external interface which interfaces with the optical layer. | 04-23-2009 |
20110113208 | STORING CHECKPOINT DATA IN NON-VOLATILE MEMORY - Methods and systems for storing checkpoint data in non-volatile memory are described. According to one embodiment, a data storage method includes executing an application using processing circuitry and during the execution, writing data generated by the execution of the application to volatile memory. An indication of a checkpoint is provided after writing the data. After the indication has been provided, the method includes copying the data from the volatile memory to non-volatile memory and, after the copying, continuing the execution of the application. The method may include suspending execution of the application. According to another embodiment, a data storage method includes receiving an indication of a checkpoint associated with execution of one or more applications and, responsive to the receipt, initiating copying of data resulting from execution of the one or more applications from volatile memory to non-volatile memory. In some embodiments, the non-volatile memory may be solid-state non-volatile memory. | 05-12-2011 |
20110134930 | PACKET-BASED NETWORKING SYSTEM - One embodiment of the present invention is directed to a networking system comprising a sending device, a receiving device, electronic communications components and transmission media through which the sending device and receiving device exchange data packets, and a networking protocol implemented in executable routines, firmware, hardware, or a combination of two or more of executable routines, firmware, hardware that provides for transmission of data in an ordered set of data packets through a sequence established between the sending device and receiving device as a result of transmitting a first data packet from the sending device to the receiving device and returning an acknowledgement by the receiving device to the sending device. | 06-09-2011 |
20110176804 | Method And Systems For Implementing High-radix Switch Topologies On Relatively Lower-radix Switch Physical Networks - Embodiments of the present invention are directed to implementing high-radix switch topologies on relatively lower-radix physical networks. In one embodiment, the method comprises constructing the physical network ( | 07-21-2011 |
20110280579 | ENERGY-EFFICIENT AND FAULT-TOLERANT RESONATOR-BASED MODULATION AND WAVELENGTH DIVISION MULTIPLEXING SYSTEMS - Systems and methods are provided for modulating, channels in dense wavelength division multiplexing (“DWDM”) systems. In one aspect, a modulation and wavelength division multiplexing system includes a channel source and a waveguide tree structure disposed on a substrate. The tree structure includes waveguides branching from a root waveguide. The waveguides include two or more terminus waveguides coupled to the channel source. The system also includes one or more modulator arrays disposed on the substrate. Each modulator array is optically coupled to one of the two or more terminus waveguides and is configured to modulate channels injected into a terminus waveguide from the channel source to produce corresponding optical signals that propagate from the terminus waveguide along one or more of the waveguides to the root waveguide. | 11-17-2011 |
20110286743 | FLOW-CONTROL METHODS AND SYSTEMS FOR MULTIBUS SYSTEMS - Methods and systems are provided that prevent buffer overflow in multibus systems. In one aspect, a method for controlling the flow of data in a multibus system includes, for each node having an associated broadcast bus in the multibus system, generating status information regarding available data storage space of each receive buffer of the node. The method includes broadcasting the status information to the other nodes connected to the broadcast bus and collecting status information regarding the available storage space of receive buffers of the other nodes connected to the broadcast bus. The method also includes determining whether or not to send data from the node to at least one of the other nodes over the broadcast bus based on the collected status information. | 11-24-2011 |
20120020242 | METHODS AND APPARATUS TO DETERMINE AND IMPLEMENT MULTIDIMENSIONAL NETWORK TOPOLOGIES - Methods and apparatus to determine and implement multidimensional network topologies are disclosed. An example method disclosed herein comprises receiving an input parameter for determining a multidimensional network topology for a network interconnecting a plurality of devices, and determining a set of multidimensional network topologies, each multidimensional network topology of the set comprising a respective plurality of nodes to interconnect the plurality of devices, each node in each multidimensional network topology of the set being fully connected with all neighbor nodes in each dimension of the multidimensional network topology, and each multidimensional network topology of the set satisfying a first constraint based on the input parameter. | 01-26-2012 |
20120059983 | PREDICTOR-BASED MANAGEMENT OF DRAM ROW-BUFFERS - A method for managing memory includes storing a history of accesses to a memory page, and determining whether to keep the memory page open or to close the memory page based on the stored history. A memory system includes a plurality of memory cells arranged in rows and columns, a row buffer, and a memory controller configured to manage the row buffer at a per-page level using a history-based predictor. A non-transitory computer readable medium is also provided containing instructions therein, wherein the instructions include storing an access history of a memory page in a lookup table, and determining an optimal closing policy for the memory page based on the stored histories. The histories can include access numbers or access durations. | 03-08-2012 |
20120105177 | RESONATOR SYSTEMS AND METHODS FOR TUNING RESONATOR SYSTEMS - Tunable resonator systems and methods for tuning resonator systems are disclosed. In one aspect, a resonator system includes an array of resonators disposed adjacent to a waveguide, at least one temperature sensor located adjacent to the array of resonators, and a resonator control electronically connected to the at least one temperature sensor. Each resonator has a resonance frequency in a resonator frequency comb and channels with frequencies in a channel frequency comb are transmitted in the waveguide. Resonance frequencies in the resonator frequency comb are to be adjusted in response to ambient temperature changes detected by the at least one temperature sensors to align the resonance frequency comb with the channel frequency comb. | 05-03-2012 |
20130058607 | OPTICAL INTERCONNECT FABRICS AND OPTICAL SWITCHES - Optical interconnect fabrics and optical switches are disclosed. In one aspect, an optical interconnect fabric comprises one or more bundles of optical broadcast buses. Each optical broadcast bus is optically coupled at one end to a node and configured to transmit optical signals generated by the node. The optical fabric also includes a number of optical tap arrays distributed along each bundle of optical broadcast buses. Each optical tap array is configured to divert a portion of the optical power associated with the optical signals carried by a bundle of optical broadcast buses to one of the nodes. | 03-07-2013 |
20130251378 | TWO-PHASE OPTICAL COMMUNICATION METHODS AND OPTICAL BUS SYSTEMS FOR IMPLEMENTING THE SAME - Various embodiments of the present invention are directed to methods and systems for transmitting optical signals from a source to a plurality of receiving devices. In one method embodiment, an optical enablement signal is transmitted from the source to the plurality of receiving devices. The target receiving device responds to receiving the optical enablement signal by preparing to receive one or more optical data signals. The source transmits the one or more optical data signals to the target receiving device. The remaining receiving devices do not receive the one or more optical data signals. | 09-26-2013 |
20140040518 | MEMORY INTERFACE - The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing as read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation. | 02-06-2014 |
20140173170 | MULTIPLE SUBARRAY MEMORY ACCESS - A multiple subarray-access memory system is disclosed. The system includes a plurality of memory chips, each including a plurality of subarrays and a memory controller in communication. with the memory chips, the memory controller to receive a memory fetch width (“MFW”) instruction during an operating system start-up and responsive to the MFW instruction to fix a quantity of the subarrays that will be activated in response to memory access requests. | 06-19-2014 |