| Patent application number | Description | Published |
|---|
| 20100088047 | POWER CONVERTER DISABLE VERIFICATION SYSTEM AND METHOD - A power electronics device with an improved IGBT protection mechanism is provided. More specifically, systems and methods are provided for shortening the duration of a shutdown test pulse, such that the power output to the load is substantially unaffected. | 04-08-2010 |
| 20100123420 | MOTOR CONTROLLER HAVING INTEGRATED COMMUNICATIONS CONFIGURATIONS - A motor drive is provided that includes a control circuit or board and a one or more functional circuits or option boards coupled to the control board, and a profile that includes a configuration for the option board. A method of operating a motor drive that includes loading a profile for a option board coupled to a control board of the controller, wherein the profile comprises a configuration for the option board. A tangible machine-readable medium implementing the method is also provided. | 05-20-2010 |
| 20100123422 | MOTOR CONTROLLER WITH DETERMINISTIC SYNCHRONOUS INTERRUPT HAVING MULTIPLE SERIAL INTERFACE BACKPLANE - In one embodiment, a motor drive is provided that includes a control board and one or more option boards coupled to the control board via one or more serial interfaces such that data from the one or more option boards is communicated via one or more synchronous interrupts on the one or more serial interfaces. A method of operating a motor drive that includes transmitting one or more signals from an option board to a control board via one or more synchronous interrupts, wherein the option board is coupled to the control board via a serial interface. A tangible machine-readable medium implementing the method is also provided. | 05-20-2010 |
| 20100123423 | SERIAL INTERFACE MOTOR CONTROLLER HAVING USER CONFIGURABLE COMMUNICATIONS SPEEDS - In one embodiment, a motor drive is provided that includes a control board and an option board coupled to the control board via a serial interface, wherein the option board includes a configurable data transfer rate. A method of operating a motor drive that includes configuring a transfer rate of an option board coupled to a control board via a serial interface. A tangible machine-readable medium implementing the method is also provided. | 05-20-2010 |
| 20100123424 | MOTOR CONTROLLER WITH INTEGRATED SERIAL INTERFACE HAVING SELECTABLE SYNCHRONIZATION AND COMMUNICATIONS - In one embodiment, a motor drive is provided that includes a control board and a plurality of option boards configured to communicate with the control board via one or more serial interfaces, wherein the one or more serial interfaces are configured to transfer one or more synchronized signals from each option board. A method of operating a motor drive that includes transferring data between a control board and a plurality of option boards over one or more serial interfaces, wherein the transfer of data from each option board is synchronized with the plurality of option boards. A tangible machine-readable medium implementing the method is also provided. | 05-20-2010 |
| 20100123425 | MOTOR DRIVE SYNCHRONIZATION SYSTEM AND METHOD - Multiple motor drives are synchronized to permit complex coordination in operation. Each motor drive includes a control circuit coupled to functional circuits that are separately supported and linked to the control circuit via dedicated serial interfaces. The control circuit generates interrupts for coordinated transfer and collection of data from all functional circuits. Each drive includes a synchronization counter, and all synchronization counters are linked via a network link. The synchronization counters synchronized clocks of each control circuit. The interrupts, and consequent data transfer and collection are thus synchronized between all drives based on the synchronization of the clocks. | 05-20-2010 |
| 20120013283 | PARALLEL POWER INVERTER MOTOR DRIVE SYSTEM - Multiple inverter motor drives are interconnected in parallel to provide a common output to a motor. Common control circuitry is coupled to all parallel drives via optical cables and provides signals to power layer circuitry of each inverter for generation, at the power layer, of timing for gate drive signals for the respective inverter power electronic switches. The resulting timing exhibits a high degree of synchronicity such that very little imbalance occurs in the outputs of the paralleled drives, resulting in very low circulating currents. | 01-19-2012 |
| 20120013284 | PARALLEL MOTOR DRIVE DISABLE VERIFICATION SYSTEM AND METHOD - Systems and methods are provided for performing diagnostic testing for multiple motor drives operating in parallel. In one embodiment, the diagnostic testing may involve determining which of the multiple motor drives are in operation and communicating the active configuration of motor drives to testing circuitry. The testing circuitry generates an enable input signal transmitted to the transistor gates in each of the active motor drives. The testing circuitry also generates a power supply input signal transmitted to a DC to DC converter in each of the active motor drives. The responses to the enable input signal and the power supply input signal are measured to determine safety compliance. | 01-19-2012 |
| 20120013372 | POWER LAYER GENERATION OF INVERTER GATE DRIVE - Techniques include systems and methods of synchronizing multiple parallel inverters in a power converter system. In one embodiment, control circuitry is connected to a power layer interface circuitry at each of the parallel inverters, via an optical fiber interface. The system is synchronized by transmitting a synchronizing pulse to each of the inverters. Depending on the operational mode of the system, different data exchanges may occur in response to the pulse. In an off mode, power up and power down data may be exchanged between the control circuitry and the inverters. In an initiating mode, identification data may be transmitted from the inverters to the control circuitry. In an active mode, control data may be sent from the control circuitry to the inverters. In some embodiments, the inverters also transmit feedback data and/or acknowledgement signals to the control circuitry. Power layer circuitry of the inverter adjusts a local clock based upon sampled data from the control circuitry to maintain synchronicity of the inverters between synchronization pulses. | 01-19-2012 |
