| Patent application number | Description | Published |
|---|
| 20080203539 | Semiconductor Components With Conductive Interconnects - A semiconductor component includes a semiconductor substrate having at least one conductive interconnect on the backside thereof bonded to an inner surface of a substrate contact. A stacked semiconductor component includes multiple semiconductor components in a stacked array having bonded connections between conductive interconnects on adjacent components. An image sensor semiconductor component includes a semiconductor substrate having light detecting elements on the circuit side, and conductive interconnects on the backside. | 08-28-2008 |
| 20080206990 | Methods For Fabricating Semiconductor Components With Conductive Interconnects - A system for fabricating semiconductor components includes a semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components. | 08-28-2008 |
| 20080229573 | System For Fabricating Semiconductor Components With Conductive Interconnects - A system for fabricating semiconductor components includes a semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components. | 09-25-2008 |
| 20080308910 | SEMINCONDUCTOR DEVICE INCLUDING THROUGH-WAFER INTERCONNECT STRUCTURE - Semiconductor devices including through-wafer interconnects are disclosed. According to an embodiment of the present invention, a semiconductor device may comprise a substrate having a first surface and a second, opposing surface, and a through-wafer interconnect extending into the first surface of the substrate. The through-wafer interconnect may include an electrically conductive material extending from the first surface of the substrate to the second, opposing surface of the substrate. The through-wafer interconnect may also include a first dielectric material disposed between the electrically conductive material and the substrate and extending from the second, opposing surface of the substrate to the first portion of the conductive material. Additionally, the through-wafer interconnect may include a second dielectric material disposed over a portion of the electrically conductive material and exhibiting a surface that defines a blind aperture extending from the first surface toward the second, opposing surface. | 12-18-2008 |
| 20090068791 | Method For Fabricating Stacked Semiconductor Components - A semiconductor component includes a carrier and multiple semiconductor substrates stacked and interconnected on the carrier. The carrier includes conductive members bonded to corresponding conductive openings on the semiconductor substrates. The component can also include terminal contacts on the carrier in electrical communication with the conductive members, and an outer member for protecting the semiconductor substrates. A method for fabricating the component includes the steps of providing the carrier with the conductive members, and providing the semiconductor substrates with the conductive openings. The method also includes the step of aligning and placing the conductive openings on the conductive members, and then bonding the conductive members to the conductive openings. A system includes the carrier having the conductive members, the semiconductor substrates having the conductive openings, an aligning and placing system for aligning and placing the semiconductor substrates on the carrier, and a bonding system for bonding the conductive members to the conductive openings. | 03-12-2009 |
| 20090155949 | MICROELECTRONIC IMAGERS WITH OPTICAL DEVICES AND METHODS OF MANUFACTURING SUCH MICROELECTRONIC IMAGERS - Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports. | 06-18-2009 |
| 20090243012 | ELECTROMAGNETIC INTERFERENCE SHIELD STRUCTURES FOR SEMICONDUCTOR COMPONENTS - A microelectronic device assembly with an integrated conductive shield is disclosed herein. The microelectronic device assembly includes a semiconductor substrate, an integrated circuit carried by the semiconductor substrate, a dielectric encapsulant encasing at least a portion of the semiconductor substrate. The microelectronic device assembly also includes a conductive shield in direct contact with at least a portion of the dielectric encapsulant and an interconnect extending through the semiconductor substrate and in direct contact with the conductive shield. | 10-01-2009 |
| 20090243051 | INTEGRATED CONDUCTIVE SHIELD FOR MICROELECTRONIC DEVICE ASSEMBLIES AND ASSOCIATED METHODS - Microelectronic device assemblies having integrated conductive shields are disclosed herein. The microelectronic device assemblies include a semiconductor substrate having a bond site and a solder ball electrically connected to the bond site, a dielectric sidewall at least partially encapsulating the semiconductor substrate, and a conductive shield in direct contact with the sidewall and in electrical communication with the solder ball and the bond site. | 10-01-2009 |
| 20100047934 | Method For Fabricating Semiconductor Component Having Encapsulated Through Wire Interconnect (TWI) - A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate. | 02-25-2010 |
| 20100144139 | Methods For Fabricating Semiconductor Components With Conductive Interconnects Having Planar Surfaces - A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from the backside to the substrate contact, and then bonding the conductive interconnect to an inner surface of the substrate contact. | 06-10-2010 |
| 20100252915 | MICROELECTRONIC DEVICE WAFERS AND METHODS OF MANUFACTURING - Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched. | 10-07-2010 |
| 20100264423 | Thinned Semiconductor Components Having Lasered Features And Methods For Fabricating Semiconductor Components Using Back Side Laser Processing - A method for fabricating semiconductor components includes the steps of providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side; thinning the substrate from the back side to a selected thickness; laser processing the back side of the thinned substrate to form at least one lasered feature on the back side; and dicing the substrate into a plurality of components having the lasered feature. The lasered feature can cover the entire back side or only selected areas of the back side, and can be configured to change electrical properties, mechanical properties or gettering properties of the substrate. A semiconductor component includes a thinned semiconductor substrate having a back side and a circuit side containing integrated circuits and associated circuitry. The semiconductor component also includes at least one lasered feature on the back side configured to provide selected electrical or physical characteristics for the substrate. | 10-21-2010 |
| 20100264521 | Semiconductor Component Having Through Wire Interconnect (TWI) With Compressed Wire - A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact. | 10-21-2010 |
| 20100327462 | METHODS FOR WAFER-LEVEL PACKAGING OF MICROFEATURE DEVICES AND MICROFEATURE DEVICES FORMED USING SUCH METHODS - Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known good microelectronic dies to a carrier substrate in a desired arrangement. In several embodiments, for example, the first dies can be releasably attached to an attachment feature on the carrier substrate. The method can also include attaching one or more second known good microelectronic dies to the individual first dies in a stacked configuration to form a plurality of stacked devices. The method further includes at least partially encapsulating the stacked devices and separating the stacked devices from each other. | 12-30-2010 |
| 20110024745 | System With Semiconductor Components Having Encapsulated Through Wire Interconnects (TWI) - A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate. | 02-03-2011 |
| 20110074043 | METHOD OF FORMING VIAS IN SEMICONDUCTOR SUBSTRATES AND RESULTING STRUCTURES - Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from an active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from a back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by laser ablation or drilling from the back surface of the substrate followed by dry etching to complete the through via. | 03-31-2011 |
| 20110089539 | PACKAGED MICROELECTRONIC IMAGERS AND METHODS OF PACKAGING MICROELECTRONIC IMAGERS - Methods for forming electrically conductive through-wafer interconnects in microelectronic devices and microelectronic devices are disclosed herein. In one embodiment, a microelectronic device can include a monolithic microelectronic substrate with an integrated circuit has a front side with integrated circuit interconnects thereon. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad. | 04-21-2011 |
| 20110095429 | METHODS FOR FABRICATING AND FILLING CONDUCTIVE VIAS AND CONDUCTIVE VIAS SO FORMED - Methods for forming conductive vias include foiling one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof A barrier layer may be fowled over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed. | 04-28-2011 |
| 20110136336 | METHODS OF FORMING CONDUCTIVE VIAS - Methods of forming a conductive via may include forming a blind via hole partially through a substrate, forming an aluminum film on surfaces of the substrate, removing a first portion of the aluminum film from some surfaces, selectively depositing conductive material onto a second portion of the aluminum film, and exposing the blind via hole through a back side of the substrate. Methods of fabricating a conductive via may include forming at least one via hole through at least one unplated bond pad, forming a first adhesive over at least one surface of the at least one via hole, forming a dielectric over the first adhesive, forming a base layer over the dielectric and the at least one unplated bond pad, and plating nickel onto the base layer. | 06-09-2011 |
