| Patent application number | Description | Published |
|---|
| 20080294728 | Service Discovery for Electronic Messaging Clients - An autodiscovery service for clients in an electronic messaging system is disclosed. Client devices in the system request messaging system configuration settings from an autodiscover server. Clients may derive the address of the autodiscover server from user input, such as an email address, or the address may be obtained by other means. The autodiscover server responds to the request with settings for that client. The settings requested may include addresses of electronic mail servers and other servers that provide client services. The autodiscover server may determine the settings for the client based on various criteria, including client location and user mailbox location. Third party servers may participate in the autodiscovery service, and addresses of third party servers may be included in the settings provided to the client devices. | 11-27-2008 |
| 20090282095 | DYNAMIC POSTBACK FOR LOCATION CODE EXECUTION - Architecture that introduces evaluation and decisionmaking (e.g., at the server) and allows a runtime decision to be made, on a per-request basis, as to where the data calculations will occur, on the server, on the client, or as a shared execution on both the server and the client. The decision can be made based on environment variables (e.g., permissions, network bandwidth, server load, etc.) of the user, for example. This approach provides performance tuning of a form by dynamically optimizing the location of execution of the code based on environment factors. | 11-12-2009 |
| Patent application number | Description | Published |
|---|
| 20080285326 | HIGH DENSITY NON-VOLATILE MEMORY ARRAY - A high-density non-volatile memory array. In one aspect of the invention, a memory array circuit includes a plurality of word lines, a plurality of bit-lines, and a plurality of memory cell transistors. The gate of each memory cell transistor is connected to one of the word lines, and the drains and sources of each memory cell transistor are connected only to the bit-lines. | 11-20-2008 |
| 20090303769 | ROM ARRAY WITH SHARED BIT-LINES - Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits. | 12-10-2009 |
| 20100315855 | ROM ARRAY WITH SHARED BIT-LINES - Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits. | 12-16-2010 |
| 20100315856 | HIGH-DENSITY NON-VOLATILE READ-ONLY MEMORY ARRAYS AND RELATED METHODS - In an embodiment, a read-only memory array includes a plurality of word lines, a plurality of bit-lines including first and second bit-lines, and a plurality of memory cells configured to represent data values. Each memory cell can include a transistor having a control terminal coupled to one of the plurality of word lines, a drain terminal, and a source terminal. Connections associated with the drain and source terminals of a particular memory cell can determine a data value represented by the memory cell. The memory cells of the plurality of memory cells that are coupled to less than two bit-lines are configured to represent one values. | 12-16-2010 |
