| Patent application number | Description | Published |
|---|
| 20080281961 | NETWORK DELAY ANALYSIS INCLUDING PARALLEL DELAY EFFECTS - A multi-functional graphical user interface facilitates the analysis and assessment of application delays, including delays that occur on multiple paths. A trace file of an application's network events is processed to categorize the causes of delays incurred in the propagation and processing of these events. The system identifies the amount of delay (‘component delay’) that can be eliminated by eliminating each of the components of delay individually, as well as the amount of delay (‘parallel delay’) that can be eliminated by eliminating combinations of the delay components. A user interface displays the amount of reduction that can be achieved by eliminating each component delay individually and the amount of reduction that can be achieved by eliminating combinations of the individual component delays. To facilitate the analysis and assessment of these potential reductions, the interface allows the user to ‘drill down’ to view the individual delay components contained in each combination forming the parallel delays. In this manner, the user is provided a view of each of the delay components that would need to be addressed, either individually or in combination, to improve the overall application delay. | 11-13-2008 |
| 20090052333 | TRAFFIC INDEPENDENT SURVIVABILITY ANALYSIS - First-order effects of hypothesized fault conditions are determined by propagating discrete test packets between select nodes and noting the change of path, if any, taken by the test packet under each condition relative to the fault-free path. Tools are provided to create classes of node pairs of interest, and test packets are created only for select classes. The network is analyzed to identify fault conditions that are likely to impact system performance, and only these fault conditions are simulated. By providing a methodology for selecting classes of node pairs to test, and prioritizing the faults to simulate, a first-order survivability analysis of large networks can be performed efficiently and effectively. The efficiency of this technique is also enhanced by providing test packets that are representative of a wide range of possible source-destination combinations, and by evaluating only the source-destination combinations that may be directly affected by each fault condition. | 02-26-2009 |
| Patent application number | Description | Published |
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| 20100172195 | ULTRA-LOW-POWER VARIATION-TOLERANT RADIATION-HARDENED CACHE DESIGN - A random access memory (RAM) cell provides a control section and a storage section coupled to the storage section. The storage section includes complementary metal-oxide semiconductor (CMOS) transistors and the storage section is read by precharging the control section to a virtual drain voltage. | 07-08-2010 |
| 20100176841 | SEU TOLERANT ARBITER - Single Event Upset (SEU, also referred to as soft error) tolerant arbiters, bare arbiters, and filters are disclosed. An arbiter provides a filter section, and a bare arbiter, coupled to the filter section. The bare arbiter includes a redundant first input and a redundant second input, and a redundant first output and a redundant second output. A pull-down transistor in the bare arbiter conditionally overpowers a corresponding pull-up transistor in the bare arbiter when a contention condition is present in the bare arbiter. | 07-15-2010 |
| 20100283502 | ASYNCHRONOUS NANO-ELECTRONICS - Asynchronous nanoelectronic circuits that operate according to principles of quasi-delay insensitive design are described. Circuit or logic elements comprising n-type devices are fabricated in a first n-plane, p-type devices are fabricated in a p-plane, and connections are formed in a routing plane of a compute tile. A state-holding element comprising a selected one of a C-element, a precharge function-block, and a read-write register is described. The state-holding element can hold a value of an output of a logic element during a time when the output is disconnected from a reference voltage. Isochronic forks having an adversary path designed to make state transitions safe are explained. | 11-11-2010 |
