| Patent application number | Description | Published |
|---|
| 20100127365 | LEADFRAME-BASED CHIP SCALE SEMICONDUCTOR PACKAGES - Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages comprise a leadframe supporting a die that contains a discrete device. The chip scale semiconductor device also contains and an interconnect structure that also serves as a land for the package. The leadframe contains a topset feature adjacent a die attach pad supporting the die, a configuration which provides a connection to the interconnect structure as well as the backside of the die. This leadframe configuration provides a maximum die size to be used in the chip scale semiconductor packages while allowing them to be used in low power and ultra-portable electronic devices. Other embodiments are described. | 05-27-2010 |
| 20100127380 | LEADFRAME FREE LEADLESS ARRAY SEMICONDUCTOR PACKAGES - Leadframe-free semiconductor packages and methods for making and using the same are described. The semiconductor packages contain an interconnect structure comprising an array of land pads. The interconnect structure is formed from and routed using a printable or wirebondable conductive material and is not formed using any etching procedure. A solderable mask covers the interconnect structure except for the land pads. A die containing an integrated circuit device is connected to the interconnect structure by either a wirebonding process or by a flipchip process. The land pad arrays can contain a solder connector, such as a solder ball or bump, that can be used to connect the semiconductor package to a printed circuit board. Other embodiments are described. | 05-27-2010 |
| 20110121453 | SEMICONDUCTOR SYSTEM-IN-PACKAGE AND METHOD FOR MAKING THE SAME - Semiconductor devices that contain a system in package and methods for making such packages are described. The semiconductor device with a system in package (SIP) contains a first IC die, passive components, and discrete devices that are contained in a lower level of the package. The SIP also contains a second IC die that is vertically separated from the first IC die by an array of metal interposers, thereby isolating the components of the first IC die from the components of the second IC die. Such a configuration provides more functionality within a single semiconductor package while also reducing or eliminating local heating in the package. Other embodiments are also described. | 05-26-2011 |
