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Akyol

Bora Akyol, San Jose, CA US

Patent application numberDescriptionPublished
20080205403Network packet processing using multi-stage classification - Methods and systems for processing packets in data network using multistage classification are disclosed. An example method for processing packets includes receiving a data packet at a first processing stage and examining the packet at the first processing stage to determine a first attribute of the packet. Based on the first attribute, a first classification is assigned to the packet. In the example method, the packet and the first classification are communicated from the first processing stage to a second processing stage and the packet is examined at the second processing stage to determine a second attribute of the packet. Based on the second attribute, a second classification is assigned to the packet. The example method further includes processing the packet based on the first classification and the second classification.08-28-2008
20080219162METHOD AND SYSTEM FOR CONTROLLING NETWORK ACCESS ON A PER-FLOW BASIS - Aspects of a method and system for controlling network access on a per-flow basis may comprise controlling access to a network by regulating at least one flow comprising one or more ingress packets based on a flow identifier associated with said one or more packets and based on an establishment of flows in said network. The flow identifier may comprise a source IP address, a destination IP address, a source MAC address, a destination MAC address, a network protocol, a source port number, and/or a destination port number. The number of flows permitted for a source and/or a rate at which a source is allowed to establish new flows may be limited. Flows that exceed one or more of these limits may be marked for further processing. Access to the network for the marked flows may be determined based on past and/or present network statistics. Flows received when a node is at capacity may also be marked for processing.09-11-2008
20080298397COMMUNICATION FABRIC BANDWIDTH MANAGEMENT - Methods and apparatus for communication fabric bandwidth management are disclosed. An example method includes receiving data at a first network entity, where the data being received from a second network entity. The example method further includes, at the first network entity, queuing the received data in a data queue associated with the second network entity. The example method still further includes determining that an amount of queued data in the data queue associated with the second network entity exceeds a first threshold. In response to the first threshold being exceeded, a first control message is communicated from the first network entity to the second network entity. In the example method, in response to the first control message, a data rate at which the second network entity sends data to the first network entity is reduced.12-04-2008
20100115174PCI Express Load Sharing Network Interface Controller Cluster - Embodiments provide load balancing in a virtual computing environment comprising a plurality of PCI-Express switches (the PCIe switching cloud) coupled to a plurality of network interface devices (NICs). An NIC cluster is added between the PCIe switching cloud and the NICs. The NIC cluster is configured to hide NICs from system images and allow the system images to access functions across multiple NICs. The NIC cluster of an embodiment dynamically load balances network resources by performing a hashing function on a header field of received packets. The NIC cluster of an embodiment performs load balancing and state management in association with driver software, which is embedded in the system image. The driver software adds a tag for flow identification to downstream data packets. The NIC cluster distributes data packets based on information in the tag.05-06-2010

Bora Akyol, Sunnyvale, CA US

Patent application numberDescriptionPublished
20090164694UNIVERSAL ROUTING IN PCI-EXPRESS FABRICS - A universal routing identifier (URID) is provided to extend the function space in PCI-Express fabrics. Methods and systems based on the URID are provided for configuring URID capable devices and upgrading PCI-Express bridges and switches having lookup tables with access control functionality. The lookup table entry contains URIDs of destination ports, backup ports, acceptance ports, and permitted ports for downstream and upstream filtering, routing and arbitrating of transaction packets. URID capable devices can be incrementally added to current PCI-Express bridges and switches. A configuration mechanism is added to the current PCI/PCI-Express enumeration software. The URID capabilities can be disabled to maintain system compatibility. A URID capable PCI-Express system is able to address ten of thousands single-function devices. A URID capability segment field is provided in the current PCI-Express configuration space. Each URID capable device contains the URID capability segment implemented in its own set of configuration space registers.06-25-2009

Hasan Akyol, Newport Beach, CA US

Patent application numberDescriptionPublished
20100194443dB-LINEAR VOLTAGE-TO-CURRENT CONVERTER - A dB-linear voltage-to-current (V/I) converter that is amenable to implementation in CMOS technology. In a representative embodiment, the dB-linear V/I converter has a voltage scaler, a current multiplier, and an exponential current converter serially connected to one another. The voltage scaler supplies an input current to the current multiplier based on an input voltage. The current multiplier multiplies the input current and a current proportional to absolute temperature and supplies the resulting current to the exponential current converter. The exponential current converter has a differential MOSFET pair operating in a sub-threshold mode and generating an output current that is proportional to a temperature-independent, exponential function of the input voltage.08-05-2010