Patent application number | Description | Published |
20090101885 | Method of producing phase change memory device - An area where a lower electrode is in contact with a variable resistance material needs to be reduced in order to lower the power consumption of a variable resistance memory device. The present invention provides a method of producing a variable resistance memory element whereby the lower electrode can be more finely formed. The method of producing a semiconductor device according to the present invention includes forming a small opening by utilizing cubical expansion due to the oxidation of silicon. Thereby forming the lower electrode smaller than that can be formed by lithography techniques. | 04-23-2009 |
20090104779 | Method of producing phase change memory device - An area where a lower electrode is in contact with a variable resistance material needs to be reduced to lower the power consumption of a variable resistance memory device. The present invention is to provide a method of producing a variable resistance memory element whereby the lower electrode can be formed smaller. Combining an anisotropic etching process with an isotropic etching process enables the lower electrode to be formed smaller. | 04-23-2009 |
20090221146 | Nonvolatile memory device and manufacturing method for the same - The object of the present invention is to provide a manufacturing method for a nonvolatile memory device including a variable resistance having a constricted shape. The nonvolatile memory device of the present invention has a storage section composed of two electrodes and a variable resistance sandwiched between the electrodes. The variable resistance is formed to a constricted shape between the electrodes. | 09-03-2009 |
20100078616 | NONVOLATILE MEMORY DEVICE AND MANUFACTURING PROCESS THEREOF - A nonvolatile memory device has a first insulating layer, a variable resistance layer provided on the first insulating layer and having a variable resistance material, and a first electrode and second electrode electrically connected with the variable resistance layer. The variable resistance layer has a variable resistance region as a data storing region and a thickness-changing region continuously extending from the variable resistance region and gradually becoming thicker from the variable resistance region. | 04-01-2010 |
20100123114 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device ( | 05-20-2010 |
20100195415 | Semiconductor memory device and reading method therefor - A memory device is configured such that, in a read access: a first switch and a second switch are turned on in a pre-charge period before a memory cell is accessed so that charges of a bit line charge voltage generating circuit are distributed to a bit line and a reference bit line, to thereby charge the bit line and the reference bit line to an initial voltage. After the charge, a selected memory cell is connected to the bit line, the reference bit line is connected to a reference voltage generating circuit, and a voltage differential type sense amplifier amplifies a difference voltage between a voltage of the bit line decreased by discharge of the selected memory cell and a voltage of the reference bit line generated by the reference voltage generating circuit, to thereby read out memory cell data. | 08-05-2010 |
20110214025 | Control method of non-volatile semiconductor device - Disclosed is a control method of a non-volatile semiconductor device including cells, wherein a stress for rewriting information is applied to each of the cells, and each cell has a first time period as a period of time until a characteristic of the cell is stabilized to expectation value information after the stress for rewriting information is applied, a plurality of first sequences, in each of which writing is performed to a plurality of the cells continuously in time series, and a plurality of second sequences, in each of which verification of a plurality of the cells is performed continuously in time series, after the writing performed continuous in time series. When repeating, continuously in time series, a plurality of sets, each of the sets comprising a plurality of the first sequences and a plurality of the second sequences, a period of time from completion of application of the stress to each of the cells in the first sequence until start of the verification in the second sequence for the each of the cells subjected to the stress application, is arranged for each of all of the sets, wherein the period of time is the first time period or more. | 09-01-2011 |
20120257437 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second interconnects, a variable resistance element that may assume a first resistance value or a second resistance value in response to the current flowing therein, and second transistors connected between the first and second interconnects in series with each other on both sides of the variable resistance element, and a power supply circuit unit that delivers the power supply to a control electrode of the first transistor. The power supply circuit unit supplies the power of a first power supply when the variable resistance element is to make transition to the first resistance value and the power supply circuit unit supplies the power of a second power supply when the variable resistance element is to make transition to the second resistance value, thereby allowing transitioning of the resistance values of the variable resistance element | 10-11-2012 |
20130088911 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor memory device includes a writing circuit and a reading circuit. The writing circuit executes a setting action for converting a resistance of a variable resistance element to a low resistance by applying current from one end side to the other end side of a memory cell via the variable resistance element, and a resetting action for converting the resistance to a high resistance by applying current from the other end side to the one end side via the variable resistance element. The reading circuit executes a first reading action for reading a resistance state of the variable resistance element by applying current from one end side to the other end side of the memory cell via the variable resistance element, and a second reading action for reading the resistance state by applying current from the other end side to the one end side via the variable resistance element. | 04-11-2013 |
20140036573 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in a matrix, each memory cell being configured such that a variable resistance element and a selection transistor are connected in series. A set operation for a memory cell (an operation of converting the resistance of the variable resistance element to a low resistance) is performed by applying a set voltage pulse for a longer time than that for a reset operation (an operation of converting the resistance of the variable resistance element to a high resistance) while limiting, using the selection transistor, an electric current flowing in the set operation to a certain low electric current, and by simultaneously applying the set voltage pulse to the plurality of memory cells. | 02-06-2014 |