Patent application number | Description | Published |
20100206841 | Method for etching metal nitride with high selectivity to other materials - A method and system of etching a metal nitride, such as titanium nitride is described. The etching process comprises introducing a process composition having a halogen containing gas, such as Cl | 08-19-2010 |
20110039416 | Method for patterning an ARC layer using SF6 and a hydrocarbon gas - A method of pattern etching a Si-containing anti-reflective coating (ARC) layer is described. The method comprises etching a feature pattern into the silicon-containing ARC layer using plasma formed from a process gas containing SF | 02-17-2011 |
20110108517 | Deep trench liner removal process - A liner removal process is described, wherein an excess portion of a conformal liner formed in a trench is substantially removed while reducing or minimizing damage to a bulk fill material in the trench. | 05-12-2011 |
20110237084 | Differential metal gate etching process - A method for etching a differential metal gate structure on a substrate is described. The differential metal gate structure includes a metal gate layer overlying a high dielectric constant (high-k) dielectric layer, wherein the metal gate layer comprises a different thickness at different regions on the substrate. The metal gate layer is patterned by using a plasma etching process, wherein at least one etch step includes forming plasma using a halogen-containing gas and at least one etch step includes forming plasma using an additive gas having as atomic constituents C, H, and F. | 09-29-2011 |
20110318936 | Etch process for reducing silicon recess - A method for selectively etching a substrate is described. The method includes disposing a substrate comprising a silicon nitride (SiN | 12-29-2011 |
20120244458 | ETCH PROCESS FOR CONTROLLING PATTERN CD AND INTEGRITY IN MULTI-LAYER MASKS - A method of patterning a multi-layer mask is described. The method includes preparing a multi-layer mask on a substrate, wherein the multi-layer mask includes a lithographic layer and an intermediate mask layer underlying the lithographic layer, and wherein the intermediate mask layer comprises a carbon-containing compound. The method further includes: establishing an etch process recipe for transferring a pattern, that is formed in the lithographic layer and characterized by an initial pattern critical dimension (CD), to the intermediate mask layer; establishing at least one parametric relationship between an intermediate pattern CD to be formed in the intermediate mask layer and at least one process parameter, wherein the at least one parametric relationship provides process conditions capable of increasing and decreasing the initial pattern CD to the intermediate pattern CD; selecting a target process condition to achieve a target CD adjustment between the initial pattern CD and the intermediate pattern CD; and transferring the pattern from the lithographic layer to the intermediate mask layer using the target process condition. | 09-27-2012 |
20120244693 | METHOD FOR PATTERNING A FULL METAL GATE STRUCTURE - A method of patterning a gate structure on a substrate is described. The method includes preparing a metal gate structure on a substrate, wherein the metal gate structure includes a high dielectric constant (high-k) layer, a first gate layer formed on the high-k layer, and a second gate layer formed on the first gate layer, and wherein the first gate layer comprises one or more metal-containing layers. The method further includes preparing a mask layer with a pattern overlying the metal gate structure, transferring the pattern to the second gate layer, transferring the pattern to the first gate layer, and transferring the pattern in the first gate layer to the high-k layer, and prior to the transferring of the pattern to the high-k layer, passivating an exposed surface of the first gate layer using a nitrogen-containing and/or carbon-containing environment to reduce under-cutting of the first gate layer relative to the second gate layer, wherein the passivating is performed separately from or in addition to the transferring of the pattern to the first gate layer. | 09-27-2012 |
20130052833 | METHOD FOR ETCHING HIGH-K DIELECTRIC USING PULSED BIAS POWER - A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm). | 02-28-2013 |
20130084707 | DRY CLEANING METHOD FOR RECOVERING ETCH PROCESS CONDITION - A method of patterning a substrate is described. The method includes establishing a reference etch process condition for a plasma processing system. The method further includes transferring a mask pattern formed in a mask layer to one or more layers on a substrate using at least one plasma etching process in the plasma processing system to form a feature pattern in the one or more layers and, following the transferring, performing a multi-step dry cleaning process to substantially recover the reference etch condition. Furthermore, the multi-step dry cleaning process includes performing a first dry cleaning process step using plasma formed from a first dry clean process composition containing an oxygen-containing gas, and performing a second dry cleaning process step using plasma formed from a second dry clean process composition containing a halogen-containing gas. | 04-04-2013 |
20130306598 | SIDEWALL IMAGE TRANSFER METHOD FOR LOW ASPECT RATIO PATTERNS - A method for patterning a substrate is described. The patterning method may include conformally depositing a material layer over a pattern according to a conformal deposition process, selectively depositing a second material layer on an exposed surface of the material layer according to a selected deposition process recipe; partially removing the material layer using a plasma etching process to expose a top surface of the pattern, open a portion of the material layer at a bottom region between adjacent features of the pattern, and retain a remaining portion of the material layer on sidewalls of the pattern; and removing the pattern using one or more etching processes to leave a final pattern comprising the remaining portion of the material layer and the second layer. | 11-21-2013 |
20140256149 | METHOD FOR ETCHING HIGH-K DIELECTRIC USING PULSED BIAS POWER - A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm). | 09-11-2014 |
20140357084 | MITIGATION OF ASYMMETRICAL PROFILE IN SELF ALIGNED PATTERNING ETCH - A method which is particularly advantageous for improving a Self-Aligned Pattern (SAP) etching process. In such a process, facets formed on a spacer layer can cause undesirable lateral etching in an underlying layer beneath the spacer layer when the underlying layer is to be etched. This detracts from the desired vertical form of the etch. The etching of the underlying layer is performed in at least two steps, with a passivation layer or protective layer formed between the etch steps, so that sidewalls of the underlying layer that was partially etched during the initial etching are protected. After the protective layer is formed, the etching of the remaining portions of the underlying layer can resume. | 12-04-2014 |
20140370717 | ETCH PROCESS FOR REDUCING DIRECTED SELF ASSEMBLY PATTERN DEFECTIVITY - Provided is a method for preparing a patterned directed self-assembly layer, comprising: providing a substrate having a block copolymer layer comprising a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer; and performing an etching process to selectively remove the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the surface of the substrate, the etching process being performed at a substrate temperature less than or equal to about 20 degrees C. The method further comprises providing a substrate holder for supporting the substrate, the substrate holder having a first temperature control element for controlling a first temperature at a central region and second temperature control element at an edge region of the substrate and setting a target value for the first and the second temperature. | 12-18-2014 |
20140370718 | ETCH PROCESS FOR REDUCING DIRECTED SELF ASSEMBLY PATTERN DEFECTIVITY USING DIRECT CURRENT POSITIONING - A method for preparing a patterned directed self-assembly layer for reducing directed self-assembly pattern defectivity using direct current superpositioning is provided. A substrate having a block copolymer layer overlying a first intermediate layer, said block copolymer layer comprising a first phase-separated polymer defining a first pattern and a second phase-separated polymer defining a second pattern in said block copolymer layer is provided. A first plasma etching process using plasma formed of a first process composition to remove said second phase-separated polymer while leaving behind said first pattern of said first phase-separated polymer is performed. A second plasma etching process to transfer said first pattern into said first intermediate layer using plasma formed of a second process composition is performed. In an embodiment, said first phase-separated polymer is exposed to an electron beam preceding, during, or following said first plasma etching process, or preceding or during said second plasma etching process. | 12-18-2014 |