| Patent application number | Description | Published |
|---|
| 20090066390 | TIMING CONTROL CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE - Disclosed is a timing control circuit which receives a first clock having a period T | 03-12-2009 |
| 20090085550 | Constant current source circuit - A constant current source circuit is constituted of a control voltage generation section which detects the output voltage at the output terminal so as to generate a control voltage, a reference current adjustment section which adjust a reference current based on the control voltage, and a current mirror section which outputs the output current responsive to the adjusted reference current at the output terminal. This reduces variations of the output current due to variations of the output voltage; hence, the constant current source circuit can precisely operate in a low-voltage region. | 04-02-2009 |
| 20090086551 | Semiconductor device - Disclosed is a semiconductor device in which In case a data group output from a first output pin in a first word configuration is output from the first output pin and a second output pin in a second word configuration, and a data group output from a third output pin in a first word configuration is output from the third output pin and a fourth output pin in a second word configuration, the second output pin is arranged adjacent to the first output pin, and the fourth output pin is arranged adjacent to the third output pin. | 04-02-2009 |
| 20090096523 | Differential amplification circuit - A differential amplification circuit is constituted of a differential transistor pair including a pair of n-channel MOS transistors whose sources are connected together, a constant current source circuit which is connected to the sources of the differential transistor pair, a current-mirror load circuit including a pair of p-channel MOS transistors whose gates are connected together, and a bias generation circuit which generates a gate bias voltage and a drain bias voltage applied to the current-mirror load circuit in such a way that the same potential is set to both the drains of the p-channel MOS transistors. Thus, it is possible to reduce the input offset voltage without reducing the margin of operation voltage and without increasing the overall chip size. | 04-16-2009 |
| 20090102524 | TIMING CONTROL CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE - Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1. The fine delay circuit comprises L-number of multiphase clock control delay circuits disposed in parallel, delays by n·T2/L the timing of sampling of the coarse timing signal by respective clocks of the group of L-phase second clocks, and takes the OR among the resulting delayed pulses to thereby produce the fine timing signal. | 04-23-2009 |
| 20090146716 | Timing control circuit, timing generation system, timing control method and semiconductor memory device - A timing control circuit DLY | 06-11-2009 |
| 20090189590 | BAND-GAP REFERENCE VOLTAGE SOURCE CIRCUIT - A band-gap reference voltage source circuit is constituted of a diode-pair circuit connected to a reference voltage output terminal, a first differential amplifier including a first transistor and a first operational amplifier, and a second differential amplifier including a second transistor and a second operational amplifier. The second differential amplifier operates based on a bias voltage, which is lower than a predetermined voltage, so as to forcedly pull up the level of the reference voltage output terminal via the second transistor before the first differential amplifier starts to pull up the level of the reference voltage output terminal up to the predetermined voltage via the first transistor. | 07-30-2009 |
| 20100052644 | BANDGAP REFERENCE CIRCUIT AND METHOD OF STARTING BANDGAP REFERENCE CIRCUIT - In accordance with a bandgap circuit and a method of starting the bandgap circuit, a start signal is continuously supplied to a differential amplifier circuit to start up the differential amplifier circuit that controls a bandgap core circuit until the differential amplifier circuit has started up, and then the supply of the start signal to the differential amplifier circuit is discontinued after the differential amplifier circuit has started up. | 03-04-2010 |
| 20100295618 | DIFFERENTIAL AMPLIFIER, REFERENCE VOLTAGE GENERATING CIRCUIT, DIFFERENTIAL AMPLIFYING METHOD, AND REFERENCE VOLTAGE GENERATING METHOD - A differential amplifier includes a main differential amplifier circuit that receives a pair of input signals and supplies a pair of output signals based on a difference between the input signals; and a bias control differential amplifier circuit that receives the pair of output signals, controls a control terminal of a current-limiting transistor making up the main differential amplifying circuit based on an offset voltage included in the output signals, and reduces the offset voltage. | 11-25-2010 |
| 20110057819 | Semiconductor device having plural semiconductor chips laminated to each other - In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced. | 03-10-2011 |
| 20110084385 | Semiconductor device and information processing system including the same - A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured. | 04-14-2011 |
| 20110093224 | Semiconductor device, semiconductor device testing method, and data processing system - To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal. | 04-21-2011 |
| 20110147945 | SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING GENERATION OF CRACKS IN SEMICONDUCTOR CHIP DURING MANUFACTURING PROCESS - A semiconductor device includes a chip stacked body where a plurality of semiconductor chips are stacked, and penetration electrodes respectively formed in the semiconductor chips are electrically interconnected in stacking order of the semiconductor chips, a first support member that is disposed to face a first semiconductor chip formed in one end of the chip stacked body, and including electrodes electrically connected to the penetration electrodes of the first semiconductor chip, and a wiring board that is disposed to face a second semiconductor chip formed in an end opposed to the one end of the chip stacked body, and including external electrodes on a surface opposed to a surface facing the second semiconductor chip that is to be electrically connected to the penetration electrodes of the second semiconductor chip. | 06-23-2011 |
