Patent application number | Description | Published |
20120126860 | GATE DRIVING CIRCUIT - A highly-reliable gate driving circuit achieved by suppressing the amount of hot-carriers generated in a MOSFET. In the gate driving circuit having NOEMI circuits, same-type NOEMI circuits are connected in series with a p-channel MOSFET constituting a gate charging circuit and an n-channel MOSFET constituting a gate discharging circuit, respectively, so as to suppress the amount of hot-carriers generated in the p-channel MOSFET and the n-channel MOSFET. | 05-24-2012 |
20130328104 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is disclosed which has a high voltage isolation structure that is a RESURF structure, wherein it is possible to reduce a displacement current generated by dV/dt noise, and a method of manufacturing the semiconductor device. It is possible to increase a lateral resistance without changing the total amount of electric charges in the uppermost surface p-type diffusion layer by using an uppermost surface p-type diffusion layer configuring a double-RESURF structure being formed so that high concentration regions with a deep diffusion depth and low concentration regions with a shallow diffusion depth are alternately arranged adjacent to each other. As a result, it is possible to reduce a displacement current generated by dV/dt noise. | 12-12-2013 |
20140145763 | GATE DRIVING CIRCUIT - A gate driving circuit for driving an insulated gate switching element, including a gate charging circuit configured to charge gate capacitance of the insulated gate switching element, and a gate discharging circuit that is connected in series with the gate charging circuit and configured to discharge a charge of the gate capacitance. The gate charging circuit includes a first p-channel metal oxide semiconductor field effect transistor (MOSFET), and a first hybrid normally-on enhancement MOSFET insertion (NOEMI) circuit connected in series with a drain of the first p-channel MOSFET. The gate discharging circuit includes a first n-channel MOSFET, and a second hybrid NOEMI circuit connected in series with a drain of the first n-channel MOSFET. | 05-29-2014 |
20140346633 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a high voltage isolation structure having a double RESURF structure. The high voltage isolation structure separates a low potential region from a high potential region. The high voltage isolation structure has an annular strip shape in a plan view and includes a straight portion and a corner portion which is connected to the straight portion. In the high voltage isolation structure, a p-type RESURF region is formed in a surface layer of a front surface of a substrate in an n-type well region along the outer circumference of the n-type well region. In the corner portion, the total amount of impurities per unit area in the RESURF region is less than that in the straight portion. | 11-27-2014 |
20150021711 | SEMICONDUCTOR DEVICE - A p diffusion region is selectively provided in a surface layer of an n | 01-22-2015 |
20150102457 | SEMICONDUCTOR DEVICE - A polysilicon resistor includes a high resistance conductor, a low resistance conductor adjacent to one end portion of the high resistance conductor, and a low resistance conductor adjacent to the other end portion of the high resistance conductor. Of the high resistance conductor, a width of a first place reacting most actively when a current flows into a polysilicon fuse is narrowest. Of the high resistance conductor, a width of a second place serving as an interface with each of the low resistance conductors is widest. The width of the high resistance conductor increases gradually from the first place toward the second place. | 04-16-2015 |
20150255454 | SEMICONDUCTOR DEVICE | 09-10-2015 |
20150380400 | SEMICONDUCTOR DEVICE - A semiconductor device provides reduced size and increased performance, and includes a semiconductor layer having a surface layer including first and second semiconductor regions connected to first and second potentials, respectively; a third semiconductor region provided inside the first semiconductor region and connected to a third potential; a fourth semiconductor region provided inside the second semiconductor region and connected to the third potential; a plurality of a first element provided in each of the first, second, third, and fourth semiconductor regions; a first isolation region provided between and in contact with the first and second semiconductor regions, electrically connected to the semiconductor layer, and connected to a fourth potential; and a second isolation region which encloses the periphery of and maintains a withstand voltage of the first and second semiconductor regions. The third and fourth potentials are lower than the second potential, which is lower than the first potential. | 12-31-2015 |