| Patent application number | Description | Published |
|---|
| 20090072804 | TRIMMING CIRCUIT - A trimming circuit which comprises a shunt circuit having two shunt resistors and two shunt ON/OFF switches and connected in parallel with a series resistor circuit. The middle point of the shunt circuit is connected to a connection point of the series resistor circuit, the resistance ratio thereof with respect to the connection point being equal to the resistance ratio of the shunt resistors. | 03-19-2009 |
| 20090072893 | VOLTAGE SUPPLY CIRCUIT - A voltage supply circuit which conducts a current from a power supply into a current supply line comprises a plurality of current drive circuits connected in parallel to the current supply line each of which conducts current from the power supply into the current supply line. Different reference voltages are respectively given to the plurality of current drive circuits, each of which compares a comparison voltage corresponding to a generated voltage developed across load resistors with the respective reference voltage and, when the comparison voltage exceeds the respective reference voltage, stops supplying current. | 03-19-2009 |
| 20090089633 | Semiconductor Testing Apparatus and Method - The present invention provides a semiconductor testing apparatus and method capable of reliably determining whether a semiconductor memory is good or bad. A “1” reading test of each cell corresponding to one bit at a first step is first performed on a memory cell array. “0” writing of each cell corresponding to one bit at a second step and a “0” reading test of each cell corresponding to one bit at a third step are executed on the memory cell array. Thus, the time taken from the supply of power to the start of the “0” reading test of the reference cell at the third step can be significantly shortened. As a result, a defect of a reference bit line due to a breaking or high resistance of a gate of a reference column switch transistor corresponding to a normally ON transistor can be screened. | 04-02-2009 |
| 20100246283 | REFERENCE POTENTIAL GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY - There is provided a reference potential generating circuit of a semiconductor memory, including: a first MOS transistor group that includes a plurality of first MOS transistors that are connected in series; a second MOS transistor that is connected in series to the first MOS transistor group; a third MOS transistor that is connected in parallel to the circuit in which the first MOS transistor group and the second MOS transistor are connected in series, has a gate connected to a connection point of the first MOS transistor group and the second MOS transistor, and corrects a reference potential from a connection point of the first MOS transistors; and a fourth MOS transistor that is connected to the gate of the third MOS transistor, and decreases the potential of the gate of the third MOS transistor when a permission signal to supply power to the semiconductor memory is input. | 09-30-2010 |
| 20100246306 | START-UP CIRCUIT OF INTERNAL POWER SUPPLY OF SEMICONDUCTOR MEMORY - There is provided a start-up circuit of an internal power supply of a semiconductor memory, including: an odd number of inverters that are connected in series and output a signal indicating whether or not to start to supply power from an internal power supply circuit of the semiconductor memory to an internal power supply circuit, and a discharge unit that is connected to an output side of an inverter at an odd-numbered stage and discharges charges remaining at the connection point between the inverter at the odd-numbered stage and the inverter at the stage immediately thereafter, after supply of power to operate the inverters is stopped. | 09-30-2010 |
| 20100246307 | INTERNAL POWER SUPPLY CONTROL CIRCUIT OF SEMICONDUCTOR MEMORY - An internal power supply control circuit of a semiconductor memory includes a periodic signal generating unit that generates a periodic signal to generate a permission signal to intermittently permit supply of power from an internal power supply circuit of the semiconductor memory to an internal circuit thereof with a predetermined period, when a mode changes from a normal operation mode where power is always supplied from the internal power supply circuit to the internal circuit to a standby mode where consumption power is further suppressed as compared with consumption power in the normal operation mode, and a permission signal output unit that outputs the permission signal synchronized with the periodic signal to the internal power supply circuit, when a mode signal indicating any mode of the normal operation mode and the standby mode and the periodic signal are input and the input mode signal indicates the standby mode. | 09-30-2010 |
| 20110181329 | SEMICONDUCTOR DEVICE AND PULSE WIDTH DETECTION METHOD - An internal pulse waveform shaping circuit provided to an IC chip generates an internal pulse monitor signal that changes in a predetermined direction at a rise timing of an internal pulse signal during a period in which a first enable signal is asserted and a second enable signal is de-asserted and then continues in the changed state for a predetermined period of time or longer, and generates the internal pulse monitor signal that changes in the predetermined direction at a fall timing of the pulse signal during a period in which the first enable signal is de-asserted and the second enable signal is asserted and then continues in the changed state for the predetermined period of time or longer. The generated internal pulse monitor signal is output to a tester for detecting the pulse width of the internal pulse signal. | 07-28-2011 |
| 20110185239 | SEMICONDUCTOR TESTING APPARATUS AND METHOD - The present invention provides a semiconductor testing apparatus and method capable of reliably determining whether a semiconductor memory is good or bad. A “1” reading test of each cell corresponding to one bit at a first step is first performed on a memory cell array. “0” writing of each cell corresponding to one bit at a second step and a “0” reading test of each cell corresponding to one bit at a third step are executed on the memory cell array. Thus, the time taken from the supply of power to the start of the “0” reading test of the reference cell at the third step can be significantly shortened. As a result, a defect of a reference bit line due to a breaking or high resistance of a gate of a reference column switch transistor corresponding to a normally ON transistor can be screened. | 07-28-2011 |
