| Patent application number | Description | Published |
|---|
| 20080264588 | Method of Making Medium Density Fiberboard - The present invention provides a method for producing an MDF board from pulp from a fibrous lignocellulose material using a treatment or pretreatment step which exposes the material to oxalic acid or oxalic acid derivatives (particularly dialkyl ester derivatives, particularly in the vapor phase). The treated wood is then subjected to a sugar extraction wash and refined using any one of the several pulping methods to produce a final pulp product. Once this is done the pulp is used to make MDF boards having improved water repellency properties. | 10-30-2008 |
| 20090194243 | Method for Treating Lignocellulosic Materials - The present invention is a method for producing a pulp from a fibrous lignocellulose material or source using a treatment or pretreatment step which exposes the material to oxalic acid derivatives, particularly dialkyl ester derivatives, particularly in the vapor phase. Once treated, the material may be refined using any one of the several pulping methods to produce a final pulp product and the production of the product is accompanied by strength increases in paper made from the pulp and energy savings in making the pulp, hi addition the treatment or pretreatment produces a soluble carbohydrate source and other components (e.g. acetic acid, other wood components) for further product development. In certain cases a pulp product is not produced and all of the carbohydrate present in the lignocellulose is converted into soluble sugars. | 08-06-2009 |
| 20100300634 | METHOD OF MAKING MEDIUM DENSITY FIBERBOARD - The present invention provides a method for producing an MDF board from pulp from a fibrous lignocellulose material using a treatment or pretreatment step which exposes the material to oxalic acid or oxalic acid derivatives (particularly dialkyl ester derivatives, particularly in the vapor phase). The treated wood is then subjected to a sugar extraction wash and refined using any one of the several pulping methods to produce a final pulp product. Once this is done the pulp is used to make MDF boards having improved water repellency properties. | 12-02-2010 |
| Patent application number | Description | Published |
|---|
| 20090235987 | Chemical Treatments to Enhance Photovoltaic Performance of CIGS - The present invention provides method of treating semiconductor surfaces (e.g., CIGS) using various solvents (including ionic solvents and eutectics), and methods preparing photovoltaic cells comprising treated CIGS materials. | 09-24-2009 |
| 20090255582 | METHODS OF DRYING GLASS FOR PHOTOVOLTAIC APPLICATIONS - This invention relates generally to methods of dehydrating glass substrates for use in photovoltaic modules, suitably by reacting moisture on the glass with organosilicon compounds. The invention also relates to methods of preparing thin film photovoltaic modules, which include dehydration of the glass substrates used in the manufacture of the photovoltaic modules. | 10-15-2009 |
| 20090293943 | Silicon Film Deposition Method Utilizing a Silent Electric Discharge - A method for depositing a silicon film on a substrate includes a step of flowing a first silicon-containing gaseous composition through an electric discharge generated to form a second silicon-containing composition that is different than the first silicon-containing composition. The second composition is directed into a deposition chamber to form a silicon-containing film on one or more substrates positioned within the deposition chamber. The formation of crystalline silicon is controlled by the temperature of the deposition. | 12-03-2009 |
| 20090301551 | Silicon Film Deposition Method Utilizing a Silent Electric Discharge and an Active Species - A method for depositing a silicon film on a substrate includes a step of flowing a first silicon-containing gaseous composition through an electric discharge generated to form a second silicon-containing composition that is different than the first silicon-containing composition. The second composition is directed into a deposition chamber to form a silicon-containing film on one or more substrates positioned within the deposition chamber. The formation of crystalline silicon is controlled by the temperature of the deposition. Optionally, an activated hydrogen-containing composition is introduced into the deposition chamber during film deposition. The activated hydrogen-containing composition is formed by exposing hydrogen gas to microwave radiation. | 12-10-2009 |
| Patent application number | Description | Published |
|---|
| 20080264559 | TOP COATING FOR INDOOR AND OUTDOOR TEMPORARY REMOVABLE GRAPHICS AND SYSTEM AND METHOD FOR MAKING, APPLYING AND REMOVING SUCH GRAPHICS - A composition for a removable top coating for protecting the exposed face of a temporary removable graphic is provided. A remover for the transferred graphic image is provided that completely dissolves the temporary removable graphic, but does not affect the commonly encountered substrates such as concrete, brick, wooden floors, asphalt surfaces, terrazzo and motor vehicle body surfaces, marine and aeronautical craft surfaces. A method for making, applying and removing the temporary removable graphic is provided. | 10-30-2008 |
| 20080268140 | TEMPORARY REMOVABLE SOLVENT BASED PROTECTIVE COATING - This invention is for a composition of clear or pigmented coating that is temporary and removable. It is especially designed to protect the surface of an automobile from the damaging effects of the environment and also from damage caused by normal daily use. The coating is a composition of 40 to 80% of cellulose acetate butyrate ester, 15 to 60% of an acrylic polymer and 2 to 10% of a sucrose acetate isobutyrate. The remover is a combination of tetrahydrofurfuryl alcohol, dibasic ester, diacetone alcohol, ethyl 3 ethoxypropionate; 2,2,4 trimethyl-1,3 pentanoldiol monoisobutyrate, and white mineral oil. | 10-30-2008 |
| 20120149812 | TOP COATING FOR INDOOR AND OUTDOOR TEMPORARY REMOVABLE GRAPHICS AND SYSTEM AND METHOD FOR MAKING, APPLYING AND REMOVING SUCH GRAPHICS - A composition for a removable top coating for protecting the exposed face of a temporary removable graphic is provided. A remover for the transferred graphic image is provided that completely dissolves the temporary removable graphic, but does not affect the commonly encountered substrates such as concrete, brick, wooden floors, asphalt surfaces, terrazzo and motor vehicle body surfaces, marine and aeronautical craft surfaces. A method for making, applying and removing the temporary removable graphic is provided. | 06-14-2012 |
| Patent application number | Description | Published |
|---|
| 20090167429 | METHODOLOGY FOR ASSESSING DEGRADATION DUE TO RADIO FREQUENCY EXCITATION OF TRANSISTORS - One embodiment relates to an on-chip power amplifier (PA) test circuit. In one embodiment, a PA test circuit comprises a controllable oscillator (CO) configured to generate a radio frequency (RF) signal, a parallel resonant circuit tuned to the radio frequency, a pre-power amplifier (PPA) coupled to the CO and the parallel resonant circuit, the PPA configured to amplify and drive the RF signal from an output of the PPA into a load. The test circuit may further comprise a first transmission gate configured to couple the RF signal from the CO to an input of the PPA. One testing methodology for a PA test circuit comprises stressing the PPA with an RF signal, measuring a characteristic of the PPA, determining stress degradation from the characteristic measurements, and repeating the stressing and characteristic measurements until a maximum stress degradation is achieved or a maximum stress has been applied. | 07-02-2009 |
| 20100061481 | CURRENT CANCELING VARIABLE GAIN AMPLIFIER AND TRANSMITTER USING SAME - A current canceling CMOS variable gain amplifier includes a first leg and a second leg. The first leg has a first input line, a first output line, a first ON transistor, a first control transistor and a first subtracting transistor. The second leg has a second input line, a second output line, a second ON transistor, a second control transistor and a second subtracting transistor. The second input line can provide a second input current. The second output line can provide a second output current. The first input line is arranged to provide a first input current to each of the first ON transistor, the first control transistor and the first subtracting transistor. The second input line is arranged to provide a second input current to each of the second ON transistor, the second control transistor and the second subtracting transistor. The first output line is in electrical connection with each of the first ON transistor, the first control transistor and the second subtracting transistor. The second output line is in electrical connection with each of the second ON transistor, the second control transistor and the first subtracting transistor. | 03-11-2010 |
| 20110124306 | CURRENT CANCELING VARIABLE GAIN AMPLIFIER AND TRANSMITTER USING SAME - A current canceling CMOS variable gain amplifier includes a first leg and a second leg. The first leg has a first input line, a first output line, a first ON transistor, a first control transistor and a first subtracting transistor. The second leg has a second input line, a second output line, a second ON transistor, a second control transistor and a second subtracting transistor. The second input line can provide a second input current. The second output line can provide a second output current. The first input line is arranged to provide a first input current to each of the first ON transistor, the first control transistor and the first subtracting transistor. The second input line is arranged to provide a second input current to each of the second ON transistor, the second control transistor and the second subtracting transistor. The first output line is in electrical connection with each of the first ON transistor, the first control transistor and the second subtracting transistor. The second output line is in electrical connection with each of the second ON transistor, the second control transistor and the first subtracting transistor. | 05-26-2011 |
| 20110199972 | Wireless Chip-to-Chip Switching - Embodiments of the invention provide a system and method for chip to chip communications in electronic circuits. A router or switch receives data packets at input port ASICs. A routing table on the input port ASIC or on a routing ASIC is used to identify a destination port ASIC based upon header information in the data packet. The data packet is transmitted from the input port ASIC to the destination port ASIC using millimeter wave signals that are transmitted across a waveguide or a wireless interface. | 08-18-2011 |
| 20120056297 | BALUNS FOR RF SIGNAL CONVERSION AND IMPEDANCE MATCHING - A magnetically-coupled structure is integrated with an integrated circuit in back end-of-line (BEOL) digital CMOS fabrication processes. A differential primary (or secondary) coil is formed by patterning a thick copper (Cu) metal layer, and a single-ended secondary (or primary) coil is formed by patterning a thick aluminum (Al) top metal bonding layer. Crossovers and/or cross-unders are formed using thin metal layers. One embodiment provides a stacked balun with a differential primary input winding defined in the copper layer, directly underneath a single-ended spiral winding defined in the aluminum layer. The spiral forms the single-ended secondary output of the balun and is rotated by 90° to prevent metal shorting for its cross-under connections. Another embodiment provides a transformer with one differential primary (or secondary) coil defined in the copper layer and another differential secondary (or primary) coil defined in the aluminum layer and adding a center tap. The position of the tap is selected to compensate for phase differences and provide desired balance. | 03-08-2012 |
| 20120068890 | HIGH SPEED DIGITAL INTERCONNECT AND METHOD - In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth. | 03-22-2012 |
| 20120068891 | CHIP TO DIELECTRIC WAVEGUIDE INTERFACE FOR SUB-MILLIMETER WAVE COMMUNICATIONS LINK - In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth. | 03-22-2012 |
| 20120086505 | SWITCHING CORE LAYOUT - Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection. | 04-12-2012 |
| 20120098069 | NEUTRALIZATION CAPACITANCE IMPLEMENTATION - Neutralization capacitances are commonly employed to compensate for the Miller effect; however, at higher frequencies, the parasitic inductance introduced in the interconnect can affect the neutralization. Here, a layout has been provided where a MOS capacitor is merged with a complementary transistor. By having this merged device, the layout is compact and reduces interconnect area, which reduces the effects of parasitic inductance at higher frequencies (i.e., millimeter wave or terahertz). This layout can also be used to implement linearity enhancement schemes. | 04-26-2012 |
