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Akamatsu, Tokyo

Hidenori Akamatsu, Tokyo JP

Patent application numberDescriptionPublished
20090237755DEVICE, APPARATUS, AND METHOD OF CONTROLLING OPTICAL SCANNING DEVICE - A device, apparatus, and method of controlling operation of scanning performed by an optical scanning device are disclosed such that the color images are not shifted in the sub-scanning direction even when thinning processing is performed.09-24-2009

Patent applications by Hidenori Akamatsu, Tokyo JP

Hiroshi Akamatsu, Tokyo JP

Patent application numberDescriptionPublished
20090115493Electric fuse determination circuit and determination method - An electrical fuse determination circuit that can speedily and reliably incorporate an electrical fuse data and improve a reliability of electrical fuse device, includes a first electrical fuse device of which one end connects with a higher voltage, a second electrical fuse device of which one end connects with a lower voltage, a set portion that puts one of the first electrical fuse device and the second electrical fuse device in a conductive state, and a determination portion that determines a voltage level of a predetermined contact point connecting the other end of the first electrical fuse device and the other end of the second electrical fuse device.05-07-2009
20100195416Anti-fuse circuit and semiconductor memory device - An anti-fuse circuit uses first to fifth power supplies which have first to fifth power supply voltages, respectively, in the order of highest to lowest during writing. The anti-fuse circuit includes: a first level shift circuit which is connected to the second to fourth power supplies and which converts a first logic signal that changes between the third and fourth power supply voltages into a second logic signal that changes between the second and fourth power supply voltages; a second level shift circuit which is connected to the first, second, and fourth power supplies and which converts the second logic signal into a third logic signal that changes between the first and fourth power supply voltages; a transistor having a source connected to the first power supply and a gate connected to the third logic signal; and an anti-fuse element having one end connected to the drain of the transistor and the other end connected to the fifth power supply.08-05-2010
20110133808APPARATUS - An apparatus has a delay circuit, a delay control circuit which detects the delay time of the delay circuit and generates a delay adjustment signal based upon the detection result, and a delay adjustment circuit operable to adjust delay time of the delay circuit in response to the delay adjustment signal.06-09-2011

Patent applications by Hiroshi Akamatsu, Tokyo JP

Hirotaka Akamatsu, Tokyo JP

Patent application numberDescriptionPublished
20080285072Printing apparatus and printing method - A printer includes a print document receiving unit 11-20-2008

Katsuya Akamatsu, Tokyo JP

Patent application numberDescriptionPublished
20100176684DYNAMOELECTRIC MACHINE - An AC generator comprises a shaft, a rotor secured to the shaft, a stator with a stator core provided to surround the outer circumference of the rotor and having a plurality of slots formed to extend in the axial direction while spaced apart in the circumferential direction, and a front bracket and a rear bracket surrounding the stator core while clamping the circumferential edge portion of the stator core from the opposite sides in the axial direction using a plurality of clamping means. A pair of front stays formed in the front bracket are secured to a vehicle by means of bolts penetrating a pair of through holes formed, respectively, in the pair of front stays. The pair of through holes are formed at such positions as the perpendicular bisector of a line connecting the centers intersects the axis of the shaft, and one clamping means is provided on the shaft side perpendicular bisector. With such an arrangement, generation of magnetic noise can be prevented without increasing the weight of the bracket and thereby the overall weight.07-15-2010

Masahiro Akamatsu, Tokyo JP

Patent application numberDescriptionPublished
20080225363OPTICAL DEFLECTOR AND OPTICAL DEVICE - An optical deflector includes a plurality of piezoelectric unimorph oscillating bodies (09-18-2008

Shinji Akamatsu, Tokyo JP

Patent application numberDescriptionPublished
20120125006GAS TURBINE COMBUSTOR AND GAS TURBINE - In a gas turbine combustor and a gas turbine, an air passage (05-24-2012

Takeshi Akamatsu, Tokyo JP

Patent application numberDescriptionPublished
20080209005INFORMATION PROCESSING SYSTEM, OPERATION MANAGEMENT METHOD FOR COMPUTER SYSTEMS, AND PROGRAM IN A DISTRIBUTED NETWORK ENVIRONMENT - An operation management system capable of simultaneously detecting and managing, in a computer distributed processing environment, employs physical location information about locations where computers are located and logical location information of software programs running on the computers. Physical location information of a network connection device, such as a network switch, is described in a master data library or the like in advance, and is created as configuration items and discovered by a software dependency discovery unit. Configuration items stored in a configuration management database are associated with the configuration items for the physical location information. Preferably, the physical location information is configured as structured data. This makes it possible to establish hierarchical associations between configuration items for the physical location information.08-28-2008
20080209430SYSTEM, APPARATUS, AND METHOD FOR FACILITATING PROVISIONING IN A MIXED ENVIRONMENT OF LOCALES - A system, a computer program product, and a method capable of dynamically and flexibly support a plurality of locales upon provisioning are provided. A management server connected via a network to a plurality of processing resources each set with a locale includes a storage unit to store processing, a locale, and a set of instructions corresponding to the processing and the locale, and a selection unit to select a set of instructions associated with required processing and a required locale by referring to the storage unit, and it further includes a determination unit to dynamically determine the required processing and the processing resource by way of provisioning, and the storage unit stores the plurality of processing resources and each locale.08-28-2008
20100037217COMPUTER PROGRAM PRODUCT FOR EVALUATING THE WORKLOADS OF INSTALLATION PLANS IN QUANTITY BY BUILDING A PRE-REQUISITE RELATION KNOWLEDGE-BASE - A first embodiment of the invention includes a computer program product including machine executable instructions stored on machine readable media, the instructions for providing an installation plan for installing at least one application in at least one processing system, by implementing a method including: loading a configuration management database (CMDB) including pre-requisite relations knowledge base and a configuration information database with workload information and skill information for installation of the at least one application; and using the loaded information to select the installation plan. In another embodiment, a system is provided.02-11-2010

Wado Akamatsu, Tokyo JP

Patent application numberDescriptionPublished
20110250684METHOD FOR PRODUCING NEURAL STEM CELLS - In order to provide a method for producing neural stem cells easily and quickly by inducing differentiation of somatic cells directly into neurospheres, dedifferentiation factors are introduced into somatic cells, which are then cultured in suspension in the presence of growth factors to produce the neurospheres, thereby allowing the neural stem cells to be produced quickly without establishing iPS cells.10-13-2011

Yasuhiko Akamatsu, Tokyo JP

Patent application numberDescriptionPublished
20090263945MANUFACTURING METHOD OF CMOS TYPE SEMICONDUCTOR DEVICE, AND CMOS TYPE SEMICONDUCTOR DEVICE - The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.10-22-2009

Patent applications by Yasuhiko Akamatsu, Tokyo JP