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Akagawa, Tokyo
Etsutaro Akagawa, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20080288825 | STORAGE SUBSYSTEM, STORAGE SYSTEM, AND COMMUNICATION CONTROL METHOD - In a storage subsystem which is connected to an IP network, by excluding an improper packet, security is heightened, and a performance of communication to a logical unit of storage subsystem is maintained and secured. In the storage subsystem, a function which carries out filtering of a packet other than an iSCSI packet is provided. With respect to only the packet passed through the function, its accessibility to the logical unit is filtered. Also, traffic of all received packets, and a traffic lob of a packet judged to be discarded by the above filtering is recorded. By using this information, controlling such as a cut-off process of improper communication, QoS securement for normal communication and so on, are carried out. | 11-20-2008 |
Hiroyuki Akagawa, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20100035164 | MASK BLANK SUBSTRATE, MASK BLANK, EXPOSURE MASK, MASK BLANK SUBSTRATE MANUFACTURING METHOD, AND SEMICONDUCTOR MANUFACTURING METHOD - In a mask blank substrate to be chucked by a mask stage of an exposure system, the flatness of a rectangular flatness measurement area excluding an area of 2 mm inward from an outer peripheral end surface on a main surface of the mask blank substrate on its side to be chucked by the mask stage is 0.6 μm or less, and at least three of four corner portions of the flatness measurement area each have a shape that rises toward the outer peripheral side. | 02-11-2010 |
| 20100173232 | MASK BLANK PROVIDING SYSTEM, MASK BLANK PROVIDING METHOD, MASK BLANK TRANSPARENT SUBSTRATE MANUFACTURING METHOD, MASK BLANK MANUFACTURING METHOD, AND MASK MANUFACTURING METHOD - A mask blank manufacturing department manufactures a mask blank by forming a thin film to be a mask pattern on a mask blank transparent substrate. When providing the mask blank to a mask manufacturing department, the mask blank manufacturing department provides optical characteristic information (transmittance variation) of the mask blank transparent substrate and optical characteristic information (transmittance variation and/or phase difference variation) of the mask blank to the mask manufacturing department. The optical characteristic information of the mask blank transparent substrate is provided to the mask blank manufacturing department from a materials processing department that manufactures mask blank transparent substrates. | 07-08-2010 |
| 20100248092 | MASK BLANK SUBSTRATE, MASK BLANK, EXPOSURE MASK, MASK BLANK SUBSTRATE MANUFACTURING METHOD, AND SEMICONDUCTOR MANUFACTURING METHOD - In a mask blank substrate to be chucked by a mask stage of an exposure system, the flatness of a rectangular flatness measurement area excluding an area of 2 mm inward from an outer peripheral end surface on a main surface of the mask blank substrate on its side to be chucked by the mask stage is 0.6 μm or less, and at least three of four corner portions of the flatness measurement area each have a shape that rises toward the outer peripheral side. | 09-30-2010 |
Keiko Akagawa, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20100322929 | ANTIGEN PRESENTING CELL TARGETED CANCER VACCINES - The present invention includes compositions and methods for the expression, secretion and use of novel compositions for use as, e.g., vaccines and antigen delivery vectors, to delivery antigens to antigen presenting cells. In one embodiment, the vector is an anti-CD40 antibody, or fragments thereof, and one or more antigenic peptides linked to the anti-CD40 antibody or fragments thereof, including humanized antibodies. | 12-23-2010 |
Masayuki Akagawa, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20090252580 | WAFER PROCESSING APPARATUS WITH WAFER ALIGNMENT DEVICE - A semiconductor-processing apparatus includes: a wafer handling chamber; a wafer processing chamber; a wafer handling device; a first photosensor disposed in the wafer handling chamber in front of the wafer processing chamber at a position where the wafer partially blocks light received by the first photosensor at a ready-to-load position and substantially entirely blocks light received by the first photosensor when the wafer moves from the ready-to-load position toward the wafer processing chamber in the x-axis direction; and a second photosensor disposed in the wafer handling chamber in front of the wafer processing chamber at a position where the wafer does not block light received by the second photosensor at the ready-to-load position and partially blocks light received by the second photosensor when the wafer moves from the ready-to-load position toward the wafer processing chamber in the x-axis direction. | 10-08-2009 |
Takamasa Akagawa, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20110221855 | DUPLEX PRINTING METHOD, BOOKBINDING METHOD, PRINTER FOR USE IN DUPLEX PRINTING METHOD - A method for printing on both sides of a roll sheet including superimposing and pressing a thermal transfer sheet and the roll sheet between a platen roller and a thermal head so that the bottom surface of the thermal transfer sheet touches the top surface of the roll sheet and the bottom surface of the roll sheet touches the platen roller, and printing an image on the top surface of the roll sheet while conveying the sheets; and superimposing and pressing a thermal transfer sheet and the roll sheet between a platen roller and a thermal head so that the top surface of the thermal transfer sheet touches the bottom surface of the roll sheet and the top surface of the roll sheet touches the platen roller, and printing an image on the bottom surface of the roll sheet while conveying the sheets. | 09-15-2011 |
Takeshi Akagawa, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20090080488 | SURFACE EMITTING LASER - A surface emitting laser including a semiconductor substrate, a semiconductor substrate, a first reflector formed on the semiconductor substrate, an active layer formed on the first reflector, a tunnel junction layer formed above a part of the active layer, a semiconductor spacer layer which covers the tunnel junction layer, a second reflector formed on the semiconductor spacer layer in a region above the tunnel junction layer, a first electrode formed in the periphery of the second reflector on the semiconductor spacer layer, and a second electrode electrically connected to a layer lower than the active layer, wherein a layer thickness of the semiconductor spacer layer in the region directly above the tunnel junction layer is thinner than the layer thickness of the semiconductor spacer layer in the region directly below the first electrode. | 03-26-2009 |
| 20100020835 | SURFACE EMITTING LASER - A surface emitting laser is provided with a first multilayer Bragg reflecting mirror including a first layer, a second multilayer Bragg reflecting mirror including a second layer, and an optical resonator unit that is held between these multilayer Bragg reflecting mirrors and includes an active layer. Further, the optical resonator unit contacts with the first layer and second layer respectively. The effective refraction index n | 01-28-2010 |
| 20100034233 | SURFACE-EMISSION TYPE SEMICONDUCTOR LASER - The present invention provides a surface-emission type semiconductor laser wherein an effective length of a cavity is reduced, thereby enabling to realize a higher-speed direct modulation. In the surface-emission type semiconductor laser according to the present invention, when supposing the optical path length (L) of a resonator part relative to a lasing wavelength λ | 02-11-2010 |