| Patent application number | Description | Published |
|---|
| 20080230815 | Mitigation of gate to contact capacitance in CMOS flow - Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics. | 09-25-2008 |
| 20080251864 | STACKED POLY STRUCTURE TO REDUCE THE POLY PARTICLE COUNT IN ADVANCED CMOS TECHNOLOGY - A method for implementing a stacked gate, comprising forming a gate dielectric on a semiconductor body, forming a first layer of gate electrode material on the gate dielectric, forming a second layer of gate electrode material on the first layer of gate electrode material, wherein the grain size distribution of the first layer of gate electrode material is different than the grain size distribution of the second layer of gate electrode material, implanting the first and second gate electrode materials, patterning the first and the second gate electrodes and the gate dielectric, and forming source and drain regions. | 10-16-2008 |
| 20080268603 | TRANSISTOR PERFORMANCE USING A TWO-STEP DAMAGE ANNEAL - A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation. | 10-30-2008 |
| 20080268627 | TRANSISTOR PERFORMANCE USING A TWO-STEP DAMAGE ANNEAL - A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation. | 10-30-2008 |
| 20080315324 | METHOD TO OBTAIN UNIFORM NITROGEN PROFILE IN GATE DIELECTRICS - The present invention, in one aspect, provides a method of manufacturing a microelectronics device | 12-25-2008 |
| 20090170346 | LOW TEMPERATURE POLYSILICON OXIDE PROCESS FOR HIGH-K DIELECTRIC/METAL GATE STACK - A method for preventing oxidation in a high-k dielectric/metal gate stack in the manufacture of an integrated circuit device is disclosed. In a detailed embodiment, a PMOS region stack has nitrided hafnium silicide, tungsten, tantalum nitride and polysilicon layers. An NMOS region stack has nitrided hafnium silicide, tungsten silicide, tantalum nitride and polysilicon layers. A thin polysilicon layer deposited over the stacks is converted to an oxide using a low temperature ultraviolet ozone oxidation process or a plasma nitridation using decoupled plasma nitridation or NH | 07-02-2009 |
