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| 20090258158 | PHOTO ALIGNMENT MATERIAL AND METHOD OF MANUFACTURING DISPLAY SUBSTRATE USING THE SAME - A photo alignment material includes a photo alignment polymer and an organic solvent. The photo alignment polymer is prepared by polymerizing a diamine monomer including at least two photo reactive parts represented by the following Chemical Formula 1. | 10-15-2009 |
| 20100034989 | ALIGNMENT SUBSTRATE, METHOD OF MANUFACTURING THE ALIGNMENT SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE ALIGNMENT SUBSTRATE - An alignment substrate includes a substrate and an alignment layer. The substrate includes a plurality of unit pixel areas. Each of the unit pixel areas includes a plurality of sub-pixel areas arranged in a matrix configuration. The alignment layer is on the substrate and has polymer chains protruding from a surface of the alignment layer. The alignment layer has a plurality of alignment vectors in which the polymer chains are pretilted according to the sub-pixel areas. The alignment vectors corresponding to adjacent sub-pixel areas point in different directions from each other. | 02-11-2010 |
| 20100197186 | PHOTOALIGNMENT MATERIAL AND METHOD OF MANUFACTURING DISPLAY SUBSTRATE USING THE SAME - A photoalignment material and a method of manufacturing of a display substrate using the photoalignment material are disclosed. The photoalignment material includes a photoalignment polymer, a photoalignment additive, and an organic solvent. When the photoalignment additive is used, a side reaction due to ultraviolet (UV) light may be prevented, and the stability of alignment layer may be improved. | 08-05-2010 |
| 20110032464 | LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD FOR THE SAME - A liquid crystal display according to an exemplary embodiment of the present invention includes a first substrate and a second substrate facing each other and a liquid crystal layer formed between the first substrate and the second substrate and including liquid crystal molecules. The liquid crystal layer includes a first sub-region and a second sub-region having different alignment azimuth angles of the liquid crystal molecules, the liquid crystal molecules of the first sub-region are aligned to have a first azimuth angle and a polar angle of less than 90° near the first substrate and are vertically aligned near the second substrate, and the liquid crystal molecules of the second sub-region are aligned to have a second azimuth angle and a polar angle of less than 90° near the second substrate and are vertically aligned near the first substrate. | 02-10-2011 |
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| 20110310548 | SUPPORT ASSEMBLY AND COMPUTER DEVICE HAVING THE SAME - A support assembly which supports a computer device body having a display unit. The support assembly includes a base member which is supported on an installation plane, a shaft which extends in parallel to a plane of the base member, a first support member having one end portion joined to the base member and the other end portion which supports the support, at least one pinion gear which is concentrically joined to the shaft, a second support member including a first support part which supports the computer device body having the display unit, a second support part which extends from the first support part to have a predetermined curvature, and a rack gear which is formed on a plane of the second support part facing the shaft along the extension direction of the second support part and moves according to rotation of the computer device body supported to the first support part. | 12-22-2011 |
| 20120099267 | SUPPORT ASSEMBLY AND COMPUTER DEVICE HAVING THE SAME - A support assembly that supports a device main body to be able to rotate includes a base member supported on an installation surface, a support unit having a predetermined curvature, coupled with the device main body on one side thereof, and reciprocating according to tilting of the device main body between an upright position and a tablet position, a guide rail coupled with the base member on a first side thereof and supported by the support unit on a second side thereof, to guide the reciprocation of the support unit, and an elastic unit connected to the support unit and providing an elastic force to maintain a tilting position of the device main body. A computer device may include the support assembly. The support assembly may support a computer device main body having a display when the computer device main body tilts between the upright position and the tablet position. | 04-26-2012 |
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| 20110171882 | CHEMICAL-MECHANICAL POLISHING APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICES - A chemical-mechanical polishing (CMP) apparatus for manufacturing a semiconductor device. The apparatus includes: a spin chuck for supporting and rotating a semiconductor wafer; a polisher comprising a polishing pad for planarizing a surface of the semiconductor wafer, the polisher moving along the surface of the semiconductor wafer by a polishing arm; and a polisher supporting device for supporting the polisher and maintaining the polisher in a horizontal state, while polishing an edge part of the surface of the semiconductor wafer, in order to improve polishing uniformity of a center part and the edge part of the semiconductor wafer. Accordingly, polishing uniformity of the center part and edge part of the semiconductor wafer may be improved, and a height of the polisher supporting device may be optimized according to a polishing degree. Also, the polisher may be easily supported, wear and tear of the support head may be minimized, and the support head may function as a conditioner. | 07-14-2011 |
| 20110217910 | CHEMICAL MECHANICAL POLISHING APPARATUS - A chemical mechanical polishing apparatus includes a platen having a first region configured to support a wafer, and a second region disposed outside the first region. The chemical mechanical polishing apparatus further includes a polishing pad disposed on the platen, a pad head to which the polishing pad is attached, a slurry supply configured to supply a slurry onto the wafer, and an injection port disposing on the second region of the platen. The injection port is configured to inject a predetermined gas to an edge of a bottom surface of the wafer and toward the outside of the wafer. | 09-08-2011 |
| 20110217911 | POLISHING PAD FOR CHEMICAL MECHANICAL POLISHING PROCESS AND CHEMICAL MECHANICAL POLISHING APPARATUS INCLUDING THE SAME - A chemical mechanical polishing apparatus includes a platen configured to support and rotate a wafer, and a polishing pad facing the platen. The polishing pad includes a body having a groove with a rotational symmetric pattern. | 09-08-2011 |
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| 20100248471 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided is a method for fabricating a semiconductor device, including forming an interconnect structure including first and second interconnects and an insulating material between the first and second interconnects, forming a first mask layer and a second mask layer having a plurality of micropores sequentially on the interconnect structure, coalescing the plurality of micropores in the second mask layer with each other and forming a plurality of first microholes in the second mask layer, forming a plurality of second microholes in the first mask layer using the plurality of first microholes, and removing the insulating material using the first mask layer with the plurality of second microholes as an etch mask so as to form an air-gap between the first and second interconnects. | 09-30-2010 |
| 20110108988 | VIA STRUCTURES AND SEMICONDUCTOR DEVICES HAVING THE VIA STRUCTURES - A via structure may include a first conductive pattern, a buffer pattern, and a second conductive pattern. The first conductive pattern may be on an inner wall of a first substrate and the inner wall may define a via hole passing at least partially through the first substrate. The buffer pattern may be on the first conductive pattern and the buffer pattern may partially fill the via hole. The second conductive pattern may be on a top surface of the buffer pattern in the via hole. | 05-12-2011 |
| 20110136332 | METHODS OF FORMING INTEGRATED CIRCUIT DEVICES WITH CRACK-RESISTANT FUSE STRUCTURES - A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer. | 06-09-2011 |
| 20110241184 | INTEGRATED CIRCUIT DEVICES HAVING SELECTIVELY STRENGTHENED COMPOSITE INTERLAYER INSULATION LAYERS AND METHODS OF FABRICATING THE SAME - An integrated circuit device includes a plurality of stacked circuit layers, at least one of the plurality of circuit layers including a composite interlayer insulation layer including laterally adjacent first and second insulating material regions having different mechanical strengths and dielectric properties and a plurality of circuit components disposed in the composite interlayer insulation layer. The first insulating material region may have a lower dielectric constant and a lower mechanical strength than the second insulating material region such that, for example, the first insulating material region may be positioned near signal lines or other circuit features to reduce capacitance while using the second insulating material region near a location that is susceptible to localized mechanical stress, such as a fuse location, an external connection bonding location or a scribe line location. | 10-06-2011 |
| 20110263117 | APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A method of manufacturing a semiconductor device and an apparatus for manufacturing a semiconductor device in which moisture is removed from a porous low-dielectric layer after a chemical mechanical polishing (CMP) process include formation of a porous low-dielectric layer on a substrate. A metal interconnection is formed on the substrate having the porous low-dielectric layer. The metal interconnection forms a planar surface with the porous low-dielectric layer to fill the openings. Ultraviolet (UV) light is irradiated to the porous low-dielectric layer to remove absorbed moisture from the porous low-dielectric layer. A capping layer is formed on the substrate having the porous low-dielectric layer and the metal interconnection. The capping layer is formed in-situ to prevent additional absorption of moisture. | 10-27-2011 |
| 20110281427 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer. | 11-17-2011 |
| 20120083117 | Method Of Forming Hardened Porous Dielectric Layer And Method Of Fabricating Semiconductor Device Having Hardened Porous Dielectric Layer - Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer. | 04-05-2012 |
| 20120094437 | METHOD OF FORMING THROUGH SILICON VIA OF SEMICONDUCTOR DEVICE USING LOW-K DIELECTRIC MATERIAL - A method of forming through silicon vias (TSVs) includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate. | 04-19-2012 |
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| 20100309705 | Stacked memory devices - A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups. | 12-09-2010 |
| 20110149633 | Memory devices and methods of operating the same - Memory devices and methods of operating the same. A memory cell of a memory device may include a ferroelectric layer and a semiconductor layer bonded to each other. The ferroelectric layer may be of a p-type and the semiconductor layer may be of an n-type. The memory cell may have a switching characteristic due to a depletion region that exists in a junction between the ferroelectric layer and the semiconductor layer. The memory device may be a device writing data using a polarization change of the ferroelectric layer. | 06-23-2011 |
| 20110241989 | Remote touch panel using light sensor and remote touch screen apparatus having the same - A remote touch panel includes a plurality of light sensor cells arranged in two dimensions. Each light sensor cell may include a light-sensitive semiconductor layer and first and second electrodes electrically connected to the light-sensitive semiconductor layer. The remote touch panel may be controlled at a remote distance. For example, a large display apparatus can be easily controlled by using a simple light source device, for example, a laser pointer. | 10-06-2011 |
| 20110261017 | Light sensing circuit, and remote optical touch panel and image acquisition apparatus including the light sensing circuit - Example embodiments are directed to light sensing circuits having a relatively simpler structure by using light-sensitive oxide semiconductor transistors as light sensing devices, and remote optical touch panels and image acquisition apparatuses, each including the light sensing circuits. The light sensing circuit includes a light-sensitive oxide semiconductor transistor in each pixel, wherein the light-sensitive oxide semiconductor transistor is configured as a light sensing device, and a driving circuit that outputs data. The light sensing circuit may have a relatively simple circuit structure including a plurality of transistors in one pixel. As a result, the structure and operation of the light sensing circuit may be simplified. | 10-27-2011 |
| 20110284722 | Light-sensing circuit, method of operating the light-sensing circuit, and light-sensing apparatus employing the light-sensing circuit - Example embodiments are directed to a light-sensing circuit, a method of operating the light-sensing circuit, and a light-sensing apparatus including the light-sensing circuit. The light-sensing circuit includes a light-sensitive oxide semiconductor transistor that senses light; and a switching transistor connected to the light-sensing transistor in series and configured to output data. During a standby time, a low voltage is applied to the switching transistor and a high voltage is applied to the light-sensitive oxide semiconductor transistor, and when data is output, the high voltage is applied to the switching transistor and the low voltage is applied to the light-sensitive oxide semiconductor transistor. | 11-24-2011 |
