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Ahmed, TX
Arshad Ahmed, Dallas, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090282316 | Memory Access in Low-Density Parity Check Decoders - Low Density Parity Check (LDPC) decoder circuitry in which memory resources are realized as single-port memory. The decoder circuitry includes a single port memory for storing log-likelihood ratio (LLR) estimates of input node data states for individual rows of a parity check matrix. The decoder circuitry also includes multiple instances of single-port column sum memories, which store updated LLR estimates for each input node. In each case, the memory resources include logic circuitry that executes at least one write cycle and one read cycle to the memory within each decoder cycle. Because the decoder cycle time is much longer than the necessary memory cycle time, particularly in LDPC decoding, data can be written to and read from single-port memory resources in ample time for the decoding operation. | 11-12-2009 |
Ashraf Ahmed, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080209184 | PROCESSOR WITH RECONFIGURABLE FLOATING POINT UNIT - A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into a single operation, when the full-bit mode is indicated, or multiple operations, when the reduced-bit mode is indicated. | 08-28-2008 |
| 20080209185 | Processor with reconfigurable floating point unit - A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into one or more full-bit operations, when the full-bit mode is indicated, or one or more reduced-bit operations, when the reduced-bit mode is indicated. | 08-28-2008 |
Ijaz Ahmed, Galveston, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090131749 | TISSUE REMOVAL SYSTEM AND METHOD USING REINFORCED LOOP - The present disclosure provides a system and method for removing a tissue that extends from a tissue layer, such as a polyp, lesion, or organ. The disclosure provides a medical loop that can be tightened around the tissue extending from the tissue layer by using a one-way anchor and a flexible member to form a loop, the flexible member having ridges to interface with the anchor and secure the flexible member in a tightened position around the tissue. The ridges interface with the tissue to secure the loop in position on the extending tissue and reduce slippage of the loop off of the tissue after tightening the loop. A snare or other cutting instrument may be used to remove the tissue extending outward from the loop. An endoscopic system may be used to guide the medical loop and the cutting instrument to an appropriate location inside a body passage. | 05-21-2009 |
Imad Ahmed, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100217649 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR FILTERING OF FINANCIAL ADVERTISING - An exemplary embodiment of a method for filtering financial advertising may include receiving advertising groupings from a financial institution, where the groupings include a group identifier and one or more advertisements; receiving identity information from a credit consumer and providing the identity to a credit bureau; the credit bureau retrieves consumer credit history including consumer credit attributes; receiving a list of group identifiers from the credit bureau, where the list is generated by the credit bureau for each of the advertising groupings by adding the group identifier to the list if the credit consumer credit attributes satisfy a group financial criteria provided to the credit bureau by the financial institution; identifying the financial advertisements from the advertising grouping, where the group identifier for the advertising grouping corresponds to the group identifier from the list of from the credit bureau; and providing the financial advertisement to the consumer. | 08-26-2010 |
Imran Ahmed, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090100247 | SIMD PERMUTATIONS WITH EXTENDED RANGE IN A DATA PROCESSOR - A processor in a data processing system executes a permutation instruction which identifies a first source register, at least one other source register, and a destination register. The first source register stores at least one in-range index value for the at least one other source register and at least one out-of-range index value for the at least one other source register. The at least one other source register stores a plurality of vector element values, wherein each in-range index value indicates which vector element value of the at least one other source register is to be stored into a corresponding vector element of the destination register. Each out-of-range index value is used to indicate which one of at least two predetermined constant values is to be stored into a corresponding vector element of the destination register. Partial table lookups using a permutation instruction shortens the time required to retrieve data. | 04-16-2009 |
Imtiaz Ahmed, Katy, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110213556 | SYSTEM AND METHOD FOR LOCAL ATTRIBUTE MATCHING IN SEISMIC PROCESSING - There is provided herein a New system arid method of local attribute match filtering which operates in the local attribute domain via the use of complex wavelet transform technology. This approach is adaptable to address various noise types in seismic data and, more particularly, is well suited to reduce the noise in geophone data as long as an associated hydrophone signal is relatively noise-free. | 09-01-2011 |
Mansoor Ahmed, Fort Worth, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110235539 | Adaptive Bearer Configuration for Broacast/Multicast Service - A method and apparatus for providing adaptive bearer configuration for MBMS delivery is disclosed. A first aspect of the present disclosure is a method of operating a wireless infrastructure entity ( | 09-29-2011 |
Minhaj Ahmed, Plano, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110128220 | Cursor control device - A cursor control device having a light source and an image sensor for optically tracking motion. The device includes an upwardly facing dome or window that provides a visual and tactile interface for user interaction. The user's hand or finger, bare or gloved, or other object controlled by the user, can be moved in close proximity or touching the dome, and means are provided to discriminate against the motion of objects that are not close to the dome in order to prevent unwanted cursor motion. Said means can include optics having a limited depth of focus, adaptive illumination processing for controlling the intensity of light emitted from the light source to optimize sensor operation, and/or processing for projecting cursor motion in accordance with a detected level of confidence in the sensor data. | 06-02-2011 |
Muhammad Ahmed, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100228944 | Apparatus and Method to Translate Virtual Addresses to Physical Addresses in a Base Plus Offset Addressing Mode - An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation lookaside buffer (TLB) lookup based on a base address value to retrieve a speculative physical address. While performing the TLB lookup based on the base address value, the base address value is added to an offset value to generate an effective address value. The method also includes performing a comparison of the base address value and the effective address value based on a variable page size to determine whether the speculative physical address corresponds to the effective address. | 09-09-2010 |
| 20120083912 | ARITHMETIC LOGIC AND SHIFTING DEVICE FOR USE IN A PROCESSOR - An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data. | 04-05-2012 |
Nadeem Ahmed, Allen, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090232238 | METHOD, APPARATUS AND SYSTEM FOR USING GUARD TONES IN OFDM SYSTEMS FOR INCREASING DATA RATES AND IMPROVING ROBUSTNESS - The present disclosure provides a method, apparatus, and system for increasing data rates and improving robustness in a wireless communication system. The method comprises identifying a set of guard tones for wireless Orthogonal Frequency Division Multiplexing (OFDM) signals, encoding data for OFDM transmission, identifying a preferred puncture pattern to puncture the encoded data, puncturing the encoded data with the preferred puncture pattern, and transmitting the punctured encoded data, wherein a portion of the punctured encoded data is transmitted on a portion of the set of guard tones. | 09-17-2009 |
Nadeem Ahmed, Alllen, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100066804 | REAL TIME VIDEO COMMUNICATIONS SYSTEM - Novel tools and techniques for providing video calling solutions. In some such solutions, a video calling device resides functionally inline between a set-top box and a television set. Such solutions can provide, in some cases, high performance video calling, high video quality, simplified installation, configuration and/or use, and/or the ability to enjoy video calling in an inclusive, comfortable environment, such as a family room, den, or media room. | 03-18-2010 |
Ramy Ahmed, College Station, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20120068868 | CONTINUOUS-TIME SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER - A continuous-time delta-sigma analog-to-digital converter (ADC) is disclosed. The ADC includes a loop filter, a loop quantizer, and a clock-jitter tolerant digital-to-analog converter (DAC). The clock-jitter tolerant DAC includes a dual switched-current (SI) DAC, a switched-capacitor (SC) DAC, an adder, and a switched-capacitor-resistor (SCR) injection circuit. The dual SI DAC provides two identical analog signals from the feedback digital signal of a loop quantizer within the ADC. The SC DAC provides an error-free reference signal from the feedback digital signal. The adder subtracts one of the two analog signals from the error-free reference signal to obtain an inverted jitter-induced error signal. The SCR injection circuit then injects the inverted jitter-induced error signal, delayed by one clock-cycle, in the form of a half-delay return-to-zero exponentially decaying waveform into the loop filter. | 03-22-2012 |
Sebastian Ahmed, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080232151 | System and method to control one time programmable memory - Systems and methods to control one time programmable (OTP) memory are disclosed. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data. | 09-25-2008 |
| 20100272265 | SYSTEM AND METHOD TO CONTROL ONE TIME PROGRAMMABLE MEMORY - Systems and methods to control one time programmable (OTP) memory are disclosed. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data. | 10-28-2010 |
| 20110141791 | SYSTEM AND METHOD TO CONTROL ONE TIME PROGRAMMABLE MEMORY - A device includes a one-time-programmable memory including multiple random accessible input/output pins. Each random accessible I/O pin corresponds to a unique memory address in the one-time-programmable memory. The device also includes a multiplexing circuit with multiple inputs. Each of the multiple inputs is coupled to one of the multiple random accessible I/O pins. An output of the multiplexing circuit has a bit width that is less than the number of the multiple random accessible I/O pins. | 06-16-2011 |
Shahir Anwar Ahmed, League City, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20120130727 | COMMUTER REWARD SYSTEMS AND METHODS - Methods and systems are disclosed for rewarding a commuter. A value of a characteristic of a commute by the commuter along a route from a first location to a second location is determined. The value of the characteristic is compared with a reference value for the characteristic for travel by the commuter along the route from the first location to the second location to determine that the determined value deviates from the reference value by more than a threshold amount. A reward to the commuter is generated in response to determining that the determined value deviates from the reference value by more than the threshold amount. | 05-24-2012 |
S. Nadeem Ahmed, Allen, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110002376 | Latency Minimization Via Pipelining of Processing Blocks - Novel tools and techniques for minimizing the latency of video processing blocks via pipelining. Video calling is a latency sensitive application. When the latency between capture at the video source and display at the video sink is too large, the call does not appear interactive. Transmission of video over a network exacerbates the problem. It is highly desirable to minimize the capture/encode/transmit latency at the video source and the receive/decode/display latency at the video sink. Certain tools disclosed herein minimize these latencies via pipelining of processing blocks. For example, in some tools, each block begins processing before the previous block has finished its processing. | 01-06-2011 |
Syed Ahmed, Katy, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100024377 | SHACKLE APPARATUS AND SYSTEM FOR THE LIFTING OF SUBSEA OBJECTS - The present invention is a shackle apparatus used for the lifting of subsea objects. The shackle apparatus includes a shackle body having a first leg and a second leg in which each of the legs has an eyelet formed therein. A pin is mounted through the eyelets of the legs of the shackle body. At least one latch extends radially outwardly of the pin and resides adjacent the first leg of the shackle body. A stop surface extends from the pin and is positioned adjacent the second leg of the shackle body. The pin has a generally pointed end so that a remotely operated vehicle can suitably guide the pin through the eyelets of the shackle body. A gripping member extends outwardly from an end of the pin so as to provide a surface whereby an ROV can grip the pin for installation into the shackle body. | 02-04-2010 |
Syed A. Ahmed, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100228709 | DYNAMICALLY REDIRECTING A TARGET LOCATION DURING A FILE I/O OPERATION - A file I/O operation is initiated to store a result of a file I/O operation in a destination file. In response to the file I/O operation being in progress, an amount of the file I/O operation currently completed is monitored. In response to determining that the amount of the file I/O operation currently completed is less than a threshold amount, another destination file is specified through a user interface, in which to store a result of file I/O operation not yet completed. The file I/O operation stores the remaining result of the file I/O operation at the another destination file. A single file handle is updated for the result of the file I/O operation to reference the destination file comprising the portion of the result and the another destination file comprising the remaining result. | 09-09-2010 |
Syed Faisal Ahmed, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090024842 | Precise Counter Hardware for Microcode Loops - In an embodiment, a microcode unit for a processor is contemplated. The microcode unit comprises a microcode memory storing a plurality of microcode routines executable by the processor, wherein each microcode routine comprises two or more microcode operations. Coupled to the microcode memory, the sequence control unit is configured to control reading microcode operations from the microcode memory to be issued for execution by the processor. The sequence control unit is configured to stall issuance of microcode operations forming a body of a loop in a first routine of the plurality of microcode routines until a loop counter value that indicates a number of iterations of the loop is received by the sequence control unit. | 01-22-2009 |
Syed Nadeem Ahmed, Allen, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080273614 | SYSTEM, METHOD, AND COMPUTER-READABLE MEDIUM FOR MULTILEVEL SHAPING FOR WIRELESS COMMUNICATION SYSTEMS - A system, method and computer-readable medium for encoding and decoding digital information over a channel is provided. Type Mapping is employed and is based on the partitioning of vectors over an alphabet into “types” and using enumeration for the encoding and decoding process. Type mapping allows for signal alphabets of arbitrary size and date rate flexible coding. Tradeoffs between optimal rate versus Signal to Noise Ratio are provided and works as a compliment to the Forward Error Control that may be employed in communications products. | 11-06-2008 |
| 20090180521 | DETECTION OF INTERFERERS USING DIVERGENCE OF SIGNAL QUALITY ESTIMATES - A method, system, and computer-readable medium for detecting an interferer in a wireless communication system are provided. The method includes receiving a signal having P tones, each of the P tones being associated with a frequency, determining a first signal quality of each of the P tones, determining a second signal quality of each of the P tones, and detecting the interferer that occupies the same frequency as one of the P tones based on the respective first signal quality and the respective second signal quality. The first signal quality and second signal quality behave differently when the interferer is present. The detecting the interferer includes determining a discrepancy in the behavior of the first signal quality and the second signal quality. | 07-16-2009 |