| Patent application number | Description | Published |
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| 20090273502 | Fast, efficient reference networks for providing low-impedance reference signals to signal converter systems - Reference network embodiments are provided for use in pipelined signal converter systems. The network embodiments are fast and power efficient and they generate low-impedance reference signals through the use of a complimentary common-drain output stage, an output current valve inserted between transistors of the output stage, and a controller. The controller is configured to provide gate voltages to the output current valve to thereby establish a substantially-constant output current. The controller is further configured to provide gate voltages to the output stage to establish top and bottom reference voltages about the output current valve that are spaced from a common-mode voltage. This reference structure maintains a constant output current as the span between the top and bottom reference voltages is selectively altered. In different embodiments, transistors of the output current valve are arranged in a drain-to-source-coupled configuration and in a source-coupled configuration. | 11-05-2009 |
| 20100019946 | Amplifier networks with controlled common-mode level and converter systems for use therewith - Effective control of the common-mode level of amplifiers is obtained through control structures (both closed-loop and open-loop structures) which are directed to various amplifier functions such as the reduction of amplifier loading, accurate sensing of common-mode levels, mitigation of headroom restraints, and proper transistor biasing. This common-mode control is especially useful in multiplying analog-to-digital converters (MDACs) of signal processing systems. | 01-28-2010 |
| 20100073210 | Pipelined converter systems with enhanced linearity - Signal converter system embodiments are provided to substantially reduce symmetrical and asymmetrical conversion errors. Signal-processing stages of these embodiments may include a signal sampler in addition to successively-arranged signal converters. In system embodiments, injected analog dither signals are initiated in response to a random digital code. They combine with a system's analog input signal and the combined signal is processed down randomly-selected signal-processing paths of the converter system to thereby realize significant improvements in system linearity. Because these linearity improvements are realized by simultaneous processing of the input signal and the injected dither signal, a combined digital code is realized at the system's output. A first portion of this combined digital code corresponds to the analog input signal and a second portion corresponds to the injected analog dither signal. The final system digital code is realized by subtracting out the second portion with a back-end decoder that responds to the random digital code. | 03-25-2010 |
| 20100109927 | RESIDUE GENERATORS FOR REDUCTION OF CHARGE INJECTION IN PIPELINED CONVERTER SYSTEMS - Pipelined converter systems include a plurality of converter stages in which some stages generate and pass a residue signal to a succeeding stage for further conversion. The generation of the residue signal can inject spurious charges into a reference source that is used in the generation. The spurious charges reduce the accuracy of the residue signal and the accuracy of the system. Residue generator embodiments are thereby formed to provide reduction charges to the reference source that are arranged to oppose and reduce the spurious charges. This reduction of spurious charges significantly enhances system accuracy and linearity. | 05-06-2010 |
| 20100149015 | FAST, EFFICIENT REFERENCE NETWORKS FOR PROVIDING LOW-IMPEDANCE REFERENCE SIGNALS TO SIGNAL PROCESSING SYSTEMS - Reference network embodiments are provided for use in pipelined signal converter systems. The network embodiments are fast and power efficient and they generate low-impedance reference signals through the use of at least one output transistor, a diode-coupled transistor coupled to the output transistor, and a controller. The controller is configured to provide a backgate voltage to the diode-coupled transistor to thereby establish a substantially-constant output current. The controller is further configured to provide a gate voltage to the output transistor to establish a reference voltage. | 06-17-2010 |
| 20100301930 | REDUCING DEVICE PARASITICS IN SWITCHED CIRCUITS - A system and method are provided to reduce the influence of parasitic capacitance at the drain and source of MOS transistors of a sampling circuit. In one embodiment, the bulk is left floating during a first phase and refreshed during a second phase. During the first phase, the effective parasitic contribution of the drain or source of a MOS transistor is lower due to the series combination of Cj and Cw capacitances. In another embodiment, a large resistance provides a path from a reference voltage to the bulk of a MOS transistor, thereby resulting in an effective parasitic capacitance of the series combination of Cj and Cw. Advantageously, the parasitic capacitance is reduced as well as its non-linear effect, the operating speed is improved, as well as the signal distortion and noise. | 12-02-2010 |
| 20110006815 | HIGH PERFORMANCE VOLTAGE BUFFERS WITH DISTORTION CANCELLATION - A voltage buffer may include a first signal path extending from an input terminal to an output terminal in which the first signal path further may include a buffer transistor that may have a control terminal, and a first and second current terminals responsive to the control terminal. In the first signal path, the control terminal may be connected to the input terminal, the first current terminal may be connected to the output terminal, and the first signal path may supply a load current to a load device responsive to an input signal at the input terminal. The voltage buffer further may include a second signal path extending from the input terminal to a current source node. The second signal path may include a replica load device. The voltage buffer further may include a current source supplying substantially constant current and coupled to the current source node. The voltage buffer further may include a current buffer positioned between the current source node and the output node in which the current buffer may direct a replica current from the second signal path responsive to the input signal and the substantially constant current from the current source to the buffer transistor. | 01-13-2011 |
| 20110210877 | CALIBRATION METHODS AND STRUCTURES FOR PIPELINED CONVERTER SYSTEMS - Calibration methods and structures are provided for pipelined analog-to-digital converter systems. They are arranged to process samples of the digital codes with an algorithm that is preferably configured to repeatedly update an estimate of the transfer function with the difference between one of the input signals and the analog equivalent of the corresponding digital code. The calibration methods and structures are further configured to calibrate the transfer function of the converter stage wherein the samples are selected in accordance with various steps. These steps can include the step of injecting dither signals into a flash portion and an MDAC portion of the converter stage to thereby maintain dynamic range. They can also include the step of limiting the samples to those processed through a selected subrange of the subranges. They can further include the step of limiting the samples to those in which the absolute value of the input signals is less that 0.25 of the selected subrange and the absolute value of the dither signals is less that 0.25 of the selected subrange. If the selected subrange is not a central subrange, the steps can further include the step of shifting the samples by a distance between the selected subrange and the central subrange. | 09-01-2011 |
