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Ahmed, CA
Abdelrehim Ahmed, Santa Clara, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110296353 | Method and system implementing user-centric gesture control - A user-centric method and system to identify user-made gestures to control a remote device images the user using a three-dimensional image system, and defines at least one user-centric three-dimensional detection zone dynamically sized appropriately for the user, who is free to move about. Images made within the detection zone are compared to a library of stored gestures, and the thus identified gesture is mapped to an appropriate control command signal coupleable to the remote device. The method and system also provides of a first user to hand off control of the remote device to a second user. | 12-01-2011 |
Akbar Saleem Ahmed, Concord, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120089546 | METHODS AND SYSTEMS FOR AUTOMATED SURVEY SCRIPT AUTHORING AND PROGRAMMING - A survey authoring and programming application parses and extracts information included in a questionnaire that consists of questions, answer options and instructions, and stores the information in a market research markup language (MRML) data model that abstracts the content, structure and instructions of the questionnaire. A logic engine then operates on the MRML representation of the questionnaire to produce one or more survey script outputs in any desired target survey programming language. The questionnaire may be written in a market research language (MRL). | 04-12-2012 |
Ak R. Ahmed, Rancho Cordova, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110069566 | MEMORY CELL WRITE - Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and a complementary data node programming module configured to receive the second supply voltage and to program a complementary data node based at least in part on a complementary write data line, wherein the voltage module is configured such that the first supply voltage is substantially different from the second supply voltage for a period of time while the memory device is being programmed. Additional variants and embodiments may also be disclosed and claimed. | 03-24-2011 |
| 20120039135 | MEMORY CELL WRITE - Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and a complementary data node programming module configured to receive the second supply voltage and to program a complementary data node based at least in part on a complementary write data line, wherein the voltage module is configured such that the first supply voltage is substantially different from the second supply voltage for a period of time while the memory device is being programmed. Additional variants and embodiments may also be disclosed and claimed. | 02-16-2012 |
Ali Kamran Ahmed, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120047425 | METHODS AND APPARATUSES FOR INTERACTION WITH WEB APPLICATIONS AND WEB APPLICATION DATA - A method of enabling content distribution for various electronic devices which comprises providing a content adaptive application for an electronic device, wherein the content adaptive application is designed to parse an abstraction schema to retrieve data or a data source, and format information. The content adaptive application further formats the data or data from the data source into at least one of a plurality of platform specific templates specified by the format information and displays at least one platform specific template including at least a portion of the data or data from the data source on a display of the electronic device. | 02-23-2012 |
Bilal Ahmed, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080288559 | Exchange server standby solution using mailbox level replication with crossed replication between two active exchange servers - This invention provides the capability to plan, monitor and control post-failure switching of user mail access hosted on Microsoft Exchange servers at the granularity of individual user mailboxes. It offers a convenient point-and-click mechanism for achieving a very complex task, and allows replication of e-mail data from a Primary Exchange Server to a Standby Exchange Server at a level of data granularity and flexibility not previously available. No limitations are placed on which Exchange servers belonging to the user of this solution are to be in a primary or standby role, and it is possible to have two Exchange servers, each acting as an active primary for mailboxes which it is hosting AND acting as a standby for mailboxes hosted on the other server. In addition, it also provides a uniquely powerful capability for migration of mailboxes between Exchange servers. | 11-20-2008 |
Ghufran Ahmed, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110258027 | POINT-OF-SALE PROMOTIONS - A method and a system to publish a promotion at a point-of-sale are provided. For example, a preliminary selection associated with a purchase from a user may be received. A promotion may be published to the user at a point-of-sale associated with the purchase after the user makes the preliminary selection and before the user finalizes the purchase. The promotion may be based on at least one attribute of past transactions and the preliminary selection. | 10-20-2011 |
Hanan Ahmed, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100035578 | Method and System for Interworking Between Two Different Networks - Systems and methods for interworking between two different networks are presented. In one embodiment, a method for wireless communication includes requesting a network access from an access point of a first network, and transmitting an EAP authentication request from the access point to a user end. An EAP authentication request response is sent from the user end to the access point. The EAP authentication request response includes an attach type indicator that indicates to a gateway associated with the access point whether the attach request is an initial attachment or a handover from a second network. | 02-11-2010 |
| 20110170479 | Mobility Management System and Method - A method and system for optimizing mobility routing are disclosed. A preferred embodiment comprises a first system of networks that comprise a home local mobility anchor and two or more distributed local mobility anchors, and a second system of networks separate from the first system of networks. Packets of data may be transmitted from a correspondent node anchored in the second system of networks to a mobile node anchored in the second system. Additionally, packets of data may be transmitted from the mobile node to the correspondent node. | 07-14-2011 |
| 20110178904 | Method for Accounting Information Handling in an Interworking - A method for accounting information handling in an interworking is provided. A method for processing accounting information by a gateway device includes sending an accounting request message to a first electronic device, and receiving a response message from a first electronic device, the response message responsive to the accounting request message. The accounting request message is related to a communications device attached to the first network. The method also includes processing accounting information. The processing is based on the response message, the gateway device and the first electronic device are part of the first network, the communications device is accessing a second network through the first network, and the communications device has a subscription only with the second network. | 07-21-2011 |
| 20120030075 | Method for Accounting Information Handling in an Interworking - A method for accounting information handling in an interworking is provided. A method for processing accounting information by a gateway device includes sending an accounting request message to a first electronic device, and receiving a response message from a first electronic device, the response message responsive to the accounting request message. The accounting request message is related to a communications device attached to the first network. The method also includes processing accounting information. The processing is based on the response message, the gateway device and the first electronic device are part of the first network, the communications device is accessing a second network through the first network, and the communications device has a subscription only with the second network. | 02-02-2012 |
Jasim Ahmed, Menlo Park, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110081563 | LITHIUM RESERVOIR SYSTEM AND METHOD FOR RECHARGEABLE LITHIUM ION BATTERIES - A lithium-ion battery cell includes at least two working electrodes, each including an active material, an inert material, an electrolyte and a current collector, a first separator region arranged between the at least two working electrodes to separate the at least two working electrodes so that none of the working electrodes are electronically connected within the cell, an auxiliary electrode including a lithium reservoir, and a second separator region arranged between the auxiliary electrode and the at least two working electrodes to separate the auxiliary electrode from the working electrodes so that none of the working electrodes is electronically connected to the auxiliary electrode within the cell. | 04-07-2011 |
Kashif A. Ahmed, Irvine, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100283542 | Linear transimpedance amplifier with wide dynamic range for high rate applications - Various amplifier configurations having increased bandwidth, linearity, dynamic range, and less distortion are shown and disclosed. To increase bandwidth in a transimpedance amplifier, a replica circuit is created to replicate a degeneration resistance, or the resistance or value that relates to a feedback resistance. From the replica circuit, the replicated values are mirrored and processed to control a FET switch which modifies a degeneration resistance. The FET switch control signal is related to the feedback resistance and modifies the degeneration resistance to thereby maintain the product of the feedback resistance and the degeneration resistance as a constant. In another embodiment, a second switch controlled by an automatic gain control signal is established between a first stage amplifier and a second stage amplifier to improve dynamic range and bandwidth without degrading other amplifier specifications. | 11-11-2010 |
| 20100283543 | Variable gain amplifier - Various amplifier configurations having increased bandwidth, linearity, dynamic range, and less distortion are shown and disclosed. To increase bandwidth in a transimpedance amplifier, a replica circuit is created to replicate a degeneration resistance, or the resistance or value that relates to a feedback resistance. From the replica circuit, the replicated values are mirrored and processed to control a FET switch which modifies a degeneration resistance. The FET switch control signal is related to the feedback resistance and modifies the degeneration resistance to thereby maintain the product of the feedback resistance and the degeneration resistance as a constant. In another embodiment, a second switch controlled by an automatic gain control signal is established between a first stage amplifier and a second stage amplifier to improve dynamic range and bandwidth without degrading other amplifier specifications. | 11-11-2010 |
Khaled Ahmed, Anaheim, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090020802 | INTEGRATED SCHEME FOR FORMING INTER-POLY DIELECTRICS FOR NON-VOLATILE MEMORY DEVICES - Electronic devices and methods for forming electronic devices that allow for a reduction in device dimensions while also maintaining or reducing leakage current for non-volatile memory devices are provided. In one embodiment, a method of fabricating a non-volatile memory device is provided. The method comprises depositing a floating gate polysilicon layer on a substrate, forming a silicon oxide layer on the floating gate polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a high-k dielectric material layer on the first silicon oxynitride layer, depositing a second silicon oxynitride on the high-k dielectric material, and forming a control gate polysilicon layer on the second silicon oxynitride layer. In one embodiment, the high-k dielectric material layer comprises hafnium silicon oxynitride. | 01-22-2009 |
| 20090242957 | ATOMIC LAYER DEPOSITION PROCESSES FOR NON-VOLATILE MEMORY DEVICES - Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer. | 10-01-2009 |
| 20100102376 | Atomic Layer Deposition Processes for Non-Volatile Memory Devices - Embodiments of the invention provide memory devices and methods for forming such memory devices. In one embodiment, a method for fabricating a non-volatile memory device on a substrate is provided which includes depositing a first polysilicon layer on a substrate surface, depositing a silicon oxide layer on the first polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a silicon nitride layer on the first silicon oxynitride layer, depositing a second silicon oxynitride layer on the silicon nitride layer, and depositing a second polysilicon layer on the second silicon oxynitride layer. In some examples, the first polysilicon layer is a floating gate and the second polysilicon layer is a control gate. | 04-29-2010 |
Khaled Z. Ahmed, Anaheim, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090042353 | INTEGRATED CIRCUIT FABRICATION PROCESS FOR A HIGH MELTING TEMPERATURE SILICIDE WITH MINIMAL POST-LASER ANNEALING DOPANT DEACTIVATION - Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer of nickel is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying layer of a metal having a higher melting temperature than nickel. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing. | 02-12-2009 |
| 20090042354 | INTEGRATED CIRCUIT FABRICATION PROCESS USING A COMPRESSION CAP LAYER IN FORMING A SILICIDE WITH MINIMAL POST-LASER ANNEALING DOPANT DEACTIVATION - Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying compression cap layer, to prevent metal agglomeration at the silicon melting temperature. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing near the silicon melting temperature. | 02-12-2009 |
| 20090042376 | INTEGRATED CIRCUIT FABRICATION PROCESS WITH MINIMAL POST-LASER ANNEALING DOPANT DEACTIVATION - Post-laser annealing dopant deactivation is minimized by performing certain low temperature process steps prior to laser annealing. | 02-12-2009 |
| 20090246972 | METHODS FOR MANUFACTURING HIGH DIELECTRIC CONSTANT FILM - Processes for making a high K (dielectric constant) film using an ultra-high purity hafnium containing organometallic compound are disclosed. Also described are devices incorporating high K films made with high purity hafnium containing organometallic compounds. | 10-01-2009 |
Khawza Iftekhar-Uddin Ahmed, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080258973 | RANGING SIGNALS METHODS AND SYSTEMS - A system and method for estimating the range between two devices performs two or more ranging estimates with subsequent estimates performed using a clock that is offset in phase with respect to a prior estimate. The subsequent estimate allows estimate uncertainties due to a finite clock resolution to be reduced and can yield a range estimate with a higher degree of confidence. In one embodiment, these additional ranging estimates are performed at n/N (for n=1, . . . N−1, with N>1 and a positive integer) clock-period offset introduced in the device. The clock-period offset can be implemented using a number of approaches, and the effect of clock drift in the devices due to relative clock-frequency offset can also be determined. To eliminate the bias due to clock-frequency offset, a system and method to estimate the clock-frequency offset is also presented. | 10-23-2008 |
| 20100283682 | CLOCK PHASE RANGING METHODS AND SYSTEMS - A system and method for estimating the range between two devices performs two or more ranging estimates with subsequent estimates performed using a clock that is offset in phase with respect to a prior estimate. The subsequent estimate allows estimate uncertainties due to a finite clock resolution to be reduced and can yield a range estimate with a higher degree of confidence. In one embodiment, these additional ranging estimates are performed at n/N (for n=1, . . . N−1, with N>1 and a positive integer) clock-period offset introduced in the device. The clock-period offset can be implemented using a number of approaches, and the effect of clock drift in the devices due to relative clock-frequency offset can also be determined. To eliminate the bias due to clock-frequency offset, a system and method to estimate the clock-frequency offset is also presented. | 11-11-2010 |
Mahad Ahmed, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080232372 | Methods and systems for interworking RSVP-based external control plane protocols with internal control plane protocols - The present invention provides improved methods and systems for interworking Resource Reservation Protocol (RSVP)-based external control plane protocols with internal control plane protocols, such as Optical Signaling and Routing Protocol (OSRP). The present invention utilizes only a high-level mapping in which a trigger is created in the internal control plane protocol to initiate the desired internal control plane action or vice versa. The external control plane protocol messages and fields are encapsulated as data in the internal control plane messages and fields and are processed only at the remote end of the internal domain. By encapsulating the entirety or parts of the external control plane protocol messages and fields ensures that necessary information is carried from an ingress border node to an egress border node. At the egress border node, the encapsulated external control plane protocol messages and fields are mapped back to the external control plane protocol, without having to make changes to the internal control plane protocol or perform processing at intermediate nodes. | 09-25-2008 |
Masood Ahmed, Rocklin, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110270091 | Apparatus and Method for Use of RFID Catheter Intelligence - A method and system is provided for using backscattered data and known parameters to characterize vascular tissue. Specifically, methods and devices for identifying information about the imaging element used to gather the backscattered data are provided in order to permit an operation console having a plurality of Virtual Histology classification trees to select the appropriate VH classification tree for analyzing data gathered using that imaging element. In order to select the appropriate VH database for analyzing data from a specific imaging catheter, it is advantageous to know information regarding the function and performance of the catheter, such as the operating frequency of the catheter and whether it is a rotational or phased-array catheter. The present invention provides a device and method for storing this information on the imaging catheter and communicating the information to the operation console. In addition, information related to additional functions of the catheter may also be stored on the catheter and used to further optimize catheter performance and/or select the appropriate Virtual Histology classification tree for analyzing data from the catheter imaging element. | 11-03-2011 |
Mohiuddin Ahmed, Moorpark, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110122924 | RAPID ACQUISITION METHOD FOR IMPULSE ULTRA-WIDEBAND SIGNALS - A method is provided that determines a delay and phase of an ultra-wide band signal in a communication system using a single correlator. A pulse search is executed that includes correlating a signal template with a UWB signal and sampling a preamble of the UWB signal at various time positions until a pulse in the signal template matches a pulse in the preamble. A chip boundary at which the pulse in the preamble is detected is identified using the signal template. A code search is executed for determining the correct phase of the received signal. The code search utilizes a plurality of phases having a same time-hopping sequence as the received signal. Each pulse of the phases is positioned at the determined chip boundary within each respective chip pulse position. Chips pulse positions of the phases are compared with the chip pulse positions of the UWB signal for determining a phase match. | 05-26-2011 |
Moinuddin Ahmed, San Ramon, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110297618 | Filtering Process and System to Remove AlCl3 Particulates from Ionic Liquid - A process for the filtration of an ionic liquid involves feeding an ionic liquid containing precipitated metal halides to a first filtering zone, which includes at least one first filter, to provide a partially filtered product. The process further includes subsequently feeding the partially filtered product to a second filtering zone, which includes at least one second filter having a smaller pore size than the at least one first filter, to provide a filtered product. A filter system capable of filtering precipitated metal halides from ionic liquid is also disclosed. | 12-08-2011 |
Muhammad Ahmed, Hayward, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100281234 | INTERLEAVED MULTI-THREADED VECTOR PROCESSOR - A method includes providing a processor configured to execute instructions. The method may further include providing a first set of registers in the processor to store first data and first instructions associated with a first thread, and providing a second set of registers in the processor to store second data and second instructions associated with a second thread. The method may further include transmitting the first data and first instructions associated with the first thread to the first set of registers, and executing the first instructions in order to process the first data. The method may further include transmitting the second data and second instructions to the second set of registers while executing the first instructions and processing the first data. A corresponding apparatus is also disclosed and claimed herein. | 11-04-2010 |
| 20100281236 | APPARATUS AND METHOD FOR TRANSFERRING DATA WITHIN A VECTOR PROCESSOR - An apparatus for processing data may include an array of processing elements (such as an n×m or n×n array of processing elements) configured to simultaneously perform operations on a plurality of data elements using a single instruction. Each processing element in the array may be configured to transfer data directly to at least one neighboring processing element within the array. In selected embodiments, the apparatus may include exchange registers to temporarily store data transferred between neighboring processing elements. | 11-04-2010 |
| 20100281483 | PROGRAMMABLE SCHEDULING CO-PROCESSOR - A scheduling co-processor for scheduling the execution of threads on a processor is disclosed. In certain embodiments, the scheduling co-processor includes one or more engines (such as lookup tables) that are programmable with a Petri-net representation of a thread scheduling algorithm. The scheduling co-processor may further include a token list to store tokens associated with the Petri-net; an enabled-thread list to indicate which threads are enabled for execution in response to particular tokens being present in the token list; and a ready-thread list to indicate which threads from the enabled-thread list are ready for execution when data and/or space availability conditions associated with the threads are satisfied. | 11-04-2010 |
Nawaaz Ahmed, San Francisco, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090055380 | Predictive Stemming for Web Search with Statistical Machine Translation Models - Techniques for determining when and how to transform words in a query to return the most relevant search results while minimizing computational overhead are provided. A dictionary is generated based upon words used in a specified number of previous most frequent search queries and comprises lists of transformations that may include variants based upon the stems of words, synonyms, and abbreviation expansions. When a query is received from a user, candidate queries are generated based upon replacing particular words in the query with a transformation of the particular words. Candidate queries are selected that have a high probability of returning relevant results by computing values of the query using language model scoring and translation scoring. The selected candidate queries and the original query are executed to return search results. The search results are displayed to the user with the words in the original query and the transformed words in bold. | 02-26-2009 |
| 20090132515 | Method and Apparatus for Performing Multi-Phase Ranking of Web Search Results by Re-Ranking Results Using Feature and Label Calibration - A method and apparatus for performing multi-phase ranking of web search results by re-ranking results using feature and label calibration are provided. According to one embodiment of the invention, a ranking function is trained by using machine learning techniques on a set of training samples to produce ranking scores. The ranking function is used to rank the set of training samples according to its ranking score, in order of its relevance to a particular query. Next, a re-ranking function is trained by the same training samples to re-rank the documents from the first ranking. The features and labels of the training samples are calibrated and normalized before they are reused to train the re-ranking function. By this method, training data and training features used in past trainings are leveraged to perform additional training of new functions, without requiring the use of additional training data or features. | 05-21-2009 |
| 20090182729 | LOCAL QUERY IDENTIFICATION AND NORMALIZATION FOR WEB SEARCH - Computer-implemented methods and systems for processing user entered query data to improve results of a search of pages using a local search database are provided, when searching the internet. The method includes receiving the user entered query data and parsing each word of the query data and examining each word to determine if the word is associated with one of a business name, a city name or a state name. The examining uses probabilistic dictionaries to determine a likelihood that the word is one of the business name, the city name or the state name. Then, associating the words that were determined to be: (i) the business name with a business name tag to create one or more tagged business terms; (ii) the city name with a city name tag to create one or more tagged city terms; and (iii) the state name with a state name tag to create one or more tagged state terms. The method further includes normalizing each of the tagged business terms, the tagged city terms and the tagged state terms. The normalizing includes boosting information if found in the local search database and determining proximity between selected ones of the tagged business, city or state terms. Then, generating an optimized internal search query that incorporates constraints and ranking based on at least the boosting information and the determined proximity between the selected tagged business, city or state terms. The optimized internal search query is applied to the internet to enable search results to be produced and displayed to the user in response to the entered query data. | 07-16-2009 |
| 20090248595 | NAME VERIFICATION USING MACHINE LEARNING - Computer-enabled methods, apparatus, and computer-readable media are provided for verifying that a given network name, such as a URL, is an official, e.g., registered, approved, or otherwise officially recognized, network name that refers to or identifies a principal, such as a business. These techniques involve receiving a principal name and a given network name, receiving at least one feature attribute from at least one database of feature attributes, wherein the at least one feature attribute comprises a characteristic of the principal name or a characteristic of the network name, and invoking a logistic regression method to generate a probability, based upon the at least one feature attribute, that the given network name is an official network name for the principal name. The logistic regression method may include a gradient boosting tree model that generates the probability based upon the at least one feature attribute. | 10-01-2009 |
| 20110264647 | QUERY PROCESSING FOR WEB SEARCH - A computer-implemented method for processing user entered query data to improve results of a search of pages using a database, when searching the internet, is disclosed. The method includes receiving the user entered query data and parsing each word of the query data and segmenting words using probability to determine a likelihood that the word is for a particular name. And, associating the particular names with a name tag to create one or more tagged name terms. Then, normalizing each of the tagged name terms and the normalizing including boosting information if found in the database and determining proximity between selected ones of the tagged name terms. The method then generates an optimized search query that incorporates normalized terms and operators. The optimized search query being applied to the internet to enable search results to be produced and displayed to the user in response to the entered query data. | 10-27-2011 |
Nisar Ahmed, Los Angeles, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120027412 | Electronic Compensation of Nonlinearity in Optical Communication - In various embodiments, electronic apparatus, systems, and methods include electronic compensation of nonlinearity in optical communication. Additional apparatus, systems, and methods are disclosed. | 02-02-2012 |
Rana Anjum Ahmed, La Mirada, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090094073 | REAL TIME CLICK (RTC) SYSTEM AND METHODS - A real-time click system to process advertisement (ad) clicks includes a real-time listener operative to listen for, and store in a memory, a plurality of click event packets emitted by an ad server when corresponding ads are clicked by web users. A sequencer stores the click event packets in a database. A collector is coupled with the real-time listener and the sequencer and is operative to retrieve the plurality of click event packets, upon request, from the memory at a predetermined time interval. The collector also determines a partition number associated with each of the plurality of click event packets and sends to the sequencer the click event packets having a partition number corresponding to the sequencer. | 04-09-2009 |
Rizwan E. Ahmed, Santa Clara, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100328149 | System and/or Method for Determining Sufficiency of Pseudorange Measurements - The subject matter disclosed herein relates to a system and method for determining a sufficiency of measurements for locating positions. In one example, although claimed subject matter is not so limited, a process to improve accuracy of pseudorange measurements may be terminated in response to a weighting of quantitative assessments of at least some of such pseudorange measurements. | 12-30-2010 |
Sadar Ahmed, Redwood Shores, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110231460 | APPARATUS AND METHOD FOR FLOATING-POINT FUSED MULTIPLY ADD - A fused multiply add (FMA) unit includes an alignment counter configured to calculate an alignment shift count, an aligner configured to align an addend input based on the alignment shift count and output an aligned addend, a multiplier configured to multiply a first multiplicand input and a second multiplicand input and output a product, an adder configured to add the aligned addend and the product and output a sum without determining the sign of the sum or complementing the sum, a normalizer configured to receive the sum directly from the adder and normalize the sum irrespective of the sign of the sum and output a normalized sum, and a rounder configured to round and complement-adjust the normalized sum and output a final mantissa. | 09-22-2011 |
Sadar U. Ahmed, Santa Clara, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100042665 | Subnormal Number Handling in Floating Point Adder Without Detection of Subnormal Numbers Before Exponent Subtraction - In an embodiment, a floating point unit (FPU) comprises an adder configured to add a first mantissa and a second mantissa and an operand adjust unit coupled to provide at least the first mantissa to the adder. The operand adjust unit is coupled to receive a first operand and a second operand for a floating point add operation, and is configured to: right shift at least one mantissa corresponding to one of the first and second operands responsive to a shift count generated from exponent portions of the first and second operands; to detect whether or not neither, one, or both of the first and second operands are subnormal numbers in parallel with at least a portion of the right shifting; and to left shift by one bit the right shifted mantissa responsive to only one of the first and second operands being a subnormal floating point number. | 02-18-2010 |
| 20110208794 | COMPUTING HALF INSTRUCTIONS OF FLOATING POINT NUMBERS WITHOUT EARLY ADJUSTMENT OF THE SOURCE OPERANDS - Apparatus and methods are disclosed for a floating point adder having half-adder capability that does not have the overhead of determining half-adder conditions prior to starting the SED, LED, and EXP datapaths. | 08-25-2011 |
Saleh Ahmed, Simi Valley, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090194831 | INTEGRATED CAVITY IN PCB PRESSURE SENSOR - Described herein is an integrated pressure sensor assembly. The integrated pressure sensor assembly includes a printed circuit board assembly comprising a plurality of boards; a pressure die mounted on at least a portion of the printed circuit board assembly; and a housing engaged to the printed circuit board assembly. The printed circuit board assembly includes at least one pressure transmission channel and at least one electrical transmission channel. | 08-06-2009 |
Shadia Ahmed, San Francisco, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110200182 | CALL LOG CONSOLIDATION WITH ALTERNATE DIALING OPTIONS - A system (and method) is disclosed for consolidating communication details associated with a data object in a call log. The system receives communication information corresponding to a contact record and determines whether a call log includes a previously stored data object having the communication information and associated with the contact record. The system associates the received communication information with the previously stored data object having the communication information in response to existence of the previously stored data object. Otherwise, the system creates for inclusion with the call log a new data object having the received communication information a new data object in response to no previously stored data object having the communication information. The previously stored or new data object is displayed in the call log. | 08-18-2011 |
Shafqat Ahmed, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090200548 | GUARD RING EXTENSION TO PREVENT REALIABILITY FAILURES - An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation. | 08-13-2009 |
| 20100187528 | GUARD RING EXTENSION TO PREVENT RELIABILITY FAILURES - An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation. | 07-29-2010 |
| 20100195383 | Isolated P-well Architecture for a Memory Device - A memory device and a method to prevent or reduce program disturb by isolating P-wells of strings in a non-volatile memory array. During a program operation, the isolated P-wells may be coupled to corresponding bitlines, which may be selected or inhibited, and may be at different voltages. During erase, read, and verify operations, the isolated P-wells may be coupled to source. | 08-05-2010 |
| 20110090739 | INDEPENDENT WELL BIAS MANAGEMENT IN A MEMORY DEVICE - Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods. | 04-21-2011 |
Shahid Ahmed, Los Altos, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100070361 | Network-Based Credit System - An online credit system is disclosed. The online credit system allows purchasers (requesters) to request and receive credit (e.g., store credit) for prior purchases of qualifying products. The credit can made available to purchasers as an electronic credit voucher. Through online interaction with the online credit system, a purchaser is able to be informed in near real-time whether a particular prior purchase qualifies for an offered credit. The online credit system can also enforce credit eligibility rules so that only certain prior purchases of certain products are able to receive a credit. The online credit system can also incorporate techniques to mitigate or prevent fraudulent attempts to access such credit. In one embodiment, the products qualifying for credit are wireless electronic devices, such as mobile telephones. | 03-18-2010 |
Sheik Ahmed, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100084997 | MULTI-MODE UTILITY LIGHTING DEVICE - A lighting device that includes a handle, a head control circuitry and a switching mechanism. The handle is adapted to being gripped and held by a human hand. The head includes a heat sink with a plurality of facets and a plurality of light panels. Each facet of the heat sink is in a different plane than other facets of the heat sink. The light panels are mounted on the heat sink. Each light panel is mounted on a different facet of the heat sink. The control circuitry causes the plurality of light panels to emit light in a plurality of user selectable light patterns. The switching mechanism allows a user to select light patterns from among the plurality of user selectable light patterns. | 04-08-2010 |
Sherjil Ahmed, Irvine, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080201751 | Wireless Media Transmission Systems and Methods - The present invention relates to a media transmission and reception system that is implemented, in the form of programs stored in a satellite device having a memory, an input mechanism for receiving commands from a user, and a transceiver capable of wirelessly accessing a network, and in a computing device having a memory and a transceiver capable of accessing a network. The program stored in the memory of the satellite device causes user commands to be processed, causes the satellite device to connect to the computing device through the network, and causes the satellite device to transmit command instructions, derived from the commands, to the computing device through the network. The program stored in the memory of the computing device causes the computing device to access media stored in a memory, causes the computing device to process the media, captures the processed media, compresses the media, and causes the computing device to transmit the compressed media to the satellite device. The media access, media processing, media compression, and media transmission occurs in real-time and in response to the command instructions. | 08-21-2008 |
| 20090201989 | Systems and Methods to Optimize Entropy Decoding - The present invention provides for an improved video compression and encoding that optimizes and enhances the overall speed and efficiency of processing video data. In one embodiment, the video codec transmits the output of an entropy decoder to a lossless compressor and memory before going through inverse discrete cosine transformation and motion compensation blocks. | 08-13-2009 |
| 20090328048 | Distributed Processing Architecture With Scalable Processing Layers - The present invention is a system on chip architecture having scalable, distributed processing and memory capabilities through a plurality of processing layers. In a preferred embodiment, a distributed processing layer processor comprises a plurality of processing layers, a processing layer controller, and a central direct memory access controller. The processing layer controller manages the scheduling of tasks and distribution of processing tasks to each processing layer. Within each processing layer, a plurality of pipelined processing units (PUs), specially designed for conducting a defined set of processing tasks, are in communication with a plurality of program memories and data memories. One application of the present invention is in a media gateway that is designed to enable the communication of media across circuit switched and packet switched networks. The hardware system architecture of the said novel gateway is comprised of a plurality of DPLPs, referred to as Media Engines that are interconnected with a Host Processor or Packet Engine, which, in turn, is in communication with interfaces to networks. Each of the PUs within the processing layers of the Media Engines are specially designed to perform a class of media processing specific tasks, such as line echo cancellation, encoding or decoding data, or tone signaling. | 12-31-2009 |
| 20100321579 | Front End Processor with Extendable Data Path - The present specification discloses a processing architecture that has multiple levels of parallelism and is highly configurable, yet optimized for media processing. At the highest level, the architecture is structured to enable each processor, which is dedicated to a specific media processing function, to operate substantially in parallel. In addition to processor-level parallelism, each processing unit can operate on multiple words in parallel, rather than just a single word per clock cycle. Moreover, at the instruction level, the control data memory, data memory, and function specific dath paths can be controlled all within the same clock cycle. Additionally, the processor has multiple layers of configurability, with the extendable data path of the processor being capable of being configured to perform specific processing functions, such as entropy encoding, discrete cosine transform (DCT), inverse discrete cosine transform (IDCT), motion compensation, motion estimation, de-blocking filter, de-interlacing, de-noising, quantization, and dequantization. | 12-23-2010 |
Shibly S. Ahmed, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110176363 | JUNCTION LEAKAGE SUPPRESSION IN MEMORY DEVICES - A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. | 07-21-2011 |
Tanvir Ahmed, Hayward, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090144804 | METHOD AND APPARATUS TO SUPPORT PRIVILEGES AT MULTIPLE LEVELS OF AUTHENTICATION USING A CONSTRAINING ACL - Embodiments of the present invention provide systems and techniques for creating, updating, and using an ACL (access control list). A database system may include a constraining ACL which represents a global security policy that is to be applied to all applications that interact with the database. By ensuring that all ACLs inherit from the constraining ACL, the database system can ensure that the global security policy is applied to all applications that interact with the database. During operation, the system may receive a request to create or update an ACL. Before creating or updating the ACL, the system may modify the ACL to ensure that it inherits from the constraining ACL. In an embodiment, the system grants a privilege to a user only if both the ACL and the constraining ACL grant the privilege. | 06-04-2009 |
| 20100281060 | TYPE SYSTEM FOR ACCESS CONTROL LISTS - A method and storage media for performing access resolution using ACL types is provided. Under an AND semantic, an intersection set formed from the types of multiple ACLs protecting a resource may be utilized to efficiently determine whether a request for a privilege to access the resource is granted or denied. If the privilege is not a member of the intersection set, the privilege cannot be granted. A union set may be used for an OR semantic. A global ACL type may represent all privileges system-wide or application-wide. A global ACL may represent a system-wide or application-wide access policy. A conjunction of a global ACL and a regular ACL may be stored in a cache. The union set, intersection set, or access resolution may also be cached for subsequent request processing. | 11-04-2010 |
| 20110055918 | ACCESS CONTROL MODEL OF FUNCTION PRIVILEGES FOR ENTERPRISE-WIDE APPLICATIONS - Techniques are provided for access control in a system. A request is received for checking whether a subject has a privilege for a resource. A security class that defines a plurality of privileges that include the requested privilege is determined. One or more access control lists have been configured for the security class. The one or more access control lists comprise one or more access control entries. Each of the one more access control entry defines whether one or more subjects has been granted or denied to zero, one or more of the plurality of privileges defined in the security class. Based on the access control lists configured for the security class, it is determined whether the subject should be granted the privilege for the requested resource. | 03-03-2011 |
Zahid Ahmed, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100223633 | API AND BUSINESS LANGUAGE SCHEMA DESIGN FRAMEWORK FOR MESSAGE EXCHANGES - A server system facilitates an exchange of messages with a remote client application. The server system includes a plurality of application servers hosting a plurality of applications. A plurality of Application Program Interfaces (APIs) provides programmatic access to the plurality of applications, each of the APIs being configured to receive request messages compiled by the remote client application. First and second request messages, respectively addressed to first and second APIs of the plurality of APIs by a remote client application, each comprise at least one common data component. Further, the first request message includes a first payload specific to the first API, and the second request message includes a payload specific to the second API. | 09-02-2010 |
Zahid N. Ahmed, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100205178 | DATA MANAGEMENT SYSTEM AND METHOD TO HOST APPLICATIONS AND MANAGE STORAGE, FINDING AND RETRIEVAL OF TYPED ITEMS WITH SUPPORT FOR TAGGING, CONNECTIONS, AND SITUATED QUERIES - A data management method to host applications and manage storage, finding and retrieval of typed items with support for tagging, connections, and situated queries is provided. | 08-12-2010 |
| 20110167430 | API AND BUSINESS LANGUAGE SCHEMA DESIGN FRAMEWORK FOR MESSAGE EXCHANGES - A server system facilitates an exchange of messages with a remote client application. The server system includes a plurality of application servers hosting a plurality of applications. A plurality of Application Program Interfaces (APIs) provides programmatic access to the plurality of applications, each of the APIs being configured to receive request messages compiled by the remote client application. First and second request messages, respectively addressed to first and second APIs of the plurality of APIs by a remote client application, each comprise at least one common data component. Further, the first request message includes a first payload specific to the first API, and the second request message includes a payload specific to the second API. | 07-07-2011 |
| 20110231435 | DATA MANAGEMENT SYSTEM AND METHOD TO HOST APPLICATIONS AND MANAGE STORAGE, FINDING AND RETRIEVAL OF TYPED ITEMS WITH SUPPORT FOR TAGGING, CONNECTIONS, AND SITUATED QUERIES - A data management method to host applications and manage storage, finding and retrieval of typed items with support for tagging, connections, and situated queries is provided. | 09-22-2011 |
Zahir Mohammad Ahmed, Torrance, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090128058 | Overload Protection Circuit - A current shut-off overload protection circuit useful for fluorescent lamp ballast protection and the like has at least one power transistor for supplying a load current to a circuit load, a protection circuit comprising a current sensing resistance connected for developing a voltage drop related to the circuit load, and a switching diode having a control input operative for turning off the power transistor by removing a bias level, as by grounding the transistor base, responsive to a preset level of the voltage drop such that the load current to the load is switched off upon the load current exceeding a maximum acceptable load current represented by a preset level of the voltage drop. | 05-21-2009 |