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Agrawal, Bangalore
Ajay Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20110158149 | MULTIMEDIA GATEWAY FOR USE IN A NETWORKED HOME ENVIRONMENT - Multimedia gateway for use in a networked home environment is disclosed. In one embodiment, in a method for delivering broadcast multimedia content in a networked home environment, a radio frequency (RF) signal is received. The RF signal is then converted into an IP stream. It is determined whether the IP stream is an IP data stream or an IP video stream and based on the outcome of the determination, the IP stream is sent to one or more televisions, one or more computing devices, and/or one or more telephones. | 06-30-2011 |
Ankit Kumar Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20090306882 | SYSTEM, APPARATUS, OR METHOD FOR ENHANCED ROUTE DIRECTIONS - Embodiments of methods, apparatuses, devices and systems associated with generating a textual explanation of a route including POI information are disclosed. | 12-10-2009 |
Atul Kumar Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20110092328 | SINGLE PLANETARY, SINGLE MOTOR/GENERATOR HYBRID POWERTRAIN WITH THREE OR MORE OPERATING MODES - A hybrid powertrain has an engine, an input member, an output member, and a stationary member, and includes a single planetary gear set having a first, a second, and a third member. The input member is connected for common rotation with the engine and the output member is connected for common rotation with the second member. A single motor/generator is continuously connected for common rotation with the third member. A starter motor is operatively connected to the engine for starting the engine. A first torque-transmitting mechanism is selectively engagable to connect the input member for rotation with the first member. A second torque-transmitting mechanism is selectively engagable to ground the first member to the stationary member. A third torque-transmitting mechanism is selectively engagable to ground the third member to the stationary member. The powertrain is operable in an electric-only operating mode, an engine-only operating mode, and an electrically-variable operating mode. | 04-21-2011 |
| 20110111905 | SINGLE PLANETARY HYBRID POWERTRAIN WITH AT LEAST THREE ELECTRICALLY-VARIABLE OPERATING MODES - A hybrid powertrain has an engine, an input member, an output member, and a stationary member, and includes a single planetary gear set having a first, a second, and a third member. The input member is connected for common rotation with the engine. The output member is connected for common rotation with the second member. A first and a second motor/generator are provided, as well as five torque-transmitting mechanisms, including only one brake. The torque-transmitting mechanisms are engagable in different combinations to establish at least two electric-only operating mode, at least two engine-only operating mode, and at least three electrically-variable operating modes. In one embodiment, an electric torque converter operating mode is provided, and may be the default mode in case of motor/generator failure. | 05-12-2011 |
| 20120010796 | CONTROL SYSTEM AND METHOD FOR SHIFT QUALITY AND PERFORMANCE IMPROVEMENT IN MANUAL TRANSMISSIONS USING ENGINE SPEED CONTROL - A control system for an engine of a vehicle includes a shift forecasting module that forecasts one of an upshift and a downshift of a manual transmission based on vehicle acceleration, clutch pedal position, acceleration pedal position and brake pedal position. A gear state calculating module determines a current gear state based on a speed of the engine and a speed of the vehicle. A next gear state calculating module determines a next gear state. The next gear state is based on the current gear state and the one of the upshift and downshift. A next engine speed calculating module estimates an estimated engine speed based on the next gear state and the vehicle speed. An engine speed control module adjusts the engine speed based on the estimated engine speed. | 01-12-2012 |
Mahima Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20090201703 | Systems and Methods for Uninterruptible Power Supply Control - Systems and methods are provided for distributing power to a load by controlling an uninterruptible power supply that has an inverter and a filter, where the filter has an inductor and a capacitor. The systems and methods apply a pulse width modulation control signal to the inverter, sample inverter inductor current and compare the inductor current to a reference current. A duty cycle of the pulse width modulation control signal is adjusted to drive the inductor current at a second sampling time to a value substantially equal to a reference current at a first sampling time. The systems and methods can filter harmonic distortion from output signals and control uninterruptible power supply output. | 08-13-2009 |
| 20110278934 | DIGITAL CONTROL METHOD FOR OPERATING THE UPS SYSTEMS IN PARALLEL - Systems and methods of operating uninterruptible power supplies in parallel in a power distribution system to provide power to a load are provided. At least one uninterruptible power supply inverter provides power to the load. A communication interface provides a measured value of at least one of inverter output current of a first uninterruptible power supply and a measured value of the load current to a second uninterruptible power supply, and receives a measured value of at least one of inverter output current of the second uninterruptible power supply and the load current. A controller controls the uninterruptible power supplies to operate in one of a master state and a slave state. In the master state the uninterruptible power supply is configured to control the voltage to the load, and in the slave state the uninterruptible power supply is configured to determine a reference output current value based at least in part on at least one of the measured value of inverter output current of the second uninterruptible power supply and the measured value of the load current. The uninterruptible power supply in the slave state drives its inverter output current toward the reference output current value to provide its share of the load current. | 11-17-2011 |
Meghna Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20110283014 | Distribution of Multimedia Content over a Network - Performing transmission of data over network using at least a first and second rate adaptation algorithm. The transmission of data may use a plurality of buffers. It may be determined that a number of available buffers of the plurality of buffers is below a first threshold. Accordingly, data may be transmitted according to the second rate adaptation algorithm which provides increased flowrate. During the transmission of the data, it may be determined that the number of available buffers of the plurality of buffers exceeds a second threshold. Accordingly, data may be transmitted according to the first rate adaptation algorithm that provides increased throughput. | 11-17-2011 |
Neetin Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20100156389 | REDUCING THE EFFECT OF BULK LEAKAGE CURRENTS - A current mirroring circuit is provided. The circuit generally comprises a current source; a first drain extended (DE) MOS transistor, a second DE MOS transistor, a current mirror, and differential amplifier. The current source is generally coupled to the current source at its drain, while the current mirror that is coupled to the sources of the first and second DE MOS transistors and to the current source. The differential amplifier generally has a first input that is coupled to the source of the first DE MOS transistor, a second input that is coupled to the source of the second DE MOS transistor, a first output that is coupled to the gate of the second DE MOS transistor, and a second output that is coupled to the gate of the first DE MOS transistor. | 06-24-2010 |
Neha Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20090111518 | INTERFACE FOR CELLULAR AND LOCAL NON-CELLULAR COMMUNICATIONS - Interface apparatus supports communications between a cellular network and a local non-cellular network, such as a Bluetooth, cordless phone, or PBX network. In an exemplary embodiment, the interface apparatus connects a conventional cellular phone to the base of a conventional cordless phone set. By placing the cordless phone, interface apparatus, and cordless phone base at a location of acceptable cellular signal strength, a user may communicate with the cellular network via the cordless phone set using the cordless phone's handset, even in locations of low cellular signal strength. The orientation of the interface apparatus may be (manually or automatically) controlled using a motorized base to optimize reception of cellular signals. | 04-30-2009 |
Pankaj Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20090255792 | CONTACT ASSEMBLY OF CIRCUIT BREAKER - A contact arm assembly including a plurality of substantially parallel plates having a space between each of the plurality of substantially parallel plates and a plurality of finger assemblies, at least one of the plurality of finger assemblies being pivotally attached to the plurality of substantially parallel plates and being located in the space between each of the plurality of substantially parallel plates, each of the plurality of finger assemblies having a body and an arc runner, the arc runner being locked against the body in at least two locations. | 10-15-2009 |
| 20090255906 | Arc chute assembly for a circuit breaker - An arc chute assembly includes a housing having a lateral axis and a quenching portion disposed within the housing. The quenching portion includes at least two deion plates being spaced along the lateral axis of the housing and each having a cut portion wherein the cut portions are staggered along the lateral axis with respect to one another and are configured to mitigate an arc. | 10-15-2009 |
| 20090257173 | SECONDARY CIRCUIT TERMINAL BLOCK DESIGN FOR FIXED TYPE CIRCUIT BREAKERS - A circuit breaker apparatus is provided and includes a circuit breaker, having a housing surface perpendicular to a plane of a front side of the circuit breaker and internal components, a terminal block structurally coupled to the housing surface, first terminal housings arrayed on the terminal block to each support first components and to be receptive of second terminal housings each of which supports second components, at least some of which are electrically coupled to the internal components, to be electrically coupled to at least some of the first components, and an access block. The access block is disposed on the terminal block and has apertures defined therein to provide for front-side access to the first terminal housings. | 10-15-2009 |
Pramod Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20110301938 | MULTILINGUAL TAGGING OF CONTENT WITH CONDITIONAL DISPLAY OF UNILINGUAL TAGS - One or more computers are programmed to obtain an identifier of a natural language (“session language”). Additionally, the one or more computers are programmed to create and store in a computer memory, a webpage to be displayed to the user, including at least a title of a piece of content. In addition, the one or more computers automatically use the language identifier to select from among multiple tags that are expressed in multiple languages, a set of tags in the session language. One or more tags in the selected set are then stored in the web page in the computer memory, if the selected set is non-zero. If the number of tags in the selected set is zero (i.e. there exist no tags in the session language), in some embodiments a message is included in the webpage, indicating that there are no tags available. | 12-08-2011 |
Rajkumar Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20120089383 | METHODS AND SYSTEMS FOR PERFORMING TIMING SIGN-OFF OF AN INTEGRATED CIRCUIT DESIGN - Systems and methods for performing timing sign-off of an integrated circuit design are disclosed. In one example embodiment the integrated circuit design is divided into plurality of blocks based on a pre-determined logic. A timing model is extracted for each block using static timing analysis (STA), wherein the extracted timing model includes timing information. An integrated circuit design level STA is performed using the extracted timing model of all of the plurality of blocks to obtain first integrated circuit design timing. The first integrated circuit timing is compared with a predetermined performance criterion. | 04-12-2012 |
Sandeep Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20110197009 | 12C-BUS INTERFACE WITH PARALLEL OPERATIONAL MODE - An electronic circuit has an interface for an I | 08-11-2011 |
Santosh K. Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20120068993 | TECHNIQUES FOR CHANGING IMAGE DISPLAY PROPERTIES - Techniques are described that can be used to adjust a refresh rate of a display device. For example, the refresh rate change can be triggered by a user application for a variety of circumstances such as a change in power source from AC to DC or display of 24 frames per second (fps) video. Contents of a primary buffer can be copied to a secondary buffer and a display engine can read video from the secondary buffer to provide video to a display. The clock rate of a clock used to read out pixels can be adjusted using software commands. Video is written to a third buffer and during a vertical blanking interval the display engine reads frames from the third buffer instead of the second buffer. | 03-22-2012 |
Somesh Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20100074099 | Access Port Adoption to Multiple Wireless Switches - An apparatus, network and techniques for minimizing wireless network downtime associated with a wireless switch failure are disclosed. Access ports are adopted to multiple wireless switches wherein one switch operates to exchange data and control traffic with the access port and remaining switches operate to exchange control traffic with the access port. In the event of a link failure between the wireless switch exchanging data and control traffic with the access port, the access port remains adopted to remaining switches and exchanges data and control traffic with one of the remaining switches. | 03-25-2010 |
| 20100302985 | METHODS AND APPARATUS FOR TRANSMITTING DATA BASED ON INTERFRAME DEPENDENCIES - Methods and apparatus are provided for reliably transmitting data. A method comprises identifying a metric for a first frame of a plurality of frames, wherein the metric is indicative of decoding significance for the first frame among the plurality of frames. When the metric corresponds to a relatively high decoding significance, the method further comprises transmitting the first frame in accordance with an enhanced transmission scheme. When the metric corresponds to a relatively low decoding significance, the method further comprises transmitting the first frame in accordance with a default transmission scheme. The reliability of the enhanced transmission scheme is greater than the reliability of the default transmission scheme. | 12-02-2010 |
| 20110158208 | UPDATING AN IGMP MEMBERSHIP REPORT WHEN A WIRELESS CLIENT DEVICE ROAMS ACROSS IP SUBNETS - A network is provided that includes a first WLAN infrastructure device (WID) that defines a first subnet, and a wireless client device (WCD) that is initially associated with the first WID. The WCD associates with a “current” WID when the wireless client device roams from the first subnet to a second subnet defined by the current WID. Upon successful association, the current WID unicasts a first IGMP query message (IGMPQM) to the WCD that has a MAC header including a destination MAC address that is set to a MAC address of the WCD. | 06-30-2011 |
Sumit Kumar Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20090157828 | TECHNIQUES FOR SPECIFYING RECIPIENTS IN AN ELECTRONIC MAIL (EMAIL) SYSTEM - Techniques for specifying recipients in an electronic email (email) system are presented. A sender of an email includes a rule in a sender field of the email, rather than a recipient address, an alias address book identifier, or a distribution list identifier. The rule is evaluated to dynamically identify multiple recipient email addresses for the email. The multiple recipient email addresses then replace the rule included within the sender field and the email is sent over a network to recipients associated with the multiple recipient email addresses. | 06-18-2009 |
| 20090172099 | FREIGHT BACKBONE MESSAGING ARCHITECTURE - A messaging architecture extends the communication capability of complex systems in existing enterprises. The architecture implements sophisticated messaging capability between typically disparate order management and shipping systems. As a result, the messaging architecture greatly streamlines order processing and shipping, increases productivity, increases system uptime and provides a baseline solution for customers that desire integrated order processing and shipping. | 07-02-2009 |
Sunil Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20100318793 | Permission-Based Dynamically Tunable Operating System Kernel - A server includes a central processing unit and electronic memory communicatively coupled to the central processing unit. The memory stores a dynamically tunable operating system kernel that includes at least one tunable implemented as a plurality of states. Each application managed by the operating system is assigned to one of these states according to a permission level association with the application. Each state defines a range of automated tuning of the tunable that is authorized to applications assigned to the state. | 12-16-2010 |
Vinay Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20090009206 | BIST DDR MEMORY INTERFACE CIRCUIT AND METHOD FOR TESTING THE SAME - An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit comprises a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a plurality of sequential input/output bit-pair signals corresponding to an internal data strobe input signal and a phase shifted data strobe output signal respectively. A second multiplexer selects a reference data input bit that corresponds to one of the internal data strobe input signals of the input/output bit pair signals s from the delay line blocks and a third multiplexer for selecting a reference data output bit that corresponds to one of the phase shifted data strobe output signals from the input/output bit pair signals. A phase detector for determining a phase difference between the reference data input bit and the reference data output bit and outputting a phase difference value. | 01-08-2009 |
| 20110026343 | BIST DDR MEMORY INTERFACE CIRCUIT AND METHOD FOR TESTING THE SAME - An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal. A phase detector determines a phase difference between the selected internal data strobe input signal and the selected phase shifted data strobe output signal and outputs a phase difference value. | 02-03-2011 |
| 20110176374 | BIST DDR MEMORY INTERFACE CIRCUIT AND METHOD FOR TESTING THE SAME - An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal. A phase detector determines a phase difference between the selected internal data strobe input signal and the selected phase shifted data strobe output signal and outputs a phase difference value. | 07-21-2011 |
Vrishti Agrawal, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20100127918 | Generation of Multi-satellite GPS Signals in Software - A method for testing GPS receivers may read GPS files with data for a plurality of GPS satellites, and two or more GPS satellites may be selected from that data. The method may receive parameters for a GPS receiver to be tested. The method may generate two or more GPS signals for the two or more selected GPS satellites. The method may operate on the two or more GPS signals using the received parameters for the GPS receiver to generate two or more calculated GPS signals. These two or more calculated GPS signals may be re-sampled to a common rate. The two or more re-sampled GPS signals may be added together to create a composite GPS signal. The composite GPS signal may be generated using a hardware signal generator, where the composite GPS signal used to test the GPS receiver. | 05-27-2010 |