| Patent application number | Description | Published |
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| 20090014709 | PROCESS FOR MANUFACTURING AN ARRAY OF CELLS INCLUDING SELECTION BIPOLAR JUNCTION TRANSISTORS WITH PROJECTING CONDUCTION REGIONS - A process manufactures an array of cells in a body of semiconductor material wherein a common conduction region of a first conductivity type and a plurality of shared control regions, of a second conductivity type, are formed in the body. The shared control regions extend on the common conduction region and are laterally delimited by insulating regions. Then, a grid-like layer is formed on the body to delimit a first plurality of empty regions directly overlying the body and conductive regions of semiconductor material and the first conductivity type are formed by filling the first plurality of empty regions, each conductive region forming, together with the common conduction region and an own shared control region, a bipolar junction transistor. | 01-15-2009 |
| 20100078619 | RESISTIVE MEMORY CELL AND METHOD FOR MANUFACTURING A RESISTIVE MEMORY CELL - A resistive memory cell includes a structural layer, a pore in the structural layer, a selector, having a coupling terminal accommodated in the pore, and a storage element of a resistive memory material, arranged in the pore and electrically coupled to the coupling terminal of the selector. The storage element has a tubular portion, extending transversely to an electrical coupling interface of the coupling terminal. | 04-01-2010 |
| 20100308296 | PHASE CHANGE MEMORY CELL WITH SELF-ALIGNED VERTICAL HEATER - A self-aligned vertical heater element is deposited directly on the silicide of a selection device, and a phase change chalcogenide material is deposited directly on the vertical heater element. The fabrication process allows for self-alignment between the chalcogenide line and vertical heater element. In an embodiment, the vertical heater element is L-shaped, having a vertical wall along the wordline direction and a horizontal base. The vertical wall and the horizontal base may have the same thickness. | 12-09-2010 |
| 20110141799 | REVERSING A POTENTIAL POLARITY FOR READING PHASE-CHANGE CELLS TO SHORTEN A RECOVERY DELAY AFTER PROGRAMMING - A potential supplied to selected cells in a Phase Change Memory (PCM) is reversed in polarity following a program operation to suppress a recovery time and provide device stabilization for a read operation. | 06-16-2011 |
| Patent application number | Description | Published |
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| 20080259677 | Memory including bipolar junction transistor select devices - An array is formed by a plurality of cells, wherein each cell is formed by a bipolar junction selection transistor having a first, a second, and a control region. The cell includes a common region, forming the second regions of the selection transistors, and a plurality of shared control regions overlying the common region. Each shared control region forms the control regions of a plurality of adjacent selection transistors and accommodates the first regions of the plurality of adjacent selection transistors as well as contact portions of the shared control region. Blocks of adjacent selection transistors of the plurality of selection transistors share a contact portion and the first regions of a block of adjacent selection transistors are arranged along the shared control region between two contact portions. A plurality of biasing structures are formed between pairs of first regions of adjacent selection transistors, for modifying a charge distribution in the shared control region below the biasing structures. | 10-23-2008 |
| 20100155894 | Fabricating Bipolar Junction Select Transistors For Semiconductor Memories - A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced. | 06-24-2010 |
| 20100165724 | WORD-LINE DRIVER INCLUDING PULL-UP RESISTOR AND PULL-DOWN TRANSISTOR - Embodiments include but are not limited to apparatuses and systems including a plurality of memory cells, each memory cell including a selector and a storage element coupled to the selector. A word-line may be coupled to the memory cells and may have a word-line driver including a pull-up resistor coupled to the selectors for the memory cells to access respective storage elements of the memory cells. Other embodiments may be described and claimed. | 07-01-2010 |
| 20110111572 | Memory Including Bipolar Junction Transistor Select Devices - An array is formed by a plurality of cells, wherein each cell is formed by a bipolar junction selection transistor having a first, a second, and a control region. The cell includes a common region, forming the second regions of the selection transistors, and a plurality of shared control regions overlying the common region. Each shared control region forms the control regions of a plurality of adjacent selection transistors and accommodates the first regions of the plurality of adjacent selection transistors as well as contact portions of the shared control region. Blocks of adjacent selection transistors of the plurality of selection transistors share a contact portion and the first regions of a block of adjacent selection transistors are arranged along the shared control region between two contact portions. A plurality of biasing structures are formed between pairs of first regions of adjacent selection transistors, for modifying a charge distribution in the shared control region below the biasing structures. | 05-12-2011 |
| 20110128779 | MEMORY INCLUDING A SELECTOR SWITCH ON A VARIABLE RESISTANCE MEMORY CELL - Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed. | 06-02-2011 |
