| Patent application number | Description | Published |
|---|
| 20080225568 | DENSE READ-ONLY MEMORY - In one embodiment, a read-only memory (ROM) is provided that includes: a plurality of word lines; a plurality of bit lines; a plurality of memory cell transistors arranged in rows corresponding to the word lines such that if a word line is asserted the corresponding memory cell transistors are conducting, the memory cell transistors also being arranged in columns corresponding to the bit lines; wherein each column of memory cell transistors is arranged into column groups, each column group including an access transistor coupled to the corresponding bit line, the remaining transistors in the column group being coupled in series from the access transistor to a last transistor in the column group, the last transistor in the column group being coupled to a voltage node. | 09-18-2008 |
| 20080225613 | MEMORY ROW AND COLUMN REDUNDANCY - In one embodiment, a memory includes a row and/or column redundancy architecture that uses binary cells to indicate whether a given row or column of memory cells is faulty. The binary cell is adapted to store a “repair true” signal in response to a conventional access to the corresponding row or column and also the assertion of a set signal. | 09-18-2008 |
| 20080266935 | DRAM STORAGE CAPACITOR WITHOUT A FIXED VOLTAGE REFERENCE - In one embodiment, a DRAM is provided that includes a plurality of memory cells, each memory cell including an access transistor and a storage capacitor, wherein the storage capacitor includes a first node coupled to the access transistor and a second node isolated from the first node, the second node comprising signal-bearing metal conductors. | 10-30-2008 |
| 20090010041 | Hybrid DRAM - In one embodiment, a hybrid DRAM is provided that includes: a sense amplifier including a differential amplifier and regenerative latch, wherein the differential amplifier and regenerative latch are constructed using core transistors that have a relatively thin gate oxide; and a plurality of memory cells coupled to the sense amplifier through a pair of bit lines, wherein each memory cell includes an access transistor coupled to a storage cell, the access transistor having a relatively thick gate oxide, whereby the storage capacitor is capable of being charged to a VIO power supply voltage that is greater than a VDD power supply voltage for the core transistors. | 01-08-2009 |
