| Patent application number | Description | Published |
|---|
| 20080278190 | Testing fuse configurations in semiconductor devices - Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal. | 11-13-2008 |
| 20090257296 | Programmable memory repair scheme - The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element. | 10-15-2009 |
| 20100100661 | PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES - An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols. | 04-22-2010 |
| 20110016352 | PROGRAMMABLE MEMORY REPAIR SCHEME - The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element. | 01-20-2011 |
| 20110063897 | DIFFERENTIAL READ AND WRITE ARCHITECTURE - A memory cell includes a pair of magnetic tunnel junctions and a pair of associated transistors. The magnetic tunnel junctions of the pair are differentially disposed so that in response to the applied voltages, when one them stores a logic one, the other one stores a logic zero. Accordingly, the read operation margin is increased by a factor of two. The true and complementary bit lines of the differential memory cell are coupled to a sense amplifier. Consequently, the need for using reference bit lines is eliminated. | 03-17-2011 |
| 20110063898 | METHOD AND SYSTEM FOR PROVIDING A HIERARCHICAL DATA PATH FOR SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY - A method and system for providing a magnetic memory are described. The method and system include providing memory array tiles (MATs), intermediate circuitry, global bit lines, global word lines, and global circuitry. Each MAT includes magnetic storage cells, bit lines, and word lines. Each of the magnetic storage cells includes at least one magnetic element and at least one selection device. The magnetic element(s) are programmable using write current(s) driven through the magnetic element(s). The bit lines and the word lines correspond to the magnetic storage cells. The intermediate circuitry controls read and write operations within the MATs. Each global bit line corresponds to a first portion of the plurality of MATs. Each global word line corresponds to a second portion of the MATs. The global circuitry selects and drives part of the global bit lines and part of the global word lines for the read and write operations. | 03-17-2011 |
| 20110141802 | METHOD AND SYSTEM FOR PROVIDING A HIGH DENSITY MEMORY CELL FOR SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY - A method and system for providing a magnetic memory are described. The method and system include providing a plurality of magnetic storage cells, a plurality of bit lines corresponding to the magnetic storage cells, a plurality of word lines corresponding to the magnetic storage cells, and a common voltage plane coupled with the magnetic storage cells. Each of the magnetic storage cells includes at least one magnetic element and at least one selection device coupled with the magnetic element(s). The magnetic element(s) are programmable using at least one write current driven through the magnetic element(s). The common voltage plane is coupled with the memory cells. The write current(s) flow between the common voltage plane, the magnetic element(s), and at least one of the bit lines. | 06-16-2011 |
| 20110202789 | PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES - An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols. | 08-18-2011 |
