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| 20110178903 | PERSONAL IDENTIFICATION NUMBER CHANGING SYSTEM AND METHOD - Systems and methods are provided for enabling a cardholder to authenticate and change a current PIN associated with a chip card using a chip card interface device (CCID) having a chip card input/output device configured for interacting with the chip card. A PIN entry device receives from the cardholder a current PIN, which is communicated to the chip card along with a verify command. The chip card compares the current PIN input by the cardholder with the PIN stored on the chip card. If the cardholder input is verified, the cardholder can input a desired new PIN. The CCID then communicates a locked PIN through a host to the issuing bank's backend system, which unlocks the PIN and stores the desired PIN. The backend system then creates a PIN change script including the new PIN and communicates the script to the chip card over the network. The chip card runs the script, which instructs the chip card to store the new PIN in place of the previous PIN. | 07-21-2011 |
| 20110179290 | AUTHENTICATING A CHIP CARD INTERFACE DEVICE - A system is configured for authenticating a chip card interface device (CCID) during a transaction with the CCID. The system has a communication device configured for communicating with the CCID over a network and a processing device coupled with the communication device. The processing device is configured for receiving a transaction initiation communication from the CCID and instructing the communication device to communicate a request for authentication information including a random number to the CCID. The CCID encrypts the random number with a unique chip key (UCK) previously created with a master chip key (MCK). Then, the CCID communicates the encrypted random number to the system along with a serial number. The system recalculates the UCK using the serial number, encrypts a copy of the random number using the recalculated UCK and compares the encrypted copy with the encrypted random number received from the CCID to authenticate the CCID. | 07-21-2011 |
| 20110179494 | PROTECTING DATA STORED IN A CHIP CARD INTERFACE DEVICE IN THE EVENT OF COMPROMISE - A chip card interface device (CCID) is configured for protecting data stored at the CCID in the event of a compromise. The CCID has a housing and a compromise detection system including one or more detection devices configured for detecting a compromise of the housing. The compromise detection system is configured for generating a detection signal indicating the detected compromise. A data protection system is coupled with the compromise detection system and includes a memory device and a processing device coupled with the compromise detection system. The processing device is for receiving the detection signal and erasing data stored on the memory device based on the detection signal in some embodiments. In some embodiments, the processing device also activates a locking function for rendering itself inoperable based on the detection signal. | 07-21-2011 |
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| 20110311186 | Fibre Optic Connector Assembly and Access Tool Kit - A fibre optic connector is provided comprising: a connector plug, which may be inserted into an associated socket in a longitudinal direction; a resilient leg, depending at a first end thereof from the first connector plug, and having a depressible part, distal therefrom, depressible towards the first connector plug; and a guard cover, configured to prevent access to the depressible part of the resilient leg in its direction of depression, but to permit access to the resilient leg in the longitudinal direction through an access aperture, the access aperture being aligned with the depressible part of the resilient leg on an axis parallel with the longitudinal direction, to allow depression of the resilient leg through the access aperture directly. A corresponding extraction tool and methods, loopback connector, blanking plug, blanking plate and patch panel are also provided. | 12-22-2011 |
| 20110318949 | Modular Connector - A modular connector is provided comprising: a connector plug, which may be inserted into an associated socket in a first longitudinal direction; a resilient leg, depending at a first end thereof from the connector plug, and having a depressible part, distal therefrom, depressible towards the connector plug; and a guard cover, configured to prevent access to the depressible part of the resilient leg in its direction of depression, but to permit access to the resilient leg in the longitudinal direction through an access aperture, the access aperture being aligned with the depressible part of the resilient leg on an axis parallel with the longitudinal direction, to allow depression of the resilient leg through the access aperture directly. A corresponding extraction tool and methods, loopback connector, blanking plug, blanking plate and patch panel are also provided. | 12-29-2011 |
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| 20090303135 | ANTENNAS - Embodiments of the invention relate to a broadband antenna structure and an antenna arrangement comprising the antenna structure and an electronic device. In one aspect, the antenna employs an electrically conductive enclosure with a closed end, over which a non-electrically conductive cover is placed. A radiating portion of the antenna feed layer comprising a conductive patch antenna element is placed in between the enclosure and the cover. This patch antenna element design is inherently broader band than that of conventional cavity-backed slot-radiating antennas, which are constrained in bandwidth by the need to keep the cavity formed in the enclosure small, so that the column elements may be arranged in an array at substantially half-wavelength spacing. The new design suffers less compromise in terms of bandwidth in achieving the same size constraint. This is achieved in part by the dielectric constant of the dielectric material of the cover reducing the required size of the conductive antenna element, compared to the size that would be required if the radiating portion were covered with a material with the dielectric constant of air. In another aspect, this broadband antenna structure is connected with an electronic device to form an antenna arrangement, wherein a portion of the antenna feed layer extends outside of the antenna housing through an opening in a surface of the antenna housing, said portion being within the electronic device enclosure of the electronic device. Connecting the electronic device directly to the antenna according to embodiments of the invention reduces the amount of coaxial cables needed or eliminates the need for coaxial cables completely. As a result the usual costs associated with coaxial cables, the RF losses introduced by the cables which can compromise the system performance, possible failure of the cables, lease costs for the space the cables occupy and lease costs for large footprint of the building or cabinet housing the electronic device are substantially reduced or eliminated. | 12-10-2009 |
| 20100046421 | Multibeam Antenna System - Embodiments of the invention relate to beamforming antennas such as can be used in space division multiplexing systems. Space division multiplexing can be used to increase data capacity in wireless networks by enabling different base stations to transmit signals within the same frequency band. Each antenna beam can potentially be used to establish a communication link within an area of wireless coverage, and other communication links established on other antenna beams then represent interference to that user. In order to reduce interference, narrow beamwidths are desirable. These are typically achieved by increasing the aperture of the antenna in the azimuth plane, and in arrangements that require finely divided angular sectors, a greater number of antennas will be required to give three hundred and sixty degree coverage. As a result, there is potentially a large increase in the total surface area of antennas which is undesirable, as it leads to increased wind loading of an antenna tower. Embodiments of the invention provide an arrangement in which data are transmitted from a first transmitter to a first receiver using a first antenna beam, and data are transmitted from a second transmitter to a second receiver using a second antenna beam. The first antenna beam is formed by splitting the signal from the first transmitter into two parts with a first phase relationship between the parts, each part being connected to an antenna. A second antenna beam is formed by splitting the signal from the second transmitter into two parts with a second phase relationship between the parts, each part being connected to one of the two antennas. An advantage of embodiments of the invention is that data can be transmitted from different transmitters at the same frequency without interference, while presenting a smaller antenna aperture than is required with conventional systems. | 02-25-2010 |
| 20110181482 | Antenna - Embodiments of the invention relate to an antenna structure and are particularly suited to array antennas. Conventionally, an antenna of the cavity-backed slot-radiating type comprises a slot formed in an end of an electrically conductive enclosure, which slot may be energised by a radiating element in registration with the slot. A feed network may connect to the radiating element via a transmission line formed by a conductive track on a feed layer located between the enclosure and an electrically conductive cover. A slot is formed in the section of the cover that covers the end of the cavity in which a slot is formed, such that the two slots are of substantially the same size and shape. A problem with this structure is that the cavity is difficult to mould in one piece and it can be difficult to achieve alignment of respective slots; as a result it is relatively costly to manufacture. Also, it is difficult to insert dielectric material into the enclosure to adjust the performance parameters of the antenna. An antenna according to an embodiment of the invention employs an enclosure having an aperture in one end; in preferred arrangements the aperture provides the enclosure with a substantially open end, over which the cover is placed. The cover has a slot therein, of a smaller size than the size of the aperture presented by the open ended enclosure and the slot in the cover then acts as the radiating slot. The benefit is that it is then easier to insert dielectric material into the enclosure and the enclosure is easier to mould in one piece, leading to a potential cost reduction. | 07-28-2011 |
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| 20080221283 | Loop Reactor for Emulsion Polymerisation - Method of emulsion polymerisation wherein a reactor comprising a closed reactor loop is continuously charged with fresh monomers and water phase at substantially the same rate as the rate of an overflow of reactor charge discharged into a secondary line section. The reactor charge is continuously recirculated within the reactor loop. The discharge rate and the circulation rate in the loop are balanced such as to result in a monomer content in the loop of less than 12 wt. %. The secondary line section has a volume of less than twice the volume of the reactor loop. | 09-11-2008 |
| 20090306288 | EMULSION POLYMERISATION PROCESS - An emulsion polymerisation process using a redox initiator comprising a reductant and an oxidant, wherein monomers are mixed into a carrier liquid, e.g. water, to make a pre-emulsion, which is then supplied to a reactor comprising one or more circulation loops, an outlet, and a circulation pump for circulating a reactor charge within the circulation loop, characterised in that the reductant is added to the pre-emulsion before it is mixed into the reactor charge and the oxidant is mixed into the reactor charge, e.g., via the water-phase feed. | 12-10-2009 |
| 20100252073 | LOOP REACTOR FOR EMULSION POLYMERISATION - A polymerisation reactor comprising one or more circulation loops with one or more inlets for raw material, one or more outlets, and a circulation pump for circulating a reactor charge within the circulation loop. A by-pass line for by-passing the circulation pump connects a point of the loop upstream of the pump with a point downstream of the pump, both points being provided with a three way valve. | 10-07-2010 |
| 20110150711 | Loop Reactor for Emulsion Polymerisation - A polymerization reactor comprising a circulation loop, an inlet for raw material, an outlet, driving means for circulating a reactor charge within the circulation loop, and a pig station for storing, launching, and receiving cleaning pigs. The pig station comprises a lid to cover an opening enabling removal of the cleaning pig. The pig station is constructed as a box with a cylindrical bore connected at both ends to the circulation loop, the bore having a central part with a diameter which is larger than the inner diameter of the circulation loop. At a transitional part at the outer ends of the bore the bore diameter narrows down to be substantially equal to the inner tube diameter of the circulation loop. Over at least a part of the inner bore substantially half of the circular cross-section is formed in the removable lid. | 06-23-2011 |
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| 20090322608 | ANTENNA SYSTEM - Embodiments of the invention are concerned with improvements to antenna systems, in particular beamforming antenna systems. Embodiments provide an improved beamformer arrangement for receiving and transmitting of signals by antenna elements. Embodiments are particularly well suited to use for transceiving of radio signals by base stations, such as are commonly found in cellular networks. In one aspect, embodiments provide a beamformer for use in processing signals received, or transmitted, by a first antenna element, the beamformer comprising a first set of ports and a second set of ports, wherein the first set of ports is connected to at least two antenna elements including said first antenna element and the second set of ports is connected to a connecting port, wherein the beamformer is arranged to generate at least first and second output beams from signals received from the at least two antenna elements and to transform signals received via the second set of ports into signals for transmission by the at least two antenna elements, wherein the beamformer is arranged to combine said generated at least first and second output beams at the connecting port such that said signals from said first antenna element are constructively combined at the connecting port, and to combine said at least first and second output beams at the connecting port such that signals from antenna elements other than the first antenna element are destructively combined at the connecting port, wherein the connecting port is arranged so as to provide access to individual said signals received, or transmitted, by said at least two antenna elements. In particularly preferred arrangements the first set of ports is connected to three or four antenna elements. | 12-31-2009 |
| 20120001801 | Antenna System - A beamformer is arranged to receive an input from a first antenna element and from at least one other antenna element and to generate at least a first and second output beam. The first and second output beams are combined at a connecting port such that signals received at the first antenna element are constructively combined at the connecting port and signals received at another antenna element or elements are destructively combined at the connecting port, so that a receiver connected to the connecting port may receive signals from the first antenna element and may not receive signals from the other antenna element or elements. The arrangement may also be used to transmit a signal which is fed into the connecting point from the first antenna element and not from the other antenna element or elements. | 01-05-2012 |
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| 20110148901 | Method and System For Tile Mode Renderer With Coordinate Shader - A method and system are provided in which one or more processors and/or circuits are operable to generate position information for a plurality of primitives utilizing a coordinate shader, one or more lists based on the generated position information, and rendering information for the plurality of primitives utilizing a vertex shader and the generated one or more lists. The generated one or more lists may comprise indices associated with one or more primitives from the plurality of primitives and with one or more tiles from a plurality of tiles in a screen plane. The position information and the one or more lists may be generated during a first rendering phase, and the rendering information may be generated during a second rendering phase different from the first rendering phase. The coordinate shader may perform a subset of the operations supported by the vertex shader. | 06-23-2011 |
| 20110216069 | Method And System For Compressing Tile Lists Used For 3D Rendering - A graphics processing device may generate coordinates for vertices of graphics primitives in a view-space. Tiles are defined within the view-space and are associated with tile lists. Primitives and/or vertices which overlap a tile are determined. Tile lists comprise differentially encoded indices and/or spatial coordinates for overlapping primitives. The differential encoding may or may not be byte aligned. During tile mode graphics rendering, tile lists are utilized to reference vertex attributes and/or primitives. Graphics rendering comprises a tile binning phase and a tile rendering phase. The primitives may comprise a triangle and/or joined triangles that share one or more vertices. For multiple joined primitives, information about shared vertices may be encoded without repetition for each primitive. Coordinates and/or corresponding weights for new vertices are encoded in a tile list and utilized for interpolating properties of the new vertices based on attributes of the original vertices. | 09-08-2011 |
| 20110221743 | Method And System For Controlling A 3D Processor Using A Control List In Memory - A graphics processing device generates control lists for controlling processing of 3D graphics. Control lists comprise primitive data for the 3D graphics, pointers to primitive data and control data. Tags that correspond to records within the control lists may be utilized for the control of processing. The graphics processing device may comprise a 3D pipeline comprising parallel processors. Processing is performed on a tile by tile basis and comprises a tile binning phase and/or a tile rendering phase. The two phases of processing may be performed in parallel on different sets of data. Control lists comprise a main list and/or sub-lists, for example, tile lists. Control lists may comprise links to other lists. Processing control may advance through the control lists without interaction from a driver and/or from a processor that is external to the graphics processing device. | 09-15-2011 |
| 20110227920 | Method and System For a Shader Processor With Closely-Coupled Peripherals - A method and system are provided in which a first instruction associated with a graphics rendering operation may be executed in a shader processor, the shader processor may receive result information associated with an intermediate portion of the graphics rendering operation performed by a peripheral device operably coupled to a register file bus in the shader processor, and the shader processor may execute a second instruction associated with the graphics rendering operation based on the received result information. The register file bus may be utilized for handling execution of intermediate instructions associated with the intermediate portion of the graphics rendering operation. The peripheral device may be accessed via one or more register file addresses associated with the peripheral device. The peripheral device may be operably coupled to the shader processor via a FIFO. | 09-22-2011 |
| 20110242113 | Method And System For Processing Pixels Utilizing Scoreboarding - In a graphics processing device, a plurality of processors write fragment shading results for order-dependent data to a buffer, according to the order in which the data is received. Fragment shading results for order-neutral data is written to the buffer one batch at a time. The order-dependent data comprises spatially overlapping data. Order-neutral data may not overlap. A scheduler controls the order of reception of one batch of data at a time by the processors. The order for receiving the order-dependent data may be determined. The plurality of processors may process the data in parallel. A writing order for writing results to a buffer from the processing in parallel, may be enforced. A portion of the processors may be instructed to wait before writing results to the buffer in a specified order. Processors signal when writing results to the buffer is complete. | 10-06-2011 |
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| 20100135158 | Flow State Aware QoS Management Without User Signalling - Conventional packet network nodes react to congestion in the packet network by dropping packets in a manner which is perceived by users to be indiscriminate. In embodiments of the present invention, indiscriminate packet discards are prevented by causing packets to be discarded according to bandwidth allocations that intelligently track flow sending rates. Flows are allocated bandwidth based on policy information. Where such policy information indicates that the flow should be treated as delay-sensitive, the present invention includes means to allocate an initial minimum rate that will be guaranteed and such flows will also have the use of an additional capacity that varies depending on the number of such flows that currently share an available pool of capacity. This provides a congestion alleviation method which is less annoying to users since communications that have been in existence for longer are less susceptible to component packets being deleted. | 06-03-2010 |
| 20100329118 | FLOW STATE AWARE MANAGEMENT OF QoS THROUGH DYNAMIC AGGREGATE BANDWIDTH ADJUSTMENTS - A packet network node and method of operating a packet network node are disclosed. Conventional packet network nodes react to congestion in the packet network by dropping packets in a manner which is perceived by users to be indiscriminate. In embodiments of the present invention, indiscriminate packet discards are prevented by causing packets to be discarded on lower priority flows and flow aggregates. A further action is taken to reduce the likelihood of packet discards. When an aggregate set of flows raises a congestion alarm action is taken to try to increase the capacity of the aggregate through taking capacity from pre-assigned donor aggregates. A donor aggregate may be carrying flows, for example flows classified as best effort. Another type of donor capacity is donor re-assignable unused capacity. Aggregates may have capacity added either up to a defined limit or, temporarily, exceeding any limit provided there is free capacity available, but removable back to the defined limit when other aggregates need increased capacity and are below their defined limits. | 12-30-2010 |
| 20110019551 | FLOW STATE AWARE MANAGEMENT OF QoS WITH A DISTRIBUTED CLASSIFIER - Packet network node and method of operating packet network node. Conventional packet network nodes react to congestion in packet network by dropping packets in a manner which is perceived by users to be indiscriminate. In the described system, indiscriminate packet discards are prevented by causing packets to be discarded on lower priority flows and flow aggregates. Further action is taken to reduce the likelihood of packet discards through: (1) classification of flows that are not observable at the point in the network where flow-based packet discards are deployed, but are consuming bandwidth and signaling classification information to flow-based packet discard function or a flow-based monitoring function or network management function; (2) classification of flows making use of extended monitoring functions that are not co-located with a flow-based packet discard function, where extended monitoring functions may perform monitoring of a flow or a group of flows over a period of time. | 01-27-2011 |
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| 20090117126 | Neutralising Antibody Molecules Having Specificity for Human IL-17 - The invention relates to an antibody molecule having specificity for antigenic determinants of IL-17, therapeutic uses of the antibody molecule and methods for producing said antibody molecule. | 05-07-2009 |
| 20090326203 | Framework Selection - The present invention relates to improved methods for the selection of appropriate human acceptor framework regions for non-human (donor) antibodies and methods for obtaining humanized antibodies of high affinity using such acceptor frameworks. | 12-31-2009 |
| 20100086538 | Antibody Molecules Which Bind to Human IL-17 - The invention relates to antibody molecules having specificity for antigenic determinants of IL-17, therapeutic uses of the antibody molecules and methods for producing said antibody molecules. | 04-08-2010 |
| 20100104573 | BINDING PROTEINS, INCLUDING ANTIBODIES, ANTIBODY DERIVATIVES AND ANTIBODY FRAGMENTS, THAT SPECIFICALLY BIND CD154 AND USES THEREOF - This invention provides binding proteins, including antibodies, antibody derivatives and antibody fragments, that specifically bind a CD154 (CD40L) protein. This invention also provides a chimeric, humanized or fully human antibody, antibody derivative or antibody fragment that specifically binds to an epitope to which a humanized Fab fragment comprising a variable heavy chain sequence according to SEQ ID NO: 1 and comprising a variable light chain sequence according to SEQ ID NO: 2 specifically binds. CD154 binding proteins of this invention may elicit reduced effector function relative to a second anti-CD154 antibody. CD154 binding proteins of this invention are useful in diagnostic and therapeutic methods, such as in the treatment and prevention of diseases including those that involve undesirable immune responses that are mediated by CD154-CD40 interactions. | 04-29-2010 |
| 20100266609 | Antibody Molecules Which Bind IL-17A and IL-17F - The invention relates to antibody molecules having specificity for antigenic determinants of both IL-17A and IL-17F, therapeutic uses of the antibody molecules and methods for producing said antibody molecules. | 10-21-2010 |
| 20110184152 | Biological Products - A multivalent antibody fusion protein which comprises an immunoglobulin moiety, for example a Fab or Fab′ fragment, with a first specificity for an antigen of interest, and further comprises two single domain antibodies (dAb) with specificity for a second antigen of interest, wherein the two single domain antibodies are linked by a disulfide bond. There is also provided particular dual specificity antibody fusion proteins comprising a Fab or Fab′ fragment and one or more single domain antibodies which may be stabilised by a disulfide bond therebetween. | 07-28-2011 |
