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Aburano
Ichiharu Aburano, Hitachi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090276557 | BUS SYSTEM FOR USE WITH INFORMATION PROCESSING APPARATUS - A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on t | 11-05-2009 |
| 20100306438 | BUS SYSTEM FOR USE WITH INFORMATION PROCESSING APPARATUS - A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal. | 12-02-2010 |
Ichiharu Aburano, Hitachi-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20080244124 | Bus system for use with information processing apparatus - A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on t | 10-02-2008 |
Maru Aburano, Tatebayashi-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20110011291 | METHOD FOR MAKING LITHOGRAPHIC PRINTING ORIGINAL PLATE - An object of the present invention is to provide a method for plate-making of a lithographic printing original plate having excellent restart toning recovery properties, and particularly an infrared-sensitive positive working lithographic printing original plate. | 01-20-2011 |
Maru Aburano, Gunma-Ken JP
| Patent application number | Description | Published |
|---|---|---|
| 20090208869 | LITHOGRAPHIC-PRINTING PLATE PRECURSOR AND IMAGE FORMING METHOD USING THE SAME - To provide an infrared-sensitive or heat-sensitive lithographic printing plate precursor which has high printing durability and wide development latitude, and also has good developing properties capable of preventing the formation of deposits during the development. In an infrared-sensitive or heat-sensitive lithographic printing plate precursor, comprising a substrate, a first image recording layer formed on the substrate, and a second image recording layer formed on the first image recording layer, the first image recording layer contains a resin which is soluble or dispersible in an aqueous alkali solution, and the second image recording layer contains a polyurethane which has a substituent having an acidic hydrogen atom. | 08-20-2009 |
| 20100236436 | POSITIVE LITHOGRAPHIC PRINTING PLATE PRECURSOR AND METHOD FOR PRODUCING THE SAME - An object of the present invention is to provide a CTP positive working lithographic printing original plate capable of developing using a negative developing solution. | 09-23-2010 |
Tamio Aburano, Hokkaido JP
| Patent application number | Description | Published |
|---|---|---|
| 20110002521 | CEREBRAL BLOOD FLOW QUANTIFICATION DEVICE, CEREBRAL BLOOD FLOW QUANTIFICATION METHOD AND PROGRAM - A cerebral blood flow rate quantification device includes: a nuclear medicine image acquisition unit for acquiring a nuclear medicine image of the head of a subject administered with a radiopharmaceutical; a count calculation unit for calculating the number of counts obtained from a unit region; a cerebral blood flow rate calculation unit for calculating the value of a cerebral blood flow rate that makes the value of a function, which expresses the concentration of the radiopharmaceutical in brain tissue; and a cerebral blood flow map generation unit for generating a map showing cerebral blood flow based on the cerebral blood flow rate in each unit region. Consequently, the cerebral blood flow rate can be accurately quantified even at a relatively early stage after administration of a radiopharmaceutical. | 01-06-2011 |