Abhyankar, US
Abhijit M. Abhyankar, Sunnyvale, CA US
Patent application number | Description | Published |
---|---|---|
20090129178 | Integrated Circuit Memory Device Having Delayed Write Timing Based on Read Response Time - An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core. | 05-21-2009 |
20100058100 | DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS - A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function. | 03-04-2010 |
20100332719 | Memory Write Signaling and Methods Thereof - In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources. | 12-30-2010 |
20120005437 | Memory Controller for Controlling Write Signaling - A memory controller has an interface to convey, over a first set of interconnect resources: a first command that specifies activation of a row of memory cells, a second command that specifies a write operation directed to the row of memory cells, a bit that specifies whether precharging will occur in connection with the write operation, a code that specifies whether data mask information will be issued in connection with the write operation, and if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation. The memory controller interface further conveys, over a second set of interconnect resources, separate from the first set of interconnect resource, the write data. | 01-05-2012 |
20120173810 | Method and Apparatus for Indicating Mask Information - An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data. | 07-05-2012 |
20120173811 | Method and Apparatus for Delaying Write Operations - An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit to the DRAM a first code to indicate that first data is to be written to the DRAM. The first code is to be sampled by the DRAM and held by the DRAM for a first period of time before it is issued inside the DRAM. The interface is further to transmit the first data that is to be sampled by the DRAM after a second period of time has elapsed from when the first code is sampled by the DRAM. The interface is further to transmit a second code, different from the first code, to indicate that second data is to be read from the DRAM. The second code is to be sampled by the DRAM on one or more edges of the external clock signal. | 07-05-2012 |
20140185725 | DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS - A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function. | 07-03-2014 |
Ashwin Abhyankar, Simi Valley, CA US
Patent application number | Description | Published |
---|---|---|
20090099957 | METHOD OF TRANSFERRING MORTGAGES AND LOANS - Embodiments of the present invention relate loan agreements, in which a second security may be substituted for an initial security. The substitution may be contingent upon specific characteristics, related to, for example, the second security, the outstanding loan, the initial loan, or the lender. | 04-16-2009 |
Atul Abhyankar, Columbus, IN US
Patent application number | Description | Published |
---|---|---|
20130199160 | AFTERTREATMENT SYSTEM FOR AN ENGINE - A system includes an internal combustion engine. An aftertreatment system is coupled to the internal combustion engine to receive an exhaust gas stream. The aftertreatment system comprises one or modules. Each module includes one or more emission reducing devices to reduce undesirable constituents in the exhaust gas stream from the internal combustion engine. | 08-08-2013 |
Rahul Abhyankar, Santa Clara, CA US
Patent application number | Description | Published |
---|---|---|
20090288168 | MANAGEMENT CAPABILITIES FOR REAL-TIME MESSAGING NETWORKS - Techniques for managing instant message (IM) communications are provided. In various embodiments, IM communications in a plurality of network implementations are managed using one or more policies. A policy in the one or more policies includes an action applicable for an IM communication. Once an IM communications is received from an IM client, a policy that is applicable for that IM communication is determined. After determining an applicable policy, an action associated with the policy for the instant message communication is performed. Examples of actions that may be taken include recording the IM communication, modifying the IM communication, blocking the IM communication, forwarding the IM communication, and the like. | 11-19-2009 |
Rohini Abhyankar, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20110187425 | PHASE-LOCKED LOOP SYSTEMS USING ADAPTIVE LOW-PASS FILTERS IN SWITCHED BANDWIDTH FEEDBACK LOOPS - Methods and systems directed toward a PLL circuit ( | 08-04-2011 |
Sachin Abhyankar, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20100138811 | Dynamic Performance Profiling - A dynamic performance profiler is operable to receive, in substantially real-time, raw performance data from a testing platform. A software-based image is executing on a target hardware platform (e.g., either simulated or actual) on the testing platform, and the testing platform monitors such execution to generate corresponding raw performance data, which is communicated, in substantially real-time, as it is generated during execution of the software-based image to a dynamic profiler. The dynamic profiler may be configured to archive select portions of the received raw performance data to data storage. As the raw performance data is received, the dynamic profiler analyzes the data to determine whether the performance of the software-based image on the target hardware platform violates a predefined performance constraint. When the performance constraint is violated, the dynamic profiler archives a portion of the received raw performance. | 06-03-2010 |
Sachin A. Abhyankar, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20120263125 | Arbitrating Resource Acquisition For Applications of a Multi-Processor Mobile Communications Device - In an embodiment, a multi-processor mobile communications device includes a first processor system executing a concurrency manager server application (CMSA) and a second processor system executing a concurrency manager client application (CMCA). The CMSA determines priority levels related to access to resources for a first set of applications that are configured for execution on the first processor system and a second set of applications that are configured for execution on the second processor system. The CMSA notifies the CMCA of the determined priorities. The CMSA and the CMCA each then selectively grant or reject access to the resources for the first and second sets of applications, respectively, based on the determined priorities levels. In another embodiment, if the CMSA or CMCA rejects an application's request to access resources, the CMSA or CMCA can determine availability of alternative resources by which the requesting application can achieve its goal. | 10-18-2012 |
Vinay Abhyankar, Keller, TX US
Patent application number | Description | Published |
---|---|---|
20140178252 | MICROFLUIDIC DEVICES AND METHODS INCLUDING POROUS POLYMER MONOLITHS - Microfluidic devices and methods including porous polymer monoliths are described. Polymerization techniques may be used to generate porous polymer monoliths having pores defined by a liquid component of a fluid mixture. The fluid mixture may contain iniferters and the resulting porous polymer monolith may include surfaces terminated with iniferter species. Capture molecules may then be grafted to the monolith pores. | 06-26-2014 |
Vinay V. Abhyankar, Philadelphia, PA US
Patent application number | Description | Published |
---|---|---|
20090098659 | METHOD OF PATTERNING PARTICLES ON AN ARBITRARY SUBSTRATE AND CONDUCTING A MICROFLUIDIC INVASION ASSAY - A method is provided for sequentially patterning different particle populations on spatially defined regions in microfluidic device. The microfluidic device has a channel and a plurality of access ports therein. Each access port has an input and an output communicating with the channel. The method includes the step of depositing a drop of a first suspension on the input of a first access port. The first suspension includes a plurality of particles. A drop of a second suspension is deposited on the input of a second access port. The second suspension includes a plurality of particles. The particles in the first and second suspensions settle onto and are patterned along corresponding spaced portions of the channel. | 04-16-2009 |
Vinay V. Abhyankar, Dublin, CA US
Patent application number | Description | Published |
---|---|---|
20100025243 | METHOD FOR ROBUST CONTROL OVER A SOLUABLE FACTOR MICROENVIRONMENT WITHIN A THREE-DIMENSIONAL GEL MATRIX - A method is provided of generating a gradient within gel matrix received in a channel of a microfluidic device. A source reservoir in communication with the input of the channel is filled with a first fluid. A sink reservoir in communication with the output of the channel is filled with a second fluid. A soluble factor is deposited in the source reservoir such that the soluble factor diffuses into the channel and forms the gradient. The soluble factor in source reservoir is replenished to maintain the gradient in a generally pseudo-steady state and the second fluid in the sink reservoir is replaced. | 02-04-2010 |
Vishwas G. Abhyankar, Pittsford, NY US
Patent application number | Description | Published |
---|---|---|
20110028825 | SYSTEMS AND METHODS FOR EFFICIENT IMAGING - A system and methods for more efficient review, processing, analysis and diagnoses of medical imaging data is disclosed. The system and methods include automatically segmenting and labeling imaging data by anatomical feature or structure. Additional tools that can improve the efficiency of health care providers are also disclosed. | 02-03-2011 |