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Abadeer
Wagdi W. Abadeer, Essex Junction, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20100289079 | HIGH-VOLTAGE SOI MOS DEVICE STRUCTURE AND METHOD OF FABRICATION - Structures and methods for integrating a thick oxide high-voltage metal-oxide-semiconductor (MOS) device into a thin oxide silicon-on-insulator (SOI). A method of forming a semiconductor structure includes forming first source and drain regions of a first device below a buried oxide layer of a silicon-on-insulator (SOI) wafer, forming a gate of the first device in a layer of semiconductor material above the buried oxide layer; and forming second source and drain regions of a second device in the layer of semiconductor material above the buried oxide layer. | 11-18-2010 |
| 20110095366 | FORMING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER - Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region. | 04-28-2011 |
Wagdi W. Abadeer, Jerico, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20090147568 | Memory Elements and Methods of Using the Same - In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided. | 06-11-2009 |
Wagdi William Abadeer, Jericho, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20090058703 | DIGITAL-TO-ANALOG CONVERTER USING DUAL-GATE TRANSISTORS - A digital to analog converter. The digital to analog converter including a current mirror comprising N stages, each stage comprising 2 | 03-05-2009 |
| 20090058704 | DESIGN STRUCTURE FOR A DIGITAL-TO-ANALOG CONVERTER USING DUAL-GATE TRANSISTORS - A design structure embodied in a machine readable medium, the design structure including a current mirror including N stages, each stage comprising 2 | 03-05-2009 |
| 20090113357 | MONITORING IONIZING RADIATION IN SILICON-ON INSULATOR INTEGRATED CIRCUITS - A method, device and system for monitoring ionizing radiation, and design structures for ionizing radiation monitoring devices. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit. | 04-30-2009 |