Patent application number | Description | Published |
20110050343 | BIAS CIRCUIT AND AMPLIFIER PROVIDING CONSTANT OUTPUT CURRENT FOR A RANGE OF COMMON MODE INPUTS - Bias circuits, amplifiers and methods are provided, such as those for providing bias signals over a range of common mode inputs for an amplifier to output a constant current. One example of a bias circuit is configured to generate a bias signal having a voltage magnitude according to a reference signal. The reference signal is indicative of a common mode input level of an input signal of the amplifier circuit and the bias circuit is further configured to adjust the bias signal over a range of common mode input levels. An amplifier receiving the bias signal is configured to generate an output signal in response to an input signal and drive an output current based on the voltage magnitude of the bias signal provided by the bias circuit. | 03-03-2011 |
20110204981 | BIAS CIRCUIT AND AMPLIFIER PROVIDING CONSTANT OUTPUT CURRENT FOR A RANGE OF COMMON MODE INPUTS - Bias circuits, amplifiers and methods are provided, such as those for providing bias signals over a range of common mode inputs for an amplifier to output a constant current. One example of a bias circuit is configured to generate a bias signal having a voltage magnitude according to a reference signal. The reference signal is indicative of a common mode input level of an input signal of the amplifier circuit and the bias circuit is further configured to adjust the bias signal over a range of common mode input levels. An amplifier receiving the bias signal is configured to generate an output signal in response to an input signal and drive an output current based on the voltage magnitude of the bias signal provided by the bias circuit. | 08-25-2011 |
20110248752 | CLOCK SIGNAL GENERATORS HAVING A REDUCED POWER FEEDBACK CLOCK PATH AND METHODS FOR GENERATING CLOCKS - Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by a adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal. | 10-13-2011 |
20120001663 | MIXED-MODE INPUT BUFFER - An input buffer with a reduced sensitivity to an externally generated reference voltage includes: a first input coupled between a first load and ground, the first input being an externally generated reference voltage; a second input coupled between a second load and ground, for generating an output; and a third input coupled in parallel to the first input, the third input being an internally generated reference voltage. The output switches between high and low or vice versa when the second input exceeds a switching point which is an average of the first input and the third input according to the relative size of the first input and the third input. | 01-05-2012 |
20120268171 | CLOCK SIGNAL GENERATORS HAVING A REDUCED POWER FEEDBACK CLOCK PATH AND METHODS FOR GENERATING CLOCKS - Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by a adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal. | 10-25-2012 |
20120293221 | DELAY LOCK LOOP AND DELAY LOCK METHOD - A delay lock loop comprising: a first delay loop, for delaying an input signal to generate a first output signal; a second delay loop, for frequency-dividing and delaying the input signal to generate a second output signal, wherein a frequency of the first output signal is higher than which of the second output signal; a phase detector, selectively detecting phases of the input signal, and one of the first delayed output signal and the second delayed output signal, to generate a phase detecting result; and a delay control circuit, for generating a first and a second delay control signal according to the phase detecting result, wherein the first and the second delay control signals are respectively transmitted to the first delay loop and the second delay loop, to control delay amounts of the first delay loop and the second delay loop. | 11-22-2012 |
20130037951 | SEMICONDUCTOR PACKAGE STRUCTURE WITH LOW INDUCTANCE - A semiconductor package structure includes: a substrate comprising a plurality of power supply balls on a first surface of the substrate, a first metal conductor on a second surface of the substrate and at least one via coupling a power supply ball to the first metal conductor of the substrate; a die, comprising a plurality of bond pads on a first surface of the die, a first metal conductor on a second surface of the die and at least one via coupling a bond pad to the first metal conductor of the die; and a plurality of first wire bonds for coupling the first metal conductor of the substrate to the first metal conductor of the die. | 02-14-2013 |
20130343134 | CLOCK SIGNAL GENERATORS HAVING A REDUCED POWER FEEDBACK CLOCK PATH AND METHODS FOR GENERATING CLOCKS - Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by an adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal. | 12-26-2013 |