Patent application number | Description | Published |
20130336051 | MULTIBIT MEMORY WITH READ VOLTAGE QUALIFICATION AT STARTUP - Systems in which multi-bit PCM is used, including memory systems, as well as methods for operating such systems. A test of multi-bit PCM memory elements with known states can be used to determine whether immediately available voltage levels can reliably read multi-bit PCM. This can be used to accelerate availability of memory states residing in multi-bit PCM with respect to, for example, redundancy address storage, other startup state information, and parameters for which nonvolatile storage is useful. | 12-19-2013 |
20130336052 | Processors and Systems With Read Voltage Qualification of Multibit Phase-Change Memory - Systems in which multi-bit PCM is used, including memory systems, as well as methods for operating such systems. A test of multi-bit PCM memory elements with known states can be used to determine whether immediately available voltage levels can reliably read multi-bit PCM. This can be used to accelerate availability of memory states residing in multi-bit PCM with respect to, for example, redundancy address storage, other startup state information, and parameters for which nonvolatile storage is useful. | 12-19-2013 |
20140063927 | Cell-Generated Reference in Phase Change Memory - Phase-change memory arrays, subarrays and chips, and systems and devices in which phase change memory is used, in which two reference columns are added on to hold complementary states for each wordline of data. The outputs from the cells in the two reference columns are combined (e.g. as a plain or weighted average) to provide a reference value for read discrimination of cell states in the other columns. This provides reference values which closely track resistance changes in corresponding ones of said words resulting from, e.g., drift and other time- and phase change material-dependent factors. One of the columns of reference cells can hold a checksum. | 03-06-2014 |
20140063928 | Processors and Systems with Cell-Generated-Reference in Phase-Change Memory - Phase-change memory arrays, subarrays and chips, and systems and devices in which phase change memory is used, in which two reference columns are added on to hold complementary states for each wordline of data. The outputs from the cells in the two reference columns are combined (e.g. as a plain or weighted average) to provide a reference value for read discrimination of cell states in the other columns. This provides reference values which closely track resistance changes in corresponding ones of said words resulting from, e.g., drift and other time- and phase change material-dependent factors. One of the columns of reference cells can hold a checksum. | 03-06-2014 |
20140063929 | Complement Reference in Phase Change Memory - Phase change memory arrays, subarrays, modules, and chips, as well as systems and devices in which phase change memory is used, wherein a reference corresponding to a pair of adjacent logical states (e.g., 0 and 1) can be generated by averaging outputs from a designated data-storing cell and a designated reference cell storing the logical complement to the logical state stored by the data-storing cell. By writing designated cells contemporaneously with words of cells that are configured to be written together, resulting references can closely track resistance changes in said words resulting from, e.g., drift and other time- and phase change material-dependent factors. | 03-06-2014 |
20140063930 | Processors and Systems with Drift-Tolerant Phase-Change Memory Data Storage - Phase change memory arrays, subarrays, modules, and chips, as well as systems and devices in which phase change memory is used, wherein a reference corresponding to a pair of adjacent logical states (e.g., 0 and 1) can be generated by averaging outputs from a designated data-storing cell and a designated reference cell storing the logical complement to the logical state stored by the data-storing cell. By writing designated cells contemporaneously with words of cells that are configured to be written together, resulting references can closely track resistance changes in said words resulting from, e.g., drift and other time- and phase change material-dependent factors. | 03-06-2014 |
20140063931 | MULTIBIT PHASE-CHANGE MEMORY WITH MULTIPLE REFERENCE COLUMNS - Systems and devices in which multi-bit phase change memory is used, including memory systems and memories, as well as methods for operating such systems and devices. According to the present invention, a reference corresponding to a pair of adjacent logical states (e.g., 0 and 1) can be generated by averaging outputs from multiple phase change memory reference cells designated to store said adjacent logical states. By writing reference cells contemporaneously with words of cells that are configured to be written together, resulting references can closely track output changes in corresponding ones of said words resulting from, e.g., drift and other time- and phase change material-dependent factors. Ordering of states within said reference cells can be used to encode information such as checksums of corresponding words. | 03-06-2014 |
20140071746 | Multilevel Differential Sensing in Phase Change Memory - Methods and systems for multi-bit phase change memories. Using differential sensing for memory reads provides advantages including improved temperature and drift resilience, improved state discrimination and increased storage density. | 03-13-2014 |
20140071747 | Processors and Systems with Multicell Multibit Phase-Change Memory - Methods and systems for processors and processing systems having multi-bit phase change memories. Using differential sensing for memory reads provides advantages including improved temperature and drift resilience, improved state discrimination and increased storage density. | 03-13-2014 |
20140146601 | PROCESSORS AND SYSTEMS WITH MULTIPLE REFERENCE COLUMNS IN MULTIBIT PHASE-CHANGE MEMORY - Systems and devices in which multi-bit phase change memory is used, including memory systems and memories, as well as methods for operating such systems and devices. According to the present invention, a reference corresponding to a pair of adjacent logical states (e.g., 0 and 1) can be generated by averaging outputs from multiple phase change memory reference cells designated to store said adjacent logical states. By writing reference cells contemporaneously with words of cells that are configured to be written together, resulting references can closely track output changes in corresponding ones of said words resulting from, e.g., drift and other time- and phase change material-dependent factors. Ordering of states within said reference cells can be used to encode information such as checksums of corresponding words. | 05-29-2014 |
20140204665 | Multilevel Differential Sensing in Phase Change Memory - Methods and systems for multi-bit phase change memories. Using differential sensing for memory reads provides advantages including improved temperature and drift resilience, improved state discrimination and increased storage density. | 07-24-2014 |
20140321200 | PHASE CHANGE MEMORY WITH FLEXIBLE TIME-BASED CELL DECODING - Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is determined using differentiated timings of read outputs changing state, rather than differentiated values of read outputs. In some single-bit single-ended sensing embodiments, a reference, with resistance between the resistances corresponding to a pair of adjacent logical states, is stored in multiple reference cells; a “vote” unit emits a clock signal when a majority of the reference cell read outputs transition at the vote unit. Timing units produce different binary outputs depending on whether a data read output or the clock signal changes state first at the timing unit. Time-based decoding provides advantages including improved temperature and drift resilience, improved state discrimination, improved reliability of multibit PCM, and fast and reliable sensing. | 10-30-2014 |
20150078076 | PHASE CHANGE MEMORY WITH FLEXIBLE TIME-BASED CELL DECODING - Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is determined using differentiated timings of read outputs changing state, rather than differentiated values of read outputs. In some single-bit single-ended sensing embodiments, a reference, with resistance between the resistances corresponding to a pair of adjacent logical states, is stored in multiple reference cells; a “vote” unit emits a clock signal when a majority of the reference cell read outputs transition at the vote unit. Timing units produce different binary outputs depending on whether a data read output or the clock signal changes state first at the timing unit. Time-based decoding provides advantages including improved temperature and drift resilience, improved state discrimination, improved reliability of multibit PCM, and fast and reliable sensing. | 03-19-2015 |