Patent application number | Description | Published |
20130301204 | PORTABLE TERMINAL WITH DETACHABLE PROTECTION COVER - A portable terminal is provided. The portable terminal includes a mounting member configured to be capable of being attached to/detached from a housing of the portable terminal, a connection member configured to extend from the mounting member and to selectively enclose at least a part of the housing, and a cover element connected to an end of the connection member to open/close a display device installed on the front surface of the housing. The portable terminal provided with the protection cover has an advantage in that the increase of the thickness of the terminal can be minimized because the protection cover may be disposed on a side surface or an edge of the rear surface of the housing by the mounting member. | 11-14-2013 |
20140198464 | FRAME STRUCTURE FOR PREVENTING DEFORMATION, AND ELECTRONIC DEVICE INCLUDING THE SAME - An electronic device is provided. The electronic device includes a main frame, an opening portion formed in the main frame, a recess portion formed along a frame of the opening portion lower than a surface of the main frame, and a plate having frames seated on the recess portion, wherein at least one of the frames of the plate is formed of a curved portion that is curved inwardly. Accordingly, it is possible to absorb an external impact and prevent deformation just by a simple structure change of the plate. | 07-17-2014 |
20150024811 | FIBER-REINFORCED PLASTIC MATERIAL AND ELECTRONIC DEVICE INCLUDING THE SAME - A fiber-reinforced plastic material is provided. The fiber-reinforced plastic material is woven with a plurality of yarns and a material property of at least a portion of the fiber-reinforced plastic material is different from another portion of the fiber-reinforced plastic material according to an arrangement direction or a weave pattern of the yarns or a material of the yarns. | 01-22-2015 |
20150065209 | COVER MEMBER AND METHOD FOR MANUFACTURING THE SAME - A cover member and a method for manufacturing the same are provided. The cover member includes a case on at least a portion of which a material pattern is formed and a color layer formed on the material pattern provided on the case, in which a portion of the color layer is at least partially marked different from the material pattern. | 03-05-2015 |
20150261946 | APPARATUS AND METHOD FOR AUTHENTICATING USER - An apparatus and method for authenticating a user in an electronic device are provided. The method for controlling, by an electronic device, a wearable electronic device to authenticate a user includes receiving biometric information of the user from the wearable electronic device, determining whether the user has been registered in the wearable electronic device, based on the biometric information and stored authentication information, and controlling the wearable electronic device to authenticate the user according to a result of the determination. | 09-17-2015 |
Patent application number | Description | Published |
20100138595 | SEMICONDUCTOR DEVICE COMPRISING FLASH MEMORY AND ADDRESS MAPPING METHOD - A semiconductor device with flash memory includes; a log type determining unit configured to select log type from among a plurality of log types with respect to a log block storing program data requested to be programmed in the flash memory and generate a control signal indicating information indicating the selected log type, and a plurality of log units configured to store program data in the log block having a corresponding log type in response to the control signal, wherein the log type determining unit converts a first type log block formed by a first log type and included in a first type log unit from among the plurality of log units into second type log block formed by a second log type and converts the log block included in a second type log unit from among the plurality of log units into the first type log blocks, the first loge type being different from the second log type. | 06-03-2010 |
20110199822 | METHOD AND APPARATUS FOR CONTROLLING PAGE BUFFER OF NON-VOLATILE MEMORY DEVICE - A method of managing a page buffer of a non-volatile memory device comprises programming least significant bit (LSB) page data from an LSB page buffer into a page of memory cells, and retaining the LSB page data in the LSB page buffer until most significant bit (MSB) page data corresponding to the LSB page data is programmed in the page. | 08-18-2011 |
20110202818 | NON-VOLATILE MEMORY DEVICE AND OPERATION METHOD USING THE SAME - The non-volatile memory system includes a non-volatile memory and a controller. The non-volatile memory includes a data region including a sector region for storing sector data, and an uncorrectable information region for storing uncorrectable sector information on the sector region. The controller includes an information generation unit for generating the uncorrectable sector information that indicates whether the sector region is assigned to an uncorrectable sector region, according to a command output from a host. | 08-18-2011 |
20120047317 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF THROTTLING PERFORMANCE OF THE SAME - A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state; and a controller configured to control the non-volatile memory device. The controller calculates a new performance level, compares the calculated performance level with a predetermined reference, and determines the calculated performance level as an updated performance level according to the comparison result. | 02-23-2012 |
20120047318 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF THROTTLING PERFORMANCE OF THE SAME - A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device; and a controller configured to receive a write command from a host and program write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device. | 02-23-2012 |
20120047319 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF THROTTLING PERFORMANCE OF THE SAME - A semiconductor storage device (SSD) and a method of throttling performance of the SSD. The method can include gathering at least two workload data items related with a workload of the semiconductor storage device, estimating the workload using the at least two workload data items, and throttling the performance of the semiconductor storage device according to the estimated workload. Accordingly, a workload that the semiconductor storage device will undergo can be estimated. | 02-23-2012 |
20120066438 | NON-VOLATILE MEMORY DEVICE, OPERATION METHOD THEREOF, AND DEVICE HAVING THE SAME - A memory device includes a control module to determine first data blocks needing a garbage collection, to determine second data blocks needing memory refresh among the determined first data blocks, and to execute the garbage collection first on the second data blocks. | 03-15-2012 |
20150019801 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF THROTTLING PERFORMANCE OF THE SAME - A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device; and a controller configured to receive a write command from a host and program write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device. | 01-15-2015 |
20150032948 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF THROTTLING PERFORMANCE OF THE SAME - A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state; and a controller configured to control the non-volatile memory device. The controller calculates a new performance level, compares the calculated performance level with a predetermined reference, and determines the calculated performance level as an updated performance level according to the comparison result. | 01-29-2015 |
Patent application number | Description | Published |
20140253859 | LIQUID CRYSTAL DISPLAY - Provided is a liquid crystal display, including: a first substrate; a pixel electrode disposed on the first substrate; a second substrate facing the first substrate; a common electrode disposed on the second substrate; and a liquid crystal layer disposed between the first substrate and the second substrate, the liquid crystal layer including a plurality of liquid crystal molecules, in which the common electrode includes a cross-shaped cutout, the cross-shaped cutout overlapping the pixel electrode and dividing the pixel electrode into a plurality of subregions, and the pixel electrode includes a direction controller extend in a direction parallel to a line connecting an intersecting point of the cross-shaped cutout and a pixel corner edge opposing the intersecting point. | 09-11-2014 |
20150241749 | DISPLAY PANEL, DISPLAY APPARATUS INCLUDING THE SAME AND METHOD OF MANUFACTURING THE SAME - A display panel includes a base substrate, a gate line disposed under the base substrate and extending in a first direction, a data line disposed under the base substrate and extends in a second direction substantially perpendicular to the first direction, a thin film transistor disposed under the base substrate, and electrically connected to the gate line and the data line, a first electrode disposed under the base substrate and electrically connected to the thin film transistor, an image displaying portion disposed under the first electrode and overlapped with the first electrode, a protecting layer disposed under the image displaying portion, surrounding a lower surface of the image displaying portion and both sides of the image displaying portion in the second direction, and including a protrusion wall protruded in a direction opposite to the base substrate, and an upper polarizer disposed on the base substrate. | 08-27-2015 |
Patent application number | Description | Published |
20100297820 | Embedded Semiconductor Device Including Planarization Resistance Patterns and Method of Manufacturing the Same - An embedded semiconductor device which a logic region and the memory region are planarized with planarization resistance patterns and a method of manufacturing the same are disclosed. The embedded semiconductor device includes a substrate, gates formed on the substrate, source/drain regions formed on both sides of the gates in the substrate, a first interlayer dielectric (ILD) layer which covers the gates and the source/drain regions, first via plugs which vertically penetrate the first ILD layer and are selectively connected to the source/drain regions, capacitors and second via plugs selectively connected to the first via plugs, a second ILD layer that fills the space between the capacitors and the second via plugs, planarization resistance patterns formed on the second ILD layer, a third ILD layer formed on the second ILD layer and the planarization resistant patterns, and third via plugs which vertically penetrate the third ILD layer, and are selectively connected to a top electrode of the capacitors and the second via plugs. | 11-25-2010 |
20120315732 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND DEVICE USING SAME - In a method for fabricating a semiconductor device, a substrate may be provided that includes: a base, an active fin that projects from an upper surface of the base and is integrally formed with the base, and a buffer oxide film pattern formed on the active fin in contact with the active fin. A first dummy gate film may be formed on the substrate to cover the buffer oxide film pattern and the first dummy gate film may be smoothed to expose the buffer oxide film pattern. A second dummy gate film may be formed on the exposed buffer oxide film pattern and the first dummy gate film. | 12-13-2012 |
20130023119 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - In a method for fabricating a semiconductor device, a substrate is provided including an interlayer dielectric layer and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric layer through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric layer and the second hard mask pattern to fill the first trench. An upper portion of the second hard mask pattern is exposed by partially removing the filler material. The second hard mask pattern is removed, and remaining filler material is removed from the first trench. A wiring is formed by filling the first trench with a conductive material. | 01-24-2013 |
Patent application number | Description | Published |
20140231849 | SEMICONDUCTOR LIGHT-EMITTING DEVICES - Semiconductor light-emitting devices including a semiconductor region that includes a light-emitting structure; and an electrode layer including a first reflection metal layer that contacts a first portion of the semiconductor region and being configured to reflect light from the light-emitting structure and a second reflection metal layer that contacts a second portion of the semiconductor region and being configured to reflect light from the light-emitting structure, wherein the second reflection metal layer is spaced apart from the first reflection metal layer and at least partially covers the first reflection metal layer. | 08-21-2014 |
20140252390 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a semiconductor region having a light-emitting structure, an electrode layer formed on the semiconductor region, and a reflective protection structure extending exposing the upper surface of the electrode layer and covering the semiconductor region adjacent to the electrode layer. | 09-11-2014 |
20140312369 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device including a light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; a first electrode connected to the first conductivity type semiconductor layer; a second electrode including a contact layer connected to the second conductivity type semiconductor layer, a capping layer disposed on the contact layer, and a metal buffer layer disposed on the capping layer, the metal buffer layer encompasses an upper and lateral surface of the capping layer; a first insulating layer disposed on the light emitting structure such that the first and second electrodes are exposed; and a second insulating layer disposed on the first insulating layer such that at least a portion of the first electrode and at least a portion of the metal buffer layer are exposed. | 10-23-2014 |
20150091041 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND SEMICONDUCTOR LIGHT EMITTING APPARATUS INCLUDING THE SAME - A semiconductor light emitting device includes a substrate, a first structure, a second structure, first and second n-electrodes, and first and second p-electrodes. The first structure is disposed on the substrate and includes a first n-type semiconductor layer, a first active layer, and a first p-type semiconductor layer. The second structure is spaced apart from the first structure on the substrate and includes a second n-type semiconductor layer, a second active layer and a second p-type semiconductor layer. The first n-electrode and the first p-electrode are connected to the first n-type semiconductor layer and the first p-type semiconductor layer, respectively. The second n-electrode and the second p-electrode are connected to the second n-type semiconductor layer and the second p-type semiconductor layer, respectively. The second n-electrode is spaced apart from the second active layer to encompass the second active layer. | 04-02-2015 |
20150162376 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND SEMICONDUCTOR LIGHT EMITTING APPARATUS INCLUDING THE SAME - A semiconductor light emitting device includes a substrate; a light emitting structure and a Zener diode structure disposed to be spaced apart from each other on the substrate, and including a first semiconductor layer and a second semiconductor layer, respectively; and a common, integrally formed, electrode electrically connected to the first semiconductor layer of the light emitting structure and the second semiconductor layer of the Zener diode structure. At least a portion of the Zener diode formed by the Zener diode structure is disposed below the common electrode. | 06-11-2015 |
20150207051 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a stacked semiconductor structure including a first conductivity-type semiconductor layer having a top surface divided into a first region and a second region, and an active layer and a second conductivity-type semiconductor layer disposed sequentially on the second region of the first conductivity-type semiconductor layer. First and second contact electrodes are disposed in the first region of the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, respectively. A current spreading layer is disposed on the second contact electrode and comprises a first conductive layer having a first resistivity and a second conductive layer having a second resistivity smaller than the first resistivity alternately stacked. | 07-23-2015 |
Patent application number | Description | Published |
20110191649 | SOLID STATE DRIVE AND METHOD OF CONTROLLING AN ERROR THEREOF - The present general inventive concept relates to a solid state drive and a method of controlling an error thereof. A flash translation layer includes a parity managing module to correct errors. A block address of a storage medium including error data that can be recovered is managed through the parity managing module. Parity data of a block including error data is generated through the parity managing module. The generated parity data is managed through the parity managing module. The generated parity data can be stored in an assigned area of the storage medium. When data of a block managed by the parity managing module is not recovered by an error correction code unit, error data is recovered with reference to the generated parity data. | 08-04-2011 |
20120221771 | DATA STORAGE SYSTEM AND DATA MAPPING METHOD OF THE SAME - A data mapping method is performed by a memory controller in a data storage system configured to control a nonvolatile memory device having a plurality of channels, where each channel includes a plurality of nonvolatile memories. The data mapping method includes selecting channels of the plurality of channels to be active channels to which data input from a host are written in response to a request from the host, including nonvolatile memories corresponding to each of the active channels in a candidate zone list as active zones, and sequentially writing the data input from the host to the active zones included in the candidate zone list. | 08-30-2012 |
20130185483 | DATA STORAGE SYSTEM, MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes: first through m-th word lines arranged sequentially and first through m-th pages connected respectively to the first through m-th word lines; a redundant array of inexpensive disks (RAID) controller generating first RAID parity data from first through (m−1)-th data; and an access controller connected to the RAID controller and capable of accessing the nonvolatile memory device, wherein the access controller programs the first through (m−1)-th data to the first through (m−1)-th pages and programs the first RAID parity data to the m-th page. | 07-18-2013 |
20150135042 | MEMORY SYSTEM MONITORING DATA INTEGRITY AND RELATED METHOD OF OPERATION - A memory controller comprises at least one interface configured to receive a request, user data, and an address from an external source, a first data check engine configured to generate data check information based on the received address and the user data in response to the received request, and a second data check engine configured to check the integrity of the user data based on the generated data check information where the user data is transmitted to the nonvolatile memory. The memory controller is configured to transmit the user data received from the external source to an external destination where the integrity of the user data is verified according to a check result, and is further configured to transmit an interrupt signal to the external source and the external destination where the check result indicates that the user data comprises an error. | 05-14-2015 |
20150227313 | METHOD OF MAPPING ADDRESS IN STORAGE DEVICE, METHOD OF READING DATA FROM STORAGE DEVICES AND METHOD OF WRITING DATA INTO STORAGE DEVICES - In a method of mapping an address in a storage device, first address mapping information including a first physical address and a first logical address is registered in an address mapping table. The first physical address corresponds to a first storage area in the storage device. The first storage area includes a first type of memory. The first logical address corresponds to the first physical address. Second address mapping information including a second physical address and a second logical address is registered in the address mapping table. The second physical address corresponds to a second storage area in the storage device. The second storage area includes a second type of memory that is different from the first type of memory. The second logical address corresponds to the second physical address. | 08-13-2015 |
Patent application number | Description | Published |
20120225530 | METHODS OF FABRICATING A SEMICONDUCTOR MEMORY DEVICE - A method of fabricating a semiconductor memory device includes forming a hard mask pattern using a damascene method on a lower mold layer stacked on a substrate and etching the lower mold layer using the hard mask pattern as an etch mask to define a protrusion under the hard mask pattern. A support pattern is formed on a top surface of the etched lower mold layer, the top surface of the etched lower mold layer being located at a lower level than a top surface of the protrusion. A lower electrode supported by the support pattern is formed. | 09-06-2012 |
20120225554 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING BOWING PREVENTION FILM - A method of manufacturing a semiconductor device, the method including sequentially forming a lower material film, a middle material film, and an upper material film on a semiconductor substrate; and forming an opening that vertically penetrates the upper material film, the middle material film, and the lower material film by etching the upper material film, the middle material film, and the lower material film, wherein the middle material film and the upper material film are formed of material films having etch rates lower than an etch rate of the lower material film with respect to an etchant for etching the lower material film. | 09-06-2012 |
20130095663 | METHOD OF FORMING A SEMICONDUCTOR MEMORY DEVICE - A method of forming a semiconductor memory device includes forming an etch target layer on a substrate, forming a sacrificial layer having preliminary openings on the etch target layer, forming assistance spacers in the preliminary openings, respectively, removing the sacrificial layer, such that the assistance spacers remain on the etch target layer, forming first mask spacers covering inner sidewalls of the assistance spacers, respectively, the first mask spacers respectively defining first openings, forming a second mask spacer covering outer sidewalls of the assistance spacers, the second mask spacer defining second openings between the first openings, the first and second openings being adjacent to each other along a first direction, and etching the etch target layer exposed by the first openings and the second openings to form holes in the etch target layer. | 04-18-2013 |
20130260559 | METHODS FOR FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE - Methods of forming fine patterns are provided. The methods may include forming first hard mask patterns extending in a first direction on a lower layer, forming second hard mask patterns filling gap regions between the first hard mask patterns, forming first mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the first mask patterns as etch masks to form first openings, forming second mask patterns filling the first openings and extending in the second direction, and etching the second hard mask patterns using the second mask patterns as etch masks to form second openings spaced apart from the first openings in a diagonal direction with respect to the first direction. | 10-03-2013 |
20130260562 | METHODS FOR FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE - A method may include forming first hard mask patterns and second hard mask patterns extending in a first direction and repeatedly and alternately arranged on a lower layer, forming third mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the third mask patterns to form first openings, forming filling patterns filling the first openings and gap regions between the third mask patterns, forming spacers on both sidewalls of each of the filling patterns, after removing the third mask patterns, and etching the second hard mask patterns using the filling patterns and the spacers to form second openings. | 10-03-2013 |
Patent application number | Description | Published |
20130173983 | GENERATION OF PROGRAM DATA FOR NONVOLATILE MEMORY - A method generating program data to be stored in a nonvolatile memory device comprises randomizing the program data, and processing the randomized program data to reduce a frequency of at least one data state among the randomized program data. | 07-04-2013 |
20130179659 | DATA STORAGE DEVICE WITH SELECTIVE DATA COMPRESSION - A memory controller comprises a host interface block comprising a compression ratio calculator configured to determine whether a compression ratio of input data exceeds a predetermined compression ratio, and a compression block configured to compress the input data as a consequence of the host compression ratio calculator determining that the compression ratio exceeds the predetermined compression ratio. | 07-11-2013 |
20130326314 | NONVOLATILE MEMORY DEVICE AND RELATED READ METHOD USING HARD AND SOFT DECISION DECODING - A storage device comprises a nonvolatile memory device comprising a plurality of memory cells, and an error correction circuit configured to receive primary data and secondary data from the nonvolatile memory device and to perform a hard decision decoding operation on the primary data and further configured to perform a soft decision decoding operation on the primary data based on the secondary data. The primary data is read from the plurality of memory cells in a hard decision read operation and the secondary data is read from memory cells programmed to a specific state from among the primary data. | 12-05-2013 |
20140037086 | MEMORY SYSTEM GENERATING RANDOM NUMBER AND METHOD GENERATING RANDOM NUMBER - In a memory of non-volatile memory cells, a random number is generated by programming non-volatile memory cells, reading the programmed non-volatile memory cells using a random number read voltage selected in accordance with a characteristic of the non-volatile memory cells to generate random read data, and generating the random number from the random read data. | 02-06-2014 |
20150261606 | DEVICE AND METHOD FOR PROCESSING DATA USING LOGICAL INFORMATION AND PHYSICAL INFORMATION - A method of operating a data storage device according to an exemplary embodiment of the present inventive concepts includes generating at least one pseudo noise (PN) sequence using logical information and physical information for the data storage device, and converting first data into second data using the at least one PN sequence. Generating the at least one PN sequence includes generating a random seed based on the logical information and the physical information, and generating the at least one PN sequence using the random seed. The logical information may be a logical page address for the data storage device, and the physical information may be a physical page address for the data storage device. | 09-17-2015 |
Patent application number | Description | Published |
20150022122 | BACKLIGHT UNIT INCLUDING A POWER TRANSMITTING WIRE - The present invention relates to a backlight unit. The backlight unit includes a light source unit, a power supply unit, and a power transmitting wire. The light source includes at least one light source. The power supply circuit is configured to supply a power voltage to the light source unit. The power transmitting wire is configured to transmit the power voltage. The power transmitting wire includes at least two circuit patterns. | 01-22-2015 |
20150084847 | DC-DC CONVERTER AND DISPLAY APPARATUS HAVING THE SAME - A direct-current-to-direct-current (“DC-DC”) converter includes an inductor to which an input voltage is applied, a diode connected to the inductor, a switching element connected between the inductor and the diode, a capacitor group disposed adjacent to the diode and comprising one or more capacitors, and an output voltage pattern connected to the diode and the capacitor group and which outputs an output voltage, where the capacitor group covers a first side of the output voltage pattern and a second side of the output voltage pattern opposite to the first side of the output voltage pattern. | 03-26-2015 |
20150260774 | NOISE TEST APPARATUS AND METHOD FOR TESTING A DISPLAY PANEL USING THE SAME - A noise test apparatus includes a ground plate, a base plate including a ground plate, the ground plate being configured to support a display panel. A first antenna configured to receive electromagnetic waves irradiated by the display panel and disposed on the base plate adjacent to a first side of the ground plate. A second antenna configured to receive the electromagnetic waves irradiated by the display panel and disposed on the base plate adjacent to a second side of the ground plate, the second side extending substantially perpendicular to the first side. | 09-17-2015 |
Patent application number | Description | Published |
20120171602 | TONER FOR DEVELOPING ELECTROSTATIC CHARGE IMAGE, AND APPARATUS AND METHOD FOR FORMING IMAGE USING THE SAME - Disclosed is a toner for developing an electrostatic charge image, including a toner particle coated with a combination of sol-gel silica particles, hydrophobically surface-treated fumed silica particles, and hydrophobically surface-treated titanium dioxide particles. | 07-05-2012 |
20130236824 | TONER TO DEVELOP ELECTROSTATIC LATENT IMAGES - A toner to develop electrostatic latent images, which has surface characteristics that may simultaneously improve charge uniformity, charge stability, transferability, and cleaning ability. The toner to develop electrostatic latent images may include core particles comprising a binder resin, a colorant, and a releasing agent; and an external additive including silica particles and titanium dioxide particles, wherein the external additive is attached to external surfaces of the core particles, wherein an iron intensity [Fe], a silicon intensity [Si], and a titanium intensity [Ti] that are measured by X-ray fluorescence (XRF) satisfy both conditions, 0.004≦[Si]/[Fe]≦0.009 and 0.8≦[Ti]/[Fe]≦2. | 09-12-2013 |
20140234766 | TONER TO DEVELOP ELECTROSTATIC LATENT IMAGES | 08-21-2014 |
20150118611 | TONER TO DEVELOP ELECTROSTATIC LATENT IMAGES - A toner to develop electrostatic latent images which uses an appropriate combination of a high molecular weight binder resin and a low molecular weight binder resin, an appropriate amount of a releasing agent, and a combination of silica particles and iron oxide particles as external additives, and thus has the following effects: the toner may reduce a generation amount of ultra-fine particles (UFPs) and have enhanced fluidity, charging uniformity, charging stability, transfer efficiency, fixability, durability and a cleaning ability. | 04-30-2015 |
Patent application number | Description | Published |
20100271327 | DISPLAY PANEL, DISPLAY APPARATUS HAVING THE SAME AND METHOD OF DRIVING THE DISPLAY APPARATUS - In a display panel, a display apparatus having the display panel, and a method of driving the display apparatus, a conductive spacer is interposed between an array substrate and an opposite substrate, and the conductive spacer electrically connects a pixel electrode and a common electrode when a touch event occurs for one or more embodiments. When a common voltage is applied to the pixel electrode by the touch event, an electric potential of a data line is lowered by the common voltage through a turned-on switching device. A signal reader periodically reads out the voltage of the data line and senses the touch event using the read-out voltage to detect a touch position at which the touch event occurs. Thus, the display panel having a touch screen function may be manufactured, and an aperture ratio in the display panel may be prevented from being deteriorated. | 10-28-2010 |
20110261028 | LIQUID CRYSTAL DISPLAY, METHOD OF DRIVING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A liquid crystal display comprising a plurality of pixels, each pixel of the plurality of pixels comprises a gate line which receives a gate signal; a data line which receives a data voltage; a first sub-pixel comprising a first transistor connected to the gate line and the data line, wherein the first transistor outputs the data voltage in response to the gate signal; and a first liquid crystal capacitor connected to the first transistor, wherein the first liquid crystal capacitor receives the data voltage output from the first transistor; a second sub-pixel comprising a second transistor connected to the gate line and the data line, wherein the second transistor outputs the data voltage in response to the gate signal; and a second liquid crystal capacitor connected to the second transistor, wherein the second liquid crystal capacitor receives the data voltage output from the second transistor; a resistor connected to the second transistor, wherein the resistor receives the data voltage output from the second transistor; and a first sharing capacitor connected to the resistor, wherein the first sharing capacitor receives the data voltage through the resistor. | 10-27-2011 |
20120044434 | DISPLAY SUBSTRATE AND FABRICATING METHOD THEREOF - An exemplary embodiment of the present invention discloses a display substrate including a pixel connected to a first gate line and a data line. The pixel includes a first sub-pixel including a first liquid crystal capacitor and a first switching element including a gate electrode connected to the first gate line, a source electrode connected to the data line, and a drain electrode connected to the first liquid crystal capacitor. The pixel also includes a second sub-pixel including a second liquid crystal capacitor and a second switching element including a gate electrode connected to the first gate line, a source electrode connected to the data line, and a drain electrode connected to the second liquid crystal capacitor. The pixel further includes a controller including a control capacitor and a control switching element, the control switching element connected between a terminal of the control capacitor and the drain electrode of the second switching element. The control capacitor includes a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is arranged on the same level on the display substrate as the gate electrode or is arranged on the same level on the display substrate as the source electrode and the drain electrode. The second capacitor electrode is arranged on the same level on the display substrate as a pixel electrode. | 02-23-2012 |
20120133873 | LIQUID CRYSTAL DISPLAY AND METHOD FOR MANUFACTURING THE SAME - A method of manufacturing a liquid crystal display includes: forming a gate line including a gate electrode on a first substrate; forming a gate insulating layer on the gate line; sequentially forming a semiconductor layer, an amorphous silicon layer, and a data metal layer on the entire surface of the gate insulating layer; aligning the edges of the semiconductor layer and the data metal layer; forming a transparent conductive layer on the gate insulating layer and the data metal layer; forming a first pixel electrode and a second pixel electrode by patterning the transparent conductive layer; and forming a data line including a source electrode, a drain electrode, and an ohmic contact layer by etching the data metal layer and the amorphous silicon layer, using the first pixel electrode and the second pixel electrode as a mask, and exposing the semiconductor between the source electrode and the drain electrode. | 05-31-2012 |
20120190157 | MASK AND METHOD OF MANUFACTURING ARRAY SUBSTRATE USING THE SAME - A mask includes: a substrate that includes a central area and a peripheral area disposed around the central area; and lenses disposed in rows and columns, in the central area and the peripheral area. The lenses of opposing sides of the peripheral area may be disposed in different rows or columns. For a given amount of input light, the lenses of the peripheral area may focus less light on a substrate than the lenses of the central area. The mask may be disposed over the substrate in different positions, and then the substrate may be irradiated through the mask, while the mask is in each of the positions. The peripheral portion of the mask may be disposed over the same area of the substrate, while the mask is in different ones of the positions. | 07-26-2012 |
20130088479 | DISPLAY DEVICE - A display device includes: an insulation substrate; a plurality of gate lines on the insulation substrate and divided into a first group and a second group; a plurality of data lines insulated from and intersecting the gate lines; a gate driver which applies a gate-on voltage to the gate lines and operates in one of a first mode and a second mode; and a data driver which applies a data voltage to the data lines, where the first group and the second group of the gate lines are applied with the gate-on voltage when the gate driver is in the first mode, and where the first group of the gate lines is applied with the gate-on voltage and the second group of the gate lines is in an off state when the gate driver is in the second mode. | 04-11-2013 |
20130093739 | DISPLAY APPARATUS - A display apparatus includes gate lines, data lines insulated from the gate lines while crossing the gate lines, and pixels each including sub-pixels in two successive rows by three successive columns. Among the sub-pixels in the two rows by the three columns, the sub-pixels in one of the three columns are respectively connected to a pair of different gate lines among three gate lines, and the sub-pixels in a different one of the three columns are connected to a remaining gate line among the three gate lines. The sub-pixels in the one and the different one of the three columns includes the same color filter and are applied with a gate signal transmitted in the same direction along pixel rows. | 04-18-2013 |
20130181747 | GATE DRIVING CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME - A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage. | 07-18-2013 |
20130230950 | MASK AND METHOD OF MANUFACTURING ARRAY SUBSTRATE USING THE SAME - A mask includes: a substrate that includes a central area and a peripheral area disposed around the central area; and lenses disposed in rows and columns, in the central area and the peripheral area. The lenses of opposing sides of the peripheral area may be disposed in different rows or columns. For a given amount of input light, the lenses of the peripheral area may focus less light on a substrate than the lenses of the central area. The mask may be disposed over the substrate in different positions, and then the substrate may be irradiated through the mask, while the mask is in each of the positions. The peripheral portion of the mask may be disposed over the same area of the substrate, while the mask is in different ones of the positions. | 09-05-2013 |
20140043066 | GATE DRIVING CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME - A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage. | 02-13-2014 |
20140092078 | Display Panel - A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit. | 04-03-2014 |
Patent application number | Description | Published |
20130093761 | DISPLAY CONTROLLER AND RELATED METHOD OF OPERATION - A display controller comprises a merger and an alpha blender. The merger is configured to mix a first left frame comprising first left pixel data and a first right frame comprising first right pixel data based on a three-dimensional (3D) display format, and further configured and to output a first mixed frame and a second mixed frame. The alpha blender is configured to blend the first mixed frame and the second mixed frame to produce a first blended frame. | 04-18-2013 |
20140240360 | METHOD FOR ROTATING AN ORIGINAL IMAGE USING SELF-LEARNING AND APPARATUSES PERFORMING THE METHOD - A method of rotating an original image includes performing a self-learning using addresses related to at least one page miss and generating address generation rules using a result of the self-learning. The method includes pre-fetching the original image from a memory device based on the address generation rules to obtain a pre-fetched image and generating a rotated image using the pre-fetched image. | 08-28-2014 |
20140253598 | GENERATING SCALED IMAGES SIMULTANEOUSLY USING AN ORIGINAL IMAGE - A method of operating an image processing circuit includes receiving a first original image, and generating a plurality of first scaled images, each having a different resolution, based on the first original image. The plurality of first scaled images are generated in response to receiving the first original image one time. | 09-11-2014 |
20140267317 | MULTIMEDIA SYSTEM AND OPERATING METHOD OF THE SAME - A multimedia system includes a main special function register (SFR) configured to store SFR information; a plurality of processing modules each configured to process frames of data, based on the SFR information; and a system control logic configured to control operations of the main SFR and the plurality of processing modules. The plurality of processing modules may process data of different frames at the same time period. | 09-18-2014 |
20140281381 | SYSTEM-ON-CHIP AND METHOD OF OPERATING THE SAME - A system-on-chip (SoC) includes a slave intellectual property (IP) block, a master IP block, and an update control unit. The slave IP block is configured to perform first processing on first data based on first control information stored in a first storage unit. The master IP block is configured to perform second processing on second data in response to receiving a first processing result obtained by performing the first processing on the first data. Performing the second processing is based on second control information stored in a second storage unit. The update control unit is configured to determine an update time of the first control information or an update time of the second control information in response to performing the first processing and performing the second processing. | 09-18-2014 |
20150213787 | DISPLAY CONTROLLER AND DISPLAY SYSTEM INCLUDING THE SAME - A display controller includes a scaler which is configured to receive a frame image, scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device, and output the frame image or the high resolution frame image to the display device for display. A method of controlling image display includes: receiving a frame image; determining whether to scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device; scaling up the frame image according to a result of the determining; and outputting the frame image or the high resolution frame image for display at the display device. | 07-30-2015 |
20150228088 | DISPLAY DEVICE AND METHOD FOR IMAGE UPDATE OF THE SAME - Provided are a display device and a method for updating an image of the same. The display device includes a display unit, a processing unit for compressing both image data corresponding to an updated region of the display unit and image data corresponding to a peripheral region adjacent to the updated region together and generating compressed image data, and a display driving unit for receiving the compressed image data and decompressing the image data, wherein the display unit displays an image corresponding to the updated region by the decompressed image data. | 08-13-2015 |
20150262337 | RECONFIGURABLE IMAGE SCALING CIRCUIT - A reconfigurable image scaling circuit includes a horizontal scalar, a bufferer, and a vertical scalar. The horizontal scalar is configured to generate a horizontally scaled image data by scaling an input image data horizontally. The bufferer includes a mapper and a plurality of buffers. The plurality of the buffers are configured to store the horizontally scaled image data. The vertical scalar is configured to generate an output image data by scaling the horizontally scaled image vertically using a vertical scaling method. | 09-17-2015 |