Lin, NY
Bor-Sheng Lin, Brewster, NY US
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20110152453 | Benzoxazine Compounds Derivated From Phenolphtalein Having Flame-Retardant Properties And A Process For Their Preparation - The instant invention relates to 3,3′-bis(3,4-dihydro-3-phenyl-2H-1,3-benzoxazin-6-yl)-1(3H)-isobenzofuranone and analogues based on phenolphthalein, formaldehyde and a primary amine. Such compounds are, when cured to form polymeric networks, difficultly inflammable and resistant to high temperatures. Such compounds may especially be used in the production of printed wiring boards. | 06-23-2011 |
Cheng T. Lin, Fresh Meadow, NY US
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20100168160 | Genipin Derivatives and Uses Thereof - Genipin derivatives and pharmaceutical compositions thereof that inhibit the activity of uncoupling protein-2 (UCP2) and are useful in treating deficient first-phase insulin secretion, non-insulin dependent diabetes mellitus, and ischemia in a mammal are disclosed. | 07-01-2010 |
Chiamu May Lin, Ney York, NY US
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20110072086 | ADAPTIVE RENDERING FOR MOBILE MEDIA SHARING - A page to be delivered to a user device is stored as page components. Based on characteristics of the user device, a page profile, an ad-banner profile and a thumbnail profile are selected. The page components are rendered based on the selected profiles. Further customization may be provided from information stored in a registration profile of a sending user and/or a registration profile of a receiving user. | 03-24-2011 |
Chiamu May Lin, New York, NY US
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20110072114 | SUBSCRIBING TO MOBILE MEDIA SHARING - A user is able to subscribe to an object by sending a mobile message or through a website. The object can be a file or a channel. The subscription message can use hierarchical mobile keywords. The user can adjust their registration information to control how much information is received from the subscription, when, and to what device the subscription is delivered. | 03-24-2011 |
Chieh-Yu Lin, Hopewell Junction, NY US
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20080301624 | SYSTEM AND METHOD FOR EMPLOYING PATTERNING PROCESS STATISTICS FOR GROUND RULES WAIVERS AND OPTIMIZATION - A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules for compliance by the layout. The process variation distributions are mapped to an intersect area distribution by creating a histogram based upon a plurality of processes for an intersect area. The intersect area is analyzed using the histogram to provide ground rule waivers and optimization. | 12-04-2008 |
Ching-Yung Lin, Forest Hills, NY US
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20090080777 | Methods and Apparatus for Filtering Video Packets for Large-Scale Video Stream Monitoring - A method of filtering video packets for video stream monitoring is provided. A video packet of a video stream is received. One or more features are extracted from a specified frame of the video packet via one or more histograms and frequency domain coefficients of the specified frame. One or more concept detectors are implemented on the one or more features creating one or more confidence values. The confidence values are transmitted to a display module for filtering of video packets. | 03-26-2009 |
20120311030 | Inferring User Interests Using Social Network Correlation and Attribute Correlation - Methods and apparatus are provided for inferring user interests from both direct and indirect social neighbors. User interests are inferred from social neighbors by exploiting the correlation among multiple attributes of a user, in addition to the social correlation of an attribute among a group of users. Attributes of a user are inferred by obtaining an inferred set of attributes comprised of one or more attributes of social neighbors of the user. Thereafter, the inferred set is modified using a user attribute correlation model describing a probability that the attributes in the inferred set co-occur on the user and one or more of the social neighbors. An inference quality of the obtained attributes can optionally be obtained based on social network properties of the social neighbors. Interactions with the user and/or the social neighbors can be employed to solicit feedback to improve the one or more inferred attributes. | 12-06-2012 |
20130036116 | PRIVACY-AWARE ON-LINE USER ROLE TRACKING - Access is obtained to a first nonnegative factor matrix and a second nonnegative factor matrix obtained by factorizing a nonnegative asymmetric matrix which represents a set of data which tracks time-stamped activities of a plurality of entities. The first nonnegative factor matrix is representative of initial role membership of the entities, and the second nonnegative factor matrix is representative of initial role activity descriptions. At a given one of the time stamps, while holding a change in the first nonnegative factor matrix constant, a change in the second nonnegative factor matrix is updated to reflect time variance of the set of data at the given one of the time stamps, without accessing actual data values at previous ones of the time stamps. At the given one of the time stamps, while holding a change in the second nonnegative factor matrix constant, a change in the first nonnegative factor matrix is updated, to reflect the time variance of the set of data at the given one of the time stamps, without accessing the actual data values at the previous ones of the time stamps. The role membership of the entities and the role activity descriptions, at the given one of the time stamps, are updated based on the updating steps. A suitable technique for nonnegative symmetric matrices is also provided. | 02-07-2013 |
20130046768 | FINDING A TOP-K DIVERSIFIED RANKING LIST ON GRAPHS - A method, system and computer program product for finding a diversified ranking list for a given query. In one embodiment, a multitude of date items responsive to the query are identified, a marginal score is established for each data item; and a set, or ranking list, of the data items is formed based on these scores. This ranking list is formed by forming an initial set, and one or more data items are added to the ranking list based on the marginal scores of the data items. In one embodiment, each of the data items has a measured relevance and a measured diversity value, and the marginal scores for the data items are based on the measured relevance and the measured diversity values of the data items. | 02-21-2013 |
20130046769 | MEASURING THE GOODNESS OF A TOP-K DIVERSIFIED RANKING LIST - A method, system and computer program product for measuring a relevance and diversity of a ranking list to a given query. The ranking list is comprised of a set of data items responsive to the query. In one embodiment, the method comprises calculating a measured relevance of the set of data items to the query using a defined relevance measuring procedure, and determining a measured diversity value for the ranking list using a defined diversity measuring procedure. The measured relevance and the measured diversity value are combined to obtain a measure of the combined relevance and diversity of the ranking list. The measured relevance of the set of data items may be based on the individual relevance of each of the data items to the query, and the diversity value may be based on the similarities of the data items to each other. | 02-21-2013 |
20150052090 | SEQUENTIAL ANOMALY DETECTION - A dataset including at least one temporal event sequence is collected. A one-class sequence classifier f(x) that obtains a decision boundary is statistically learned. At least one new temporal event sequence is evaluated, wherein the at least one new temporal event sequence is outside of the dataset. It is determined whether the at least one new temporal event sequence is one of a normal sequence or an abnormal sequence based on the evaluation. Numerous additional aspects are disclosed. | 02-19-2015 |
20150058273 | COMPOSITE PROPENSITY PROFILE DETECTOR - Detecting propensity profile for a person may comprise receiving artifacts associated with the person; detecting profile characteristics for the person based on the artifacts; receiving a plurality of predefined profiles comprising a plurality of characteristics and relationships between the characteristics over time, each of the plurality of predefined profiles specifying an indication of propensity; matching the profile characteristics for the person with one or more of the plurality of predefined profiles; and outputting one or more propensity indicators based on the matching, the propensity indicators comprising at least an expressed strength of a given propensity in the person at a given time. | 02-26-2015 |
Ching-Yung Lin, Hawthorne, NY US
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20110055379 | CONTENT-BASED AND TIME-EVOLVING SOCIAL NETWORK ANALYSIS - System and method for modeling a content-based network. The method includes finding single mode clusters from among network (sender and recipient) and content dimensions represented as a tensor data structure. The method allows for derivation of useful cross-mode clusters (interpretable patterns) that reveal key relationships among user communities and keyword concepts for presentation to users in a meaningful and intuitive way. Additionally, the derivation of useful cross-mode clusters is facilitated by constructing a reduced low-dimensional representation of the content-based network. Moreover, the invention may be enhanced for modeling and analyzing the time evolution of social communication networks and the content related to such networks. To this end, a set of non-overlapping or possibly overlapping time-based windows is constructed and the analysis performed at each successive time interval. | 03-03-2011 |
20120278261 | DETERMINING THE IMPORTANCE OF DATA ITEMS AND THEIR CHARACTERISTICS USING CENTRALITY MEASURES - Computer-implemented methods, systems, and articles of manufacture for determining the importance of a data item. A method includes: (a) receiving a node graph; (b) approximating a number of neighbor nodes of a node; and (c) calculating a average shortest path length of the node to the remaining nodes using the approximation step, where this calculation demonstrates the importance of a data item represented by the node. Another method includes: (a) receiving a node graph; (b) building a decomposed line graph of the node graph; (c) calculating stationary probabilities of incident edges of a node graph node in the decomposed line graph, and (d) calculating a summation of the stationary probabilities of the incident edges associated with the node, where the summation demonstrates the importance of a data item represented by the node. Both methods have at least one step carried out using a computer device. | 11-01-2012 |
20130124488 | METHOD AND SYSTEM FOR MANAGING AND QUERYING LARGE GRAPHS - A method, system and computer program product for managing and querying a graph. The method includes the steps of: receiving a graph; partitioning the graph into homogeneous blocks; compressing the homogeneous blocks; and storing the compressed homogeneous blocks in files where at least one of the steps is carried out using a computer device. | 05-16-2013 |
Ching-Yung Lin, Scarsdale, NY US
Patent application number | Description | Published |
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20090282047 | SYSTEM AND METHOD FOR SOCIAL INFERENCE BASED ON DISTRIBUTED SOCIAL SENSOR SYSTEM - A method (and system) for data acquisition includes extracting information from user communications and allowing a user to control the information to be extracted. The method of data acquisition may include downloading a user's sent materials from a communication data repository, analyzing the downloaded materials and extracting data portions that are authored by the user, generating statistical values from the extracted data, transmitting the generated statistical values to one or multiple repositories, receiving generated statistical values one or multiple server machines, and aggregating statistical values of multiple users. | 11-12-2009 |
20110270845 | Ranking Information Content Based on Performance Data of Prior Users of the Information Content - Methods and apparatus are provided for ranking information content based on performance data of prior users of the information content. Information content is ranked by receiving a search request specifying search criteria; identifying a preliminary document list by searching a corpus using the search criteria; identifying content elements in documents in the preliminary document list; assigning a value to at least one document in the preliminary document list based on a score for each content element in the at least one document, wherein the score is based on a performance measure of one or more related users that accessed one or more documents having a given content element; and providing search results based on the assigned values. The score can be assigned, for example, based on a regression model between the performance measure and one or more of the content elements and/or one or more social network metrics. The social network metrics can comprise, for example, graph entropy; outdegree; betweenness; network constraint and/or number of managers. The performance measure can comprise, for example, one or more of revenue generated by the related users and/or a performance rating of the related users. | 11-03-2011 |
20120173720 | SYSTEM AND METHOD FOR SOCIAL INFERENCE BASED ON DISTRIBUTED SOCIAL SENSOR SYSTEM - A method (and system) for data acquisition includes downloading a user's sent materials from a communication data repository, analyzing the sent materials and extracting data portions that are authored by the user, generating statistical values from the extracted data, transmitting the generated statistical values to one or multiple repositories, receiving the generated statistical values on one or multiple server machines, and aggregating statistical values of multiple users. | 07-05-2012 |
20120278021 | METHOD AND SYSTEM FOR DETECTING ANOMALIES IN A BIPARTITE GRAPH - A method of detecting anomalies from a bipartite graph includes analyzing the graph to determine a row-cluster membership, a column-cluster membership and a non-negative residual matrix, and in a processor, detecting the anomalies from the non-negative residual matrix. | 11-01-2012 |
20150088791 | GENERATING DATA FROM IMBALANCED TRAINING DATA SETS - Injecting generated data samples into a minority data class of an imbalanced training data set is provided. In response to receiving an input to balance the imbalanced training data set that includes a majority data class and the minority data class, a set of data samples is generated for the minority data class. A distance is calculated from each data sample in the set of generated data samples to a center of a kernel that includes a set of data samples of the majority data class. Each data sample in the set of generated data samples is stored within a corresponding distance score bucket based on the calculated distance of a data sample. Generated data samples are selected from a number of highest ranking distance score buckets. The generated data samples selected from the number of highest ranking distance score buckets are injected into the minority data class. | 03-26-2015 |
Chuangang Lin, Amherst, NY US
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20090004389 | High-performance interface materials for improving thermal contacts - A conformable, spreadable, electrically nonconductive, thermally conductive, thermally stable and phase separation resistant paste substantially consisting of fumed oxide dispersed in a non-aqueous paste-forming vehicle is disclosed. The fumed oxide is preferably silane-treated. This invention also discloses a thermal contact enhancing interface material comprising said paste, which, upon compression between two solid surfaces, forms a material that enhances the thermal contact between said surfaces. In addition, a method of providing a thermal contact between two solid surfaces is disclosed. This method comprises disposing between and in contact with said surfaces a material comprising said paste and applying a pressure to cause said paste to conform to the topography of said surfaces. | 01-01-2009 |
Chun Lin, Croton-On-Hudson, NY US
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20090075097 | PROCESS FOR PREPARING A FILM HAVING ALTERNATING MONOLAYERS OF A METAL-METAL BONDED COMPLEX MONOLAYER AND AN ORGANIC MONOLAYER BY LAYER-BY LAYER GROWTH - The present invention provides a process for preparing a thin film having alternating monolayers of a metal-metal bonded complex monolayer and an organic monolayer by layer-by-layer growth. The process comprises the steps of: (1) applying onto a surface of a substrate a first linker compound to produce a primer layer; (2) applying onto said primer layer a layer of a metal-metal bonded complex to produce a metal-metal bonded complex monolayer on said primer layer; (3) applying onto said metal-metal bonded complex monolayer a second linker compound; and optionally (4) sequentially repeating steps (2) and (3) at least once to produce said layer-by-layer grown thin film having alternating monolayers of a metal-metal bonded complex monolayer and an organic monolayer. | 03-19-2009 |
Chung-Hsun Lin, White Plains, NY US
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20110049624 | MOSFET ON SILICON-ON-INSULATOR REDX WITH ASYMMETRIC SOURCE-DRAIN CONTACTS - A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region. | 03-03-2011 |
20110049626 | ASYMMETRIC EMBEDDED SILICON GERMANIUM FIELD EFFECT TRANSISTOR - A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source region that includes embedded silicon germanium is formed within the semiconductor layer. A drain region that includes embedded silicon germanium is formed within the semiconductor layer. The source region includes an angled implantation region that extends into the embedded silicon germanium of the source region, and is asymmetric relative to the drain region. | 03-03-2011 |
20110049627 | EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT - A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively. | 03-03-2011 |
20110163379 | Body-Tied Asymmetric P-Type Field Effect Transistor - In one exemplary embodiment of the invention, an asymmetric P-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric P-type field effect transistor is operable to act as a symmetric P-type field effect transistor. | 07-07-2011 |
20110163380 | Body-Tied Asymmetric N-Type Field Effect Transistor - In one exemplary embodiment of the invention, an asymmetric N-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor. | 07-07-2011 |
20110215300 | GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE - A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices. | 09-08-2011 |
20110227043 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 09-22-2011 |
20110233674 | Design Structure For Dense Layout of Semiconductor Devices - A semiconductor structure, and a method of making, includes: a substrate; and at least one layer of silicon overlying the substrate, the layer of silicon including at least one active region having at least one device, a design layout of the active region in accordance with design layout rules including: a multiple-fingered device is mapped to a symmetric device or an asymmetric body-tied device; a single-fingered device is mapped to an asymmetric device; an active region having a single-fingered device is entirely source-up or source-down; and an active region falls into one of two categories: the active region does not include any symmetric devices or the active region does not include any asymmetric devices. In another exemplary embodiment, a design structure tangibly embodied on a computer readable medium, for use by a machine in the design, manufacture or simulation of an integrated circuit having the above semiconductor structure. | 09-29-2011 |
20110233688 | NOVEL DEVICES WITH VERTICAL EXTENSIONS FOR LATERAL SCALING - A method of forming a semiconductor device is provided, in which extension regions are formed atop the substrate in a vertical orientation. In one embodiment, the method includes providing a semiconductor substrate doped with a first conductivity dopant. Raised extension regions are formed on first portions of the semiconductor substrate that are separated by a second portion of the semiconductor substrate. The raised extension regions have a first concentration of a second conductivity dopant. Raised source regions and raised drain regions are formed on the raised extension regions. The raised source regions and the raised drain regions each have a second concentration of the second conductivity dopant, wherein the second concentration is greater than the first concentration. A gate structure is formed on the second portion of the semiconductor substrate. | 09-29-2011 |
20110241120 | Field Effect Transistor Device and Fabrication - A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device. | 10-06-2011 |
20110248362 | SELF-ALIGNED CONTACTS - A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer. | 10-13-2011 |
20110309448 | DIFFERENTIALLY RECESSED CONTACTS FOR MULTI-GATE TRANSISTOR OF SRAM CELL - A complementary metal-oxide-semiconductor static random access memory cell that includes a plurality of P-channel multi-gate transistors and a plurality of N-channel multi-gate transistors. Each transistor includes a gate electrode and source and drain regions separated by the at least one gate electrode. The SRAM cell further includes a plurality of contacts formed within the source and drain regions of at least one transistor. A plurality of contacts of at least one transistor are recessed a predetermined recess amount, wherein a resistance of the at least one transistor is varied based upon the predetermined recess amount. | 12-22-2011 |
20120007054 | Self-Aligned Contacts in Carbon Devices - A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and forming a conductive contact in the at least one cavity. | 01-12-2012 |
20120007183 | Multi-gate Transistor Having Sidewall Contacts - A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer. | 01-12-2012 |
20120043585 | Field Effect Transistor Device with Shaped Conduction Channel - A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region. | 02-23-2012 |
20120199941 | SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL) - A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner. | 08-09-2012 |
20120235234 | FIN FET DEVICE WITH INDEPENDENT CONTROL GATE - A FinFET device with an independent control gate, including: a silicon-on-insulator substrate; a non-planar multi-gate transistor disposed on the silicon-on-insulator substrate, the transistor comprising a conducting channel wrapped around a thin silicon fin; a source/drain extension region; an independently addressable control gate that is self-aligned to the fin and does not extend beyond the source/drain extension region, the control gate comprising: a thin layer of silicon nitride; and a plurality of spacers. | 09-20-2012 |
20120235247 | FIN FIELD EFFECT TRANSISTOR WITH VARIABLE CHANNEL THICKNESS FOR THRESHOLD VOLTAGE TUNING - A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers. | 09-20-2012 |
20120276739 | DIFFERENTIALLY RECESSED CONTACTS FOR MULTI-GATE TRANSISTOR OF SRAM CELL - A complementary metal-oxide-semiconductor static random access memory cell includes a plurality of P-channel multi-gate transistors and a plurality of N-channel multi-gate transistors. Each transistor includes a gate electrode and source and drain regions separated by the at least one gate electrode. The SRAM cell further includes a plurality of contacts formed within the source and drain regions of at least one transistor. A plurality of contacts of at least one transistor are recessed a predetermined recess amount, wherein a resistance of the at least one transistor is varied based upon the predetermined recess amount. | 11-01-2012 |
20120280279 | Field Effect Transistor Device with Shaped Conduction Channel - A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region. | 11-08-2012 |
20120286366 | Field Effect Transistor Device and Fabrication - In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET. | 11-15-2012 |
20120292597 | Self-Aligned Contacts in Carbon Devices - A semiconductor device includes a carbon layer disposed on a substrate, a gate stack disposed on a portion of the carbon layer, a first cavity defined by the carbon layer and the substrate, a second cavity defined by the carbon layer and the substrate, a source region including a first conductive contact disposed in the first cavity, a drain region including a second conductive contact disposed in the second cavity. | 11-22-2012 |
20120295423 | GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE - A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices. | 11-22-2012 |
20120299062 | EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT - A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively. | 11-29-2012 |
20120299125 | SELF-ALIGNED CONTACTS - A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer. | 11-29-2012 |
20120319178 | DOUBLE GATE PLANAR FIELD EFFECT TRANSISTORS - A stacked planar device and method for forming the same is shown that includes forming, on a substrate, a stack of layers having alternating sacrificial and channel layers, patterning the stack such that sides of the stack include exposed surfaces of the sacrificial and channel layers, forming a dummy gate structure over a region of the stack to establish a planar area, forming a dielectric layer around the dummy gate structure to cover areas adjacent to the planar area, removing the dummy gate structure to expose the stack, selectively etching the stack to remove the sacrificial layers from the channel layers in the planar area, and forming a gate conductor over and in between the channel layers to form a transistor device. | 12-20-2012 |
20120326236 | MULTI-GATE TRANSISTOR HAVING SIDEWALL CONTACTS - A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer. | 12-27-2012 |
20120329193 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 12-27-2012 |
20130026465 | SEMICONDUCTOR DEVICE INCLUDING AN ASYMMETRIC FEATURE, AND METHOD OF MAKING THE SAME - A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact. | 01-31-2013 |
20130106496 | NANOWIRE EFUSES | 05-02-2013 |
20130109167 | NANOWIRE EFUSES | 05-02-2013 |
20130149823 | SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL) - A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner. | 06-13-2013 |
20130153993 | HYBRID CMOS NANOWIRE MESH DEVICE AND FINFET DEVICE - A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a FINFET device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the FINFET device on the same SOI substrate. | 06-20-2013 |
20130153996 | HYBRID CMOS NANOWIRE MESH DEVICE AND PDSOI DEVICE - A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a PDSOI device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the PDSOI device on the same SOI substrate. | 06-20-2013 |
20130153997 | HYBRID CMOS NANOWIRE MESH DEVICE AND BULK CMOS DEVICE - A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a bulk CMOS device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the bulk CMOS device on the same SOI substrate. | 06-20-2013 |
20130154006 | FINFET WITH VERTICAL SILICIDE STRUCTURE - FinFETS and methods for making FinFETs with a vertical silicide structure. A method includes providing a substrate with a plurality of fins, forming a gate stack above the substrate wherein the gate stack has at least one sidewall and forming an off-set spacer adjacent the gate stack sidewall. The method also includes growing an epitaxial film which merges the fins to form an epi-merge layer, forming a field oxide layer adjacent to at least a portion of the off-set spacer and removing a portion of the field oxide layer to expose a portion of the epi-merge-layer. The method further includes removing at least part of the exposed portion of the epi-merge-layer to form an epi-merge sidewall and an epi-merge spacer region and forming a silicide within the epi-merge sidewall to form a silicide layer and two silicide sidewalls. | 06-20-2013 |
20130161744 | FINFET WITH MERGED FINS AND VERTICAL SILICIDE - A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region. | 06-27-2013 |
20130161745 | SOURCE-DRAIN EXTENSION FORMATION IN REPLACEMENT METAL GATE TRANSISTOR DEVICE - In one embodiment a transistor structure includes a gate stack disposed on a surface of a semiconductor body. The gate stack has a layer of gate dielectric surrounding gate metal and overlies a channel region in the semiconductor body. The transistor structure further includes a source having a source extension region and a drain having a drain extension region formed in the semiconductor body, where each extension region has a sharp, abrupt junction that overlaps an edge of the gate stack. Also included is a punch through stopper region having an implanted dopant species beneath the channel in the semiconductor body between the source and the drain. There is also a shallow channel region having an implanted dopant species located between the punch through stopper region and the channel. Both bulk semiconductor and silicon-on-insulator transistor embodiments are described. | 06-27-2013 |
20130161763 | SOURCE-DRAIN EXTENSION FORMATION IN REPLACEMENT METAL GATE TRANSISTOR DEVICE - A method includes forming on a surface of a semiconductor a dummy gate structure comprised of a plug; forming a first spacer surrounding the plug, the first spacer being a sacrificial spacer; and performing an angled ion implant so as to implant a dopant species into the surface of the semiconductor adjacent to an outer sidewall of the first spacer to form a source extension region and a drain extension region, where the implanted dopant species extends under the outer sidewall of the first spacer by an amount that is a function of the angle of the ion implant. The method further includes performing a laser anneal to activate the source extension and the drain extension implant. The method further includes forming a second spacer surrounding the first spacer, removing the first spacer and the plug to form an opening, and depositing a gate stack in the opening. | 06-27-2013 |
20130164890 | METHOD FOR FABRICATING FINFET WITH MERGED FINS AND VERTICAL SILICIDE - A method is provided for fabricating a finFET device. Fin structures are formed over a BOX layer. The fin structures include a semiconductor layer and extend in a first direction. A gate stack is formed on the BOX layer over the fin structures and extending in a second direction. The gate stack includes a high-K dielectric layer and a metal gate. Gate spacers are formed on sidewalls of the gate stack, and an epi layer is deposited to merge the fin structures. Ions are implanted to form source and drain regions, and dummy spacers are formed on sidewalls of the gate spacers. The dummy spacers are used as a mask to recess or completely remove an exposed portion of the epi layer. Silicidation forms silicide regions that abut the source and drain regions and each include a vertical portion located on the vertical sidewall of the source or drain region. | 06-27-2013 |
20130171813 | FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION - A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device. | 07-04-2013 |
20130175623 | RECESSED SOURCE AND DRAIN REGIONS FOR FINFETS - Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins. | 07-11-2013 |
20130175624 | RECESSED SOURCE AND DRAIN REGIONS FOR FINFETS - Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins. | 07-11-2013 |
20130176769 | 8-TRANSISTOR SRAM CELL DESIGN WITH SCHOTTKY DIODES - An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration to form two inverters for storing a single data bit, wherein each of the inverters includes a Schottky diode; first and second pass gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass gate transistors coupled to a write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. In a preferred embodiment, the 8-transistor SRAM cell has column select writing enabled for writing a value to the 8-transistor SRAM cell without inadvertently also writing a value to another 8-transistor SRAM cell. | 07-11-2013 |
20130176770 | 8-TRANSISTOR SRAM CELL DESIGN WITH INNER PASS-GATE JUNCTION DIODES - An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line; inner junction diodes at shared source/drain terminals of the pass-gate and pull-down transistors oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state. | 07-11-2013 |
20130176771 | 8-TRANSISTOR SRAM CELL DESIGN WITH OUTER PASS-GATE DIODES - An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state. | 07-11-2013 |
20130193513 | Multi-Gate Field Effect Transistor with a Tapered Gate Profile - A multi-gate field effect transistor apparatus and method for making same. The apparatus includes a source terminal, a drain terminal, and a gate terminal which includes a tapered-gate profile. A method for designing a multi-gate field effect transistor includes arranging a source terminal, a drain terminal and a gate terminal with a tapered-gate profile to create a wider gate width on a bottom of a fin. | 08-01-2013 |
20130198695 | Multi-Gate Field Effect Transistor with A Tapered Gate Profile - A multi-gate field effect transistor apparatus and method for making same. The apparatus includes a source terminal, a drain terminal, and a gate terminal which includes a tapered-gate profile. A method for designing a multi-gate field effect transistor includes arranging a source terminal, a drain terminal and a gate terminal with a tapered-gate profile to create a wider gate width on a bottom of a fin. | 08-01-2013 |
20130214357 | NON-PLANAR MOSFET STRUCTURES WITH ASYMMETRIC RECESSED SOURCE DRAINS AND METHODS FOR MAKING THE SAME - Non-planar Metal Oxide Field Effect Transistors (MOSFETs) and methods for making non-planar MOSFETs with asymmetric, recessed source and drains having improved extrinsic resistance and fringing capacitance. The methods include a fin-last, replacement gate process to form the non-planar MOSFETs and employ a retrograde metal lift-off process to form the asymmetric source/drain recesses. The lift-off process creates one recess which is off-set from a gate structure while a second recess is aligned with the structure. Thus, source/drain asymmetry is achieved by the physical structure of the source/drains, and not merely by ion implantation. The resulting non-planar device has a first channel of a fin contacting a substantially undoped area on the drain side and a doped area on the source side, thus the first channel is asymmetric. A channel on atop surface of a fin is symmetric because it contacts doped areas on both the drain and source sides. | 08-22-2013 |
20130230978 | SELF-ALIGNED CONTACTS - A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer. | 09-05-2013 |
20130256763 | LOW EXTENSION DOSE IMPLANTS IN SRAM FABRICATION - A static random access memory fabrication array includes at least one p-type field effect transistor, including a gate stack and isolating spacers forming a gate having a gate length Lgate and an effective gate length, Leff and a source and drain region adjacent the gate stack, wherein the source and drain regions are formed from a low extension dose implant that decreases a difference between Lgate and Leff. | 10-03-2013 |
20130256797 | Asymmetric FET Formed Through Use of Variable Pitch Gate for Use as Logic Device and Test Structure - Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a FET device is provided. The FET device includes a wafer; a plurality of active areas formed in the wafer; a plurality of gate stacks on the wafer, wherein at least one of the gate stacks is present over each of the active areas, and wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area; spacers on opposite sides of the gate stacks; and an angled implant in the source side of the given active area. | 10-03-2013 |
20130260516 | Asymmetric FET Formed Through Use of Variable Pitch Gate for Use as Logic Device and Test Structure - Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided. A plurality of active areas is formed in the wafer using STI. A plurality of gate stacks is formed on the wafer, wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area. Spacers are formed on opposite sides of the gate stacks. An angled implant is performed into the source side of the given active area. A FET device is also provided. | 10-03-2013 |
20130260525 | LOW EXTENSION DOSE IMPLANTS IN SRAM FABRICATION - A static random access memory fabrication method includes forming a gate stack on a substrate, forming isolating spacers adjacent the gate stack, the isolating spacers and gate stack having a gate length, forming a source and drain region adjacent the gate stack, which generates an effective gate length, wherein the source and drain regions are formed from a low extension dose implant that varies a difference between the gate length and the effective gate length. | 10-03-2013 |
20130285156 | FIN FIELD EFFECT TRANSISTOR WITH VARIABLE CHANNEL THICKNESS FOR THRESHOLD VOLTAGE TUNING - A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers. | 10-31-2013 |
20130292701 | Doped Core Trigate FET Structure and Method - Techniques for fabricating a field effect transistor (FET) device having a doped core and an undoped or counter-doped epitaxial shell are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A wafer is provided having a semiconductor material selected from the group consisting of silicon, silicon germanium and silicon carbon. At least one fin core is formed in the wafer. Ion implantation is used to dope the fin core. Corners of the fin core are reshaped to make the corners rounded or faceted. An epitaxial shell is grown surrounding the fin core, wherein the epitaxial shell includes a semiconductor material selected from the group consisting of silicon, silicon germanium and silicon carbon. | 11-07-2013 |
20130306935 | DOUBLE GATE PLANAR FIELD EFFECT TRANSISTORS - A transistor device includes multiple planar layers of channel material connecting a source region and a drain region, where the planar layers are formed in a stack of layers of a channel material; and a gate conductor formed around and between the planar layers of channel material. | 11-21-2013 |
20130328016 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 12-12-2013 |
20130341596 | NANOWIRE FET AND FINFET - A complimentary metal oxide semiconductor (CMOS) device includes a wafer having a buried oxide (BOX) layer having a first region with a first thickness and a second region with a second thickness, the first thickness is less than the second thickness, a nanowire field effect transistor (FET) arranged on the BOX layer in the first region, the nanowire FET, and a finFET arranged on the BOX layer in the second region. | 12-26-2013 |
20140034905 | Epitaxially Thickened Doped or Undoped Core Nanowire FET Structure and Method for Increasing Effective Device Width - Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX. Nanowire cores and pads are etched in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial shells are formed surrounding each of the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores/epitaxial shells, wherein the portions of the nanowire cores/epitaxial shells surrounded by the gate stack serve as channels of the device, and wherein the pads and portions of the nanowire cores/epitaxial shells that extend out from the gate stack serve as source and drain regions of the device. | 02-06-2014 |
20140034908 | Epitaxially Thickened Doped or Undoped Core Nanowire FET Structure and Method for Increasing Effective Device Width - Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX, wherein the SOI layer is present between a buried nitride layer and a nitride cap. The SOI layer, the buried nitride layer and the nitride cap are etched to form nanowire cores and pads in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial sidewalls are formed over the sidewalls of the nanowires cores. The buried nitride layer and the nitride cap are removed from the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores and the epitaxial sidewalls. | 02-06-2014 |
20140035037 | EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT - A semiconductor device includes a gate stack formed on an active region in a p-type field effect transistor (pFET) portion of a silicon-on-insulator (SOI) substrate. The SOI substrate includes a n-type field effect transistor (nFET) portion. A gate spacer is formed over the gate stack. A source region and a drain region are formed within a first region and a second region, respectively, of the pFET portion of the semiconductor layer including embedded silicon germanium (eSiGe). A source region and a drain region are formed within a first region and a second region, respectively, of the nFET portion of the semiconductor layer including eSiGe. The source and drain regions within the pFET portion includes at least one dimension that is different from at least one dimension of the source and drain regions within the nFET portion. | 02-06-2014 |
20140038368 | EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT - A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively. | 02-06-2014 |
20140048882 | TECHNIQUES FOR GATE WORKFUNCTION ENGINEERING TO REDUCE SHORT CHANNEL EFFECTS IN PLANAR CMOS DEVICES - In one aspect, a CMOS device is provided. The CMOS device includes a SOI wafer having a SOI layer over a BOX; one or more active areas formed in the SOI layer in which one or more FET devices are formed, each of the FET devices having an interfacial oxide on the SOI layer and a gate stack on the interfacial oxide layer, the gate stack having (i) a conformal gate dielectric layer present on a top and sides of the gate stack, (ii) a conformal gate metal layer lining the gate dielectric layer, and (iii) a conformal workfunction setting metal layer lining the conformal gate metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer present in the gate stack are/is proportional to a length of the gate stack. | 02-20-2014 |
20140051213 | Techniques for Metal Gate Work Function Engineering to Enable Multiple Threshold Voltage Nanowire FET Devices - A method of fabricating a nanowire FET device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are etched in the SOI layer. The nanowires are suspended over the BOX. An interfacial oxide is formed surrounding each of the nanowires. A conformal gate dielectric is deposited on the interfacial oxide. A conformal first gate material is deposited on the conformal gate dielectric. A work function setting material is deposited on the conformal first gate material. A second gate material is deposited on the work function setting material to form at least one gate stack over the nanowires. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires. | 02-20-2014 |
20140051225 | TECHNIQUES FOR GATE WORKFUNCTION ENGINEERING TO REDUCE SHORT CHANNEL EFFECTS IN PLANAR CMOS DEVICES - Techniques for gate workfunction engineering using a workfunction setting material to reduce short channel effects in planar CMOS devices are provided. In one aspect, a method of fabricating a CMOS device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A patterned dielectric is formed on the wafer having trenches therein present over active areas in which a gate stack will be formed. Into each of the trenches depositing: (i) a conformal gate dielectric (ii) a conformal gate metal layer and (iii) a conformal workfunction setting metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer deposited into a given one of the trenches are/is proportional to a length of the gate stack being formed in the given trench. A CMOS device is also provided. | 02-20-2014 |
20140061796 | TECHNIQUES FOR METAL GATE WORKFUNCTION ENGINEERING TO ENABLE MULTIPLE THRESHOLD VOLTAGE FINFET DEVICES - Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a FIN FET device is provided. The FIN FET device includes a SOI wafer having an oxide layer and a SOI layer over a BOX, and a plurality of fins patterned in the oxide layer and the SOI layer; an interfacial oxide on the fins; and at least one gate stack on the interfacial oxide, the gate stack having (i) a conformal gate dielectric layer present, (ii) a conformal gate metal layer, and (iii) a conformal work function setting material layer. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer present in the gate stack is proportional to a pitch of the fins. | 03-06-2014 |
20140065802 | TECHNIQUES FOR METAL GATE WORKFUNCTION ENGINEERING TO ENABLE MULTIPLE THRESHOLD VOLTAGE FINFET DEVICES - Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a method of fabricating a FIN FET device includes the following steps. A SOI wafer having a SOI layer over a BOX is provided. An oxide layer is formed over the SOI layer. A plurality of fins is patterned in the SOI layer and the oxide layer. An interfacial oxide is formed on the fins. A conformal gate dielectric layer, a conformal gate metal layer and a conformal work function setting material layer are deposited on the fins. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer deposited over the fins is proportional to a pitch of the fins. A FIN FET device is also provided. | 03-06-2014 |
20140131708 | SEMICONDUCTOR DEVICE INCLUDING AN ASYMMETRIC FEATURE, AND METHOD OF MAKING THE SAME - A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact. | 05-15-2014 |
20140175374 | HYBRID CMOS NANOWIRE MESH DEVICE AND FINFET DEVICE - A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate containing a nanowire mesh device and a second portion of the SOI substrate containing a FINFET device. The nanowire mesh device including stacked and spaced apart semiconductor nanowires located on the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region. The FINFET device including spaced apart fins on a top semiconductor layer on the second portion of the substrate; and a gate region over at least a portion of the fins. | 06-26-2014 |
20140175375 | HYBRID CMOS NANOWIRE MESH DEVICE AND PDSOI DEVICE - A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate contains a nanowire mesh device and a second portion of the SOI substrate contains a partially depleted semiconductor on insulator (PDSOI) device. The nanowire mesh device includes stacked and spaced apart semiconductor nanowires located on the SOI substrate with each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region. The nanowire mesh device further includes a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires. The PDSOI device includes a partially depleted semiconductor layer on the substrate, and a gate region over at least a portion of the partially depleted semiconductor layer. | 06-26-2014 |
20140201699 | METHODS FOR MODELING OF FINFET WIDTH QUANTIZATION - A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (I | 07-17-2014 |
20140201700 | APPARATUS FOR MODELING OF FINFET WIDTH QUANTIZATION - A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (I | 07-17-2014 |
20140217364 | Diode Structure and Method for Wire-Last Nanomesh Technologies - In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack. | 08-07-2014 |
20140217502 | Diode Structure and Method for Wire-Last Nanomesh Technologies - In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack. | 08-07-2014 |
20140217506 | Diode Structure and Method for FINFET Technologies - A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device. | 08-07-2014 |
20140217507 | Diode Structure and Method for Gate All Around Silicon Nanowire Technologies - A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration. | 08-07-2014 |
20140217508 | Diode Structure and Method for FINFET Technologies - A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device. | 08-07-2014 |
20140217509 | Diode Structure and Method for Gate All Around Silicon Nanowire Technologies - A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration. | 08-07-2014 |
20140264593 | Hybrid ETSOI Structure to Minimize Noise Coupling from TSV - In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided. | 09-18-2014 |
20140264605 | Hybrid ETSOI Structure to Minimize Noise Coupling from TSV - In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided. | 09-18-2014 |
20140266254 | Techniques for Quantifying Fin-Thickness Variation in FINFET Technology - Techniques for quantifying ΔDfin in FINFET technology are provided. In one aspect, a method for quantifying ΔDfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ΔVth for the pair of long channel FINFET devices; and (c) using the ΔVth to determine the ΔDfin between the pair of long channel FINFET devices, wherein the ΔVth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ΔVth is proportional to the ΔDfin between the pair of long channel FINFET devices. | 09-18-2014 |
20140273298 | Techniques for Quantifying Fin-Thickness Variation in FINFET Technology - Techniques for quantifying ΔDfin in FINFET technology are provided. In one aspect, a method for quantifying ΔDfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ΔVth for the pair of long channel FINFET devices; and (c) using the ΔVth to determine the ΔDfin between the pair of long channel FINFET devices, wherein the ΔVth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ΔVth is proportional to the ΔDfin between the pair of long channel FINFET devices. | 09-18-2014 |
20140310676 | METHODS FOR MODELING OF FINFET WIDTH QUANTIZATION - A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (I | 10-16-2014 |
20140312419 | FINFET DEVICES CONTAINING MERGED EPITAXIAL FIN-CONTAINING CONTACT REGIONS - A plurality of semiconductor fins are formed which extend from a semiconductor material portion that is present atop an insulator layer of a semiconductor-on-insulator substrate. A gate structure and adjacent gate spacers are formed that straddle each semiconductor fin. Portions of each semiconductor fin are left exposed. The exposed portions of the semiconductor fins are then merged by forming an epitaxial semiconductor material from an exposed semiconductor material portion that is not covered by the gate structure and gate spacers. | 10-23-2014 |
20140312420 | FINFET DEVICES CONTAINING MERGED EPITAXIAL FIN-CONTAINING CONTACT REGIONS - A plurality of semiconductor fins are formed which extend from a semiconductor material portion that is present atop an insulator layer of a semiconductor-on-insulator substrate. A gate structure and adjacent gate spacers are formed that straddle each semiconductor fin. Portions of each semiconductor fin are left exposed. The exposed portions of the semiconductor fins are then merged by forming an epitaxial semiconductor material from an exposed semiconductor material portion that is not covered by the gate structure and gate spacers. | 10-23-2014 |
20140332890 | STRINGER-FREE GATE ELECTRODE FOR A SUSPENDED SEMICONDUCTOR FIN - At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the recessed surfaces of the insulator layer and the bottom surface(s) of the at least one semiconductor fin. An interface between the metallic gate electrode layer and a semiconductor gate electrode layer contiguously extends over the at least one semiconductor fin and does not underlie any of the at least one semiconductor fin. During patterning of a gate electrode, removal of the semiconductor material in the semiconductor gate electrode layer can be facilitated because the semiconductor gate electrode layer is not present under the at least one semiconductor fin. | 11-13-2014 |
20140332892 | STRINGER-FREE GATE ELECTRODE FOR A SUSPENDED SEMICONDUCTOR FIN - At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the recessed surfaces of the insulator layer and the bottom surface(s) of the at least one semiconductor fin. An interface between the metallic gate electrode layer and a semiconductor gate electrode layer contiguously extends over the at least one semiconductor fin and does not underlie any of the at least one semiconductor fin. During patterning of a gate electrode, removal of the semiconductor material in the semiconductor gate electrode layer can be facilitated because the semiconductor gate electrode layer is not present under the at least one semiconductor fin. | 11-13-2014 |
20140339640 | FINFET WITH VERTICAL SILICIDE STRUCTURE - FinFETS and methods for making FinFETs with a vertical silicide structure. A method includes providing a substrate with a plurality of fins, forming a gate stack above the substrate wherein the gate stack has at least one sidewall and forming an off-set spacer adjacent the gate stack sidewall. The method also includes growing an epitaxial film which merges the fins to form an epi-merge layer, forming a field oxide layer adjacent to at least a portion of the off-set spacer and removing a portion of the field oxide layer to expose a portion of the epi-merge-layer. The method further includes removing at least part of the exposed portion of the epi-merge-layer to form an epi-merge sidewall and an epi-merge spacer region and forming a silicide within the epi-merge sidewall to form a silicide layer and two silicide sidewalls. | 11-20-2014 |
Chung-Hsun Lin, Yorktown Heights, NY US
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20110049583 | Recessed contact for multi-gate FET optimizing series resistance - A transistor, which can be referred to as a multi-gate transistor or as a FinFET, includes a gate structure having a length, a width and a height. The transistor further includes at least one electrically conductive channel or fin between a source region and a drain region that passes through the width of the gate structure. The channel has a first height (h | 03-03-2011 |
20110063019 | DUAL DIELECTRIC TRI-GATE FIELD EFFECT TRANSISTOR - A dual dielectric tri-gate field effect transistor, a method of fabricating a dual dielectric tri-gate field effect transistor, and a method of operating a dual dielectric tri-gate effect transistor are disclosed. In one embodiment, the dual dielectric tri-gate transistor comprises a substrate, an insulating layer on the substrate, and at least one semiconductor fin. A first dielectric having a first dielectric constant extends over sidewalls of the fin, and a metal layer extends over the first dielectric, and a second dielectric having a second dielectric constant is on a top surface of the fin. A gate electrode extends over the fin and the first and second dielectrics. The gate electrode and the first dielectric layer form first and second gates having a threshold voltage Vt | 03-17-2011 |
20110065244 | ASYMMETRIC FINFET DEVICE WITH IMPROVED PARASITIC RESISTANCE AND CAPACITANCE - A method for forming a fin field effect transistor (finFET) device includes, forming a fin structure in a substrate, forming a gate stack structure perpendicular to the fin structure, and implanting ions in the substrate at an angle (θ) to form a source region and a drain region in the substrate, wherein the angle (θ) is oblique relative to the source region. | 03-17-2011 |
20110084315 | SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL) - A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner. | 04-14-2011 |
20110108900 | BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR - A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack. | 05-12-2011 |
20110115044 | DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE - A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other. | 05-19-2011 |
20110298058 | FACETED EPI SHAPE AND HALF-WRAP AROUND SILICIDE IN S/D MERGED FINFET - FinFETs and methods of making. FinFETs are provided. The FinFET contains two or more fins over a semiconductor substrate; two or more epitaxial layers over side surfaces of the fins; and metal-semiconductor compounds over an upper surfaces of the epitaxial layers. The fin has side surfaces that are substantially vertical relative to the upper surface of the semiconductor substrate. The epitaxial layer has an upper surface that extends at an oblique angle with respect to the side surface of the fin. The FinFET can contain a contact over the metal-semiconductor compounds. | 12-08-2011 |
20120112310 | DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE - A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other. | 05-10-2012 |
20120292678 | BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR - A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack. | 11-22-2012 |
20130023093 | RECESSED CONTACT FOR MULTI-GATE FET OPTIMIZING SERIES RESISTANCE - A method to fabricate a transistor including forming at least one electrically conductive channel structure over a substrate, the channel having a length, a width and a first height (h | 01-24-2013 |
David M. Lin, New York, NY US
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20120180676 | Methods and Apparatus for High-Throughput Formation of Nano-Scale Arrays - An apparatus for forming an array of deposits on a substrate is disclosed. The apparatus may include a stencil capable of releasable attached to the substrate and having an array of openings and at least one alignment mark. The apparatus may further include a high throughput deposition printer aligned with the stencil to form an array of deposits on the substrate. The array of deposits may be aligned with the array of openings through the at least one alignment mark and an optional alignment device. Methods of manufacturing the stencil and using it to generate multiplexed or combinatorial arrays are also disclosed. | 07-19-2012 |
Elaine Lin, New York, NY US
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20110135711 | Methods and Compositions for Delivery of Catecholic Butanes for Treatment of Tumors - The present invention provides kits, methods and compositions for the treatment of diseases such as cancers. The compositions herein contain a substantially pure preparation of at least one catecholic butane, including, for example, NDGA compounds in a pharmaceutically acceptable carrier or excipient. The catecholic butane such as NDGA or its derivatives are administered to one or more subjects in need of treatment by a route other than direct injection into the affected tissues or topical application on affected tissues. | 06-09-2011 |
Erwin Lin, Whitestone, NY US
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20090018504 | SYSTEMS AND METHODS FOR INTRAVASCULAR COOLING - Methods and systems for infusing a cooled infusate to a target location in a patient are described. A temperature of the blood and infusate admixture upstream of the catheter as well as at other locations along the catheter may be monitored and a feedback system utilized to control the volume, temperature, and/or infusion rate of the infusate so as to achieve a predetermined temperature at the target location. Control may also be based on the patient's native vessel flow rate. The system may monitor or calculate hematocrit upstream of the catheter and adjust infusion so as to provide sufficient oxygenation of the blood and infusate admixture. The system may also monitor reflux of the infusate past a distal end of the catheter and reduce infusion upon the detection of reflux. | 01-15-2009 |
20090198122 | SYSTEMS AND METHODS FOR DETERMINING METABOLIC RATE USING TEMPERATURE SENSITIVE MAGNETIC RESONANCE IMAGING - A method for determining a metabolic rate of a portion of a body of a patient. The method includes obtaining magnetic resonance information from the portion of the body after introduction of a fluid and determining a magnetic resonance parameter using the magnetic resonance information. The method further includes using the magnetic resonance parameter to determine a temperature differential in the portion of the body and using the temperature differential to determine a metabolic rate of the portion of the body. | 08-06-2009 |
20100268065 | SYSTEMS AND METHODS FOR IMAGING A BLOOD VESSEL USING TEMPERATURE SENSITIVE MAGNETIC RESONANCE IMAGING - A method for producing an image of a blood vessel in a patient utilizing temperature sensitive MRI measurement. The method includes introducing a fluid in a blood vessel, obtaining magnetic resonance information from the blood vessel, and determining a magnetic resonance parameter using the magnetic resonance information. The method further includes using the magnetic resonance parameter to determine a temperature differential in the blood vessel and producing an image of the blood vessel based on the temperature differential. Systems for producing an image of a blood vessel in a patient using temperature sensitive MRI measurements are also provided. | 10-21-2010 |
20110224536 | SYSTEMS AND METHODS FOR DETERMINING A TEMPERATURE DIFFERENTIAL USING TEMPERATURE SENSITIVE MAGNETIC RESONANCE IMAGING - A method and apparatus for determining a temperature differential at a portion of a patient's body utilizing temperature sensitive MRI measurements. A diagnostic fluid bolus is administered into a blood vessel of the patient, wherein the diagnostic fluid bolus has a diagnostic fluid bolus temperature waveform. MRI measurements are used to determine the thermodiluted temperature waveform of the diagnostic fluid bolus at a target site in the body spaced away from the administration site. The temperature differential may be used to determine a cardiovascular parameter. | 09-15-2011 |
20130150705 | SYSTEMS AND METHODS FOR IMAGING A BLOOD VESSEL USING TEMPERATURE SENSITIVE MAGNETIC RESONANCE IMAGING - A method for producing an image of a blood vessel in a patient utilizing temperature sensitive MRI measurement. The method includes introducing a fluid in a blood vessel, obtaining magnetic resonance information from the blood vessel, and determining a magnetic resonance parameter using the magnetic resonance information. The method further includes using the magnetic resonance parameter to determine a temperature differential in the blood vessel and producing an image of the blood vessel based on the temperature differential. Systems for producing an image of a blood vessel in a patient using temperature sensitive MRI measurements are also provided. | 06-13-2013 |
20130331916 | SYSTEMS AND METHODS FOR INTRAVASCULAR COOLING - Methods and systems for infusing a cooled infusate to a target location in a patient are described. A temperature of the blood and infusate admixture upstream of the catheter as well as at other locations along the catheter may be monitored and a feedback system utilized to control the volume, temperature, and/or infusion rate of the infusate so as to achieve a predetermined temperature at the target location. Control may also be based on the patient's native vessel flow rate. The system may monitor or calculate hematocrit upstream of the catheter and adjust infusion so as to provide sufficient oxygenation of the blood and infusate admixture. The system may also monitor reflux of the infusate past a distal end of the catheter and reduce infusion upon the detection of reflux. | 12-12-2013 |
Fubao Lin, Stony Brook, NY US
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20090111738 | FIBRONECTIN POLYPEPTIDES AND METHODS OF USE - Described herein are fragments of fibronectin and variants thereof that bind growth factors. Compositions containing such a fragment of fibronectin are therefore useful in sequestering growth factors, and complexes containing both a FN fragment and a bound, active growth factor can be used to deliver growth factors to a patient (e.g., to a wound on the patient's skin). | 04-30-2009 |
Gang Lin, Forest Hills, NY US
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20110118274 | PROTEASOME INHIBITORS AND THEIR USE IN TREATING PATHOGEN INFECTION AND CANCER - The present invention relates to proteasome inhibitors and their use in methods of treating a subject for a pathogen infection or cancer. The methods involve administering to the subject a compound of Formula (I). (I) where: Q is Formula or Formula, where the crossing dashed line illustrates the bond formed joining Q to the rest of the compound of Formula (I). The remainder of substituents of the compound of Formula (I) are defined in the present application. | 05-19-2011 |
George Lin, Orangeburg, NY US
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20110209896 | FEP PELLET - An FEP pellet having a volatile content of 0.2% by weight or less. The FEP pellet satisfies the following requirements (i) and (ii) when used to form a insulating material coating a core wire by extrusion coating at a coating speed of 2,800 ft/min.: (i) an adhesive strength between the insulating material and said core wire of 0.8 kg or more; and (ii) an average number of cone-breaks in the insulating material of one or less per 50,000 feet of the coated core wire. | 09-01-2011 |
Grace Yuh-Jiun Lin, Chappaqua, NY US
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20080215410 | LARGE INVENTORY-SERVICE OPTIMIZATION IN CONFIGURE-TO-ORDER SYSTEMS - A manufacturing process is migrated from an existing operation to a configure-to-order (CTO) system. As the CTO operation will eliminate the “machine-type model” (MTM) inventory of the existing operation, the emphasis is shifted to the components, or “building blocks”, which will still follow the build-to-stock scheme, due to their long leadtimes, and hence still require inventory. The solution involves an inventory-service trade-off of the new CTO system, resulting in performance gains, in terms of reduced inventory cost and increased service level. Other benefits include better forecast accuracy through parts commonality and risk-pooling, and increased customer demand, as orders will no longer be confined within a restricted set of pre-configured MTMs. | 09-04-2008 |
20140031966 | Large Inventory-Service Optimization in Configure-To-Order Systems - A manufacturing process is migrated from an existing operation to a configure-to-order (CTO) system. As the CTO operation will eliminate the “machine-type model” (MTM) inventory of the existing operation, the emphasis is shifted to the components, or “building blocks”, which will still follow the build-to-stock scheme, due to their long leadtimes, and hence still require inventory. The solution involves an inventory-service trade-off of the new CTO system, resulting in performance gains, in terms of reduced inventory cost and increased service level. Other benefits include better forecast accuracy through parts commonality and risk-pooling, and increased customer demand, as orders will no longer be confined within a restricted set of pre-configured MTMs. | 01-30-2014 |
Hao Lin, Rochester, NY US
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20110240123 | Photovoltaic Cells With Improved Electrical Contact - A photovoltaic cell comprising a metal oxide back buffer layer. Improved n-CdS/p-CdTe heterojunction photovoltaic cells comprising a metal oxide buffer layer for making low-resistance electrical contact to the p-type CdTe layer. The back buffer layer comprises metal oxides having a high work function. | 10-06-2011 |
20130074921 | Low-Resistance Back Contact For Photovoltaic Cells - Photovoltaic cells (e.g., p-CdTe thin film photovoltaic cells) comprising a back contact buffer layer that makes low-resistance electrical contact to the p-type semiconductor material of the cell (e.g., CdTe). The back contact buffer material comprises Cu and Te. | 03-28-2013 |
How Lin, Vestal, NY US
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20120038046 | SEMI-CONDUCTOR CHIP WITH COMPRESSIBLE CONTACT STRUCTURE AND ELECTRONIC PACKAGE UTILIZING SAME - A method of forming a compressible contact structure on a semi-conductor chip which comprises bonding a compressible polymer layer to the chip's surface, forming a plurality of openings within the layer, depositing electrically conductive material within the openings to form electrical connections with the chip's contacts, forming a plurality of electrically conductive line elements on the polymer layer extending from a respective opening and each including an end portion, and forming a plurality of contact members each on a respective one of the line segment end portions. The compressible polymer layer allows the contact members to deflect toward (compress) the chip when the contact members are engaged by an external force or forces. A semi-conductor chip including such a compressible contact structure is also provided. | 02-16-2012 |
How T. Lin, Vestal, NY US
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20080238323 | LED lighting assembly and lamp utilizing same - An LED lighting assembly including a plurality of individual LEDs mounted on a common, bendable heat sinking member designed to remove heat from the LEDs during operation and also to be formed (bent) to provide the desired light direction and intensity. Several such assemblies may be used within an LED lamp, as also provided herein. The lamp is ideal for use within medical and dental environments to assure optimal light onto a patient located at a specified distance from the lamp. | 10-02-2008 |
20080248596 | Method of making a circuitized substrate having at least one capacitor therein - A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art. In still another embodiment, at least two spaced-apart conductors may be formed within a metal layer deposited on a dielectric layer, these conductors defining a channel there-between. The capacitive dielectric material may then be deposited (e.g., using lamination) within the channels. | 10-09-2008 |
20090092353 | Method of making circuitized substrate with internal optical pathway - A circuitized substrate (e.g., PCB) including an internal optical pathway as part thereof such that the substrate is capable of transmitting and/or receiving both electrical and optical signals. The substrate includes an angular reflector on one of the cladding layers such that optical signals passing through the optical core will impinge on the angled reflecting surfaces of the angular reflector and be reflected up through an opening (including one with optically transparent material therein), e.g., to a second circuitized substrate also having at least one internal optical pathway as part thereof, to thus interconnect the two substrates optically. A method of making the substrate is also provided. | 04-09-2009 |
20090093073 | Method of making circuitized substrate with internal optical pathway using photolithography - A method of making a circuitized substrate (e.g., PCB) including at least one and possibly several internal optical pathways as part thereof such that the resulting substrate will be capable of transmitting and/or receiving both electrical and optical signals. The method involves forming at least one opening between a side of the optical core and an adjacent upstanding member such that the opening is defined by at least one angular sidewall. Light passing through the optical core material (or into the core from above) is reflected off this angular sidewall. The medium (e.g., air) within the opening thus also serves as a reflecting medium due to its own reflective index in comparison to that of the adjacent optical core material. The method utilizes many processes used in conventional PCB manufacturing, thereby keeping costs to a minimum. The formed substrate is capable of being both optically and electrically coupled to one or more other substrates possessing similar capabilities, thereby forming an electro-optical assembly of such substrates. | 04-09-2009 |
20090109624 | Circuitized substrate with internal cooling structure and electrical assembly utilizing same - An electrical assembly which includes a circuitized substrate including a first plurality of dielectric and electrically conductive circuit layers alternatively oriented in a stacked orientation, a thermal cooling structure bonded to one of the dielectric layers and at least one electrical component mounted on the circuitized substrate. The circuitized substrate includes a plurality of electrically conductive and thermally conductive thru-holes located therein, selected ones of the thermally conductive thru-holes thermally coupled to the electrical component(s) and extending through the first plurality of dielectric and electrically conductive circuit layers and being thermally coupled to the thermal cooling structure, each of these selected ones of thermally conductive thru-holes providing a thermal path from the electrical component to the thermal cooling structure during assembly operation. The thermal cooling structure is adapted for having cooling fluid pass there-through during operation of the assembly. A method of making the substrate is also provided. | 04-30-2009 |
20090206051 | Capacitive substrate and method of making same - A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation. | 08-20-2009 |
20120015532 | HIGH DENSITY DECAL AND METHOD FOR ATTACHING SAME - A flexible, high density decal and the use thereof methods of forming detachable electrical interconnections between a flexible chip carrier and a printed wiring board. The flexible decal has fine-pitch pads on a first surface and pads of a pitch wider than the fine pitch on a second surface, the fine-pitch pads on the first surface designed to electrically connect to a semiconductor device, and the wider-pitch pads on the second surface designed to electrically connect to a printed wiring board or the like. The pads on the first surface are conductively wired to the pads on the second surface through one or more insulating levels in the flexible decal. | 01-19-2012 |
20120223047 | METHOD OF FORMING MULTILAYER CAPACITORS IN A PRINTED CIRCUIT SUBSTRATE - Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces. | 09-06-2012 |
20120260063 | MODULAR, DETACHABLE COMPUTE LEAF FOR USE WITH COMPUTING SYSTEM - A detachable, logic leaf module having dendritic projections on a surface is connected to a recessed area on the surface of a cluster interface board. The projections are used for electrically connecting the logic module device to the cluster interface board or the like, the projections on the surface of the logic leaf being flexibly and conductively wired to the receiving area on the surface of the cluster interface board. The logic leaf connector is removable without the need for solder softening thermal cycles or special tools, and permits the simple removal or replacement of an individual leaf at any time. | 10-11-2012 |
Hsin Chieh Lin, Yorktown Heights, NY US
Patent application number | Description | Published |
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20100129817 | IDENTIFYING GERMLINE COMPETENT EMBRYONIC STEM CELLS - Methods and compositions for selecting ES cells that are germline competent are provided, including gene expression arrays of from one to about 300 or more genes. Selecting ES cells that are competent for germline transmission by comparing the expression of one or more genes between an ES cell that is competent at germline transmission with an ES cell of interest is described. Selecting ES cells likely to be competent at germline transmission, based on their level of expression of gtl2, is also described. | 05-27-2010 |
Hsin-Jung Lin, Forest Hills, NY US
Hung-Yun Lin, Schenectady, NY US
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20090298058 | Inhibitors of PGHS-2Transactivator Activity - Prostaglandin-endoperoxide H synthase (PGHS-2) converts arachidonic acid to prostaglandin H | 12-03-2009 |
20100159021 | Small Molecule Ligands of the Integrin RGD Recognition Site and Methods of Use - Provided herein are compositions and methods for treating cancer by increasing the pro-apototic actions of small molecule ligands of integrin RGD recognition sites such as polyphenols by administering such compounds in conjunction with anti-angiogenic thyroid hormone analogs such as tetrac or triac. | 06-24-2010 |
20100255108 | Combination Treatment of Cancer With Cetuximab and Tetrac - Provided herein are compositions and methods for treating cancer by increasing the inhibitory effect of cetuximab on HIF1α expression by administering cetuximab in combination with anti-angiogenic thyroid hormone analogs such as tetrac or triac. | 10-07-2010 |
I-Chyang Lin, Spring Valley, NY US
Patent application number | Description | Published |
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20080306183 | Antimicrobial polyolefin and polyester compositions - Disclosed are polyolefin or polyester fibers, films and molded parts that have excellent durable antimicrobial activity. The polyolefins and polyesters have incorporated therein one or more silver antimicrobial additives and one or more wettability additives. The silver antimicrobials are for example silver supported on a zeolite, silver supported on a glass, elemental silver, micro or nano scaled elemental silver, elemental silver dispersed in silocone oil, silver chloride, silver nitrate, silver sulfate, silver phosphate, silver zirconate or silver apatite. The wettability additives are for instance ethoxylated alcohols CH | 12-11-2008 |
20100136073 | ANTIMICROBIAL PLASTICS AND COATINGS - Plastics and coatings are provided outstanding antimicrobial activity by incorporation therein of elemental silver and silver supported on a zeolite or on a glass. The compositions are suitable for medical use, for example for tubes, catheters, textiles and the like. The plastic textiles are woven or nonwoven. The plastics are for example polyurethane, polycarbonate, liquid silicone rubber, polypropylene or polyethylene or polymer composites. | 06-03-2010 |
Jie Lin, Rochester, NY US
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20080201215 | MOBILE ADVERTISEMENT METHODS AND SYSTEMS - A method of displaying an advertisement on a vehicle comprising the steps of detecting a user's wireless transmission, receiving information pertaining to an advertisement from a user via a wireless interface, activating an electronic paper screen by supplying power to the screen, displaying the advertisement on the electronic paper screen and removing the power to the electronic paper screen such that the advertisement may still be displayed on the electronic paper screen after the power is removed. | 08-21-2008 |
20080235158 | Processor, system and method for accommodating high priority print jobs - Disclosed herein is a production planning processor comprising an admissions control module in communication with a queue management module, the admissions control module calculating a proposed profit for expedited handling of a new print job, the queue management module determining a revised print job queue based upon data received from the admissions control module. A corresponding method of processing print jobs is also disclosed, along with a system and a method for determining the profitability of accommodating a rush print job. | 09-25-2008 |
20090033996 | SYSTEM AND METHOD OF EVALUATING PRINT SHOP CONSOLIDATION OPTIONS IN AN ENTERPRISE - A print shop consolidation system including a print shop consolidation management system with an application is provided. The application is used to (1) evaluate, with a set of information, an operational capacity of a first print shop to process both a first group of print jobs and a second group of print jobs, (2) evaluate, with the set of information, an operational capacity of the second print shop to process both the first and second groups of print jobs, and (3) use the evaluations of )1) and (2) to consolidate processing of the first and second groups of print jobs at one of first and second print shops. | 02-05-2009 |
Jie Lin, Webster, NY US
Patent application number | Description | Published |
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20110228338 | SYSTEM AND METHOD FOR DEVELOPING A PRINT SHOP CONFIGURATION - A system is provided for forming a print shop configuration with a first set of equipment, the first set of equipment being derived from a second set of equipment from a first print shop and a third set of equipment from a second print shop. The system includes a manager and application, the manager and application working together to generate a list of at least some of all possible print shop configurations that could be formed with a selected number of cells. The cells are populated with selected pieces of equipment from the second and third sets of multiple pieces of equipment. A criterion is used to select, from the list of possible print shop configurations, the print shop configuration with the first set of equipment. | 09-22-2011 |
Julianna Lin, Rochester, NY US
Patent application number | Description | Published |
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20100303280 | METHOD FOR MEASUREMENT OF REFLECTANCE PROFILES OF IMAGE SURFACES - A system of measuring the bare belt signature of a surface that does not require the use of extra print jobs, or extra belt cycles, during the printing of the actual print job. Instead, the inter-document zone and other “toner-free” areas within the test job itself are used to extract an estimate of the bare belt signature. More specifically, prior knowledge of the job content and of the location of the area between image pitches is used to identify areas of the belt that should be toner-free. These areas are then treated as “bare belt” segments, and the sensor signal for these areas are extracted, aligned according to their spatial location along the belt, and then averaged to produce a final estimate of the bare belt signature. | 12-02-2010 |
Julianna Elizabeth Lin, Rochester, NY US
Patent application number | Description | Published |
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20090033918 | METHOD AND APPARATUS FOR ROBUST DETECTION OF THE DENSITY OF A PIGMENTED LAYER - Aspects of the disclosure can provide a method of detecting a density of a pigmented layer on an object. The method can include emitting a first modulated light onto a first portion of the object having the pigmented layer, detecting a first reflected light of the first modulated light from the first portion of the object, and determining the density of the pigmented layer according to the first reflected light. Furthermore, the method can include emitting a second modulated light onto a second portion of the object, detecting a second reflected light of the second modulated light from the second portion of the object, and determining the density of the pigmented layer according to a relative ratio that is related to the first reflected light and the second reflected light. | 02-05-2009 |
20100003044 | AMPLITUDE MODULATION OF ILLUMINATORS IN SENSING APPLICATIONS IN PRINTING SYSTEM - An image printing system includes a print engine and a sensing system. The print engine is configured to print a marking material image on a image bearing surface. The sensing system includes a plurality of illuminators, a modulator, a sensor, and a demodulator. Each illuminator is configured to simultaneously emit a light beam at the marking material image on the image bearing surface, thereby producing reflectance from the marking material image at least in a first direction. The modulator is configured to modulate an intensity characteristic of each of the light beams emitted by the illuminators such that each light beam has a different modulated waveform characteristic, where the waveform characteristic includes at least frequency. The sensor is configured to detect the reflectance from the plurality of light beams in the first direction and output a reflectance signal. The demodulator is configured to demodulate the reflectance signal to isolate a response of the marking material image to each of the individual illuminators. | 01-07-2010 |
20120294514 | TECHNIQUES TO ENABLE AUTOMATED WORKFLOWS FOR THE CREATION OF USER-CUSTOMIZED PHOTOBOOKS - A system and method for generating a photobook are provided. The method includes receiving a set of images and automatically selecting a subset of the images as candidates for inclusion in a photobook. At least one design element of a design template for the photobook is automatically selected, based on information extracted from at least one of the images in the subset. Placeholders of the design template are automatically filled with images drawn from the subset to form at least one page of a multipage photobook. The exemplary system and method address some of the problems of photobook creation, thorough combining automatic methods for selecting, cropping, and placing photographs into a photo album template, which the user can then post-edit, if desired. This can greatly reduce the time required to create a photobook and thus encourage users to print photo albums. | 11-22-2012 |
20130108179 | PERSONALIZED PHOTO CALENDAR GENERATION SYSTEM AND METHOD | 05-02-2013 |
Leu-Fen H. Lin, White Plains, NY US
Liang-Bih Lin, Rocheter, NY US
Patent application number | Description | Published |
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20080220352 | Photoconductors containing chelating components - A photoconductor containing a supporting substrate, a photogenerating layer; and at least one charge transport layer where the photogenerating layer contains a photogenerating pigment and a chelating additive or agent. | 09-11-2008 |
Lipyeow Lin, Hawthorne, NY US
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20080219278 | METHOD FOR FINDING SHARED SUB-STRUCTURES WITHIN MULTIPLE HIERARCHIES - Shared sub-structures are found within a collection of multiple hierarchies. A label is associated with each node in the collection of hierarchies, and an inverted index mapping node labels to lists of hierarchies is created. Each pair of hierarchies in each hierarchy list is iterated over in a certain order, and a shared substructure is found between a pair of hierarchies using the node labels. When more than one shared substructure is found, the substructures are merged into a shared subtree. | 09-11-2008 |
20080221939 | METHODS FOR REWRITING AGGREGATE EXPRESSIONS USING MULTIPLE HIERARCHIES - Key performance indicator (KPI) expressions are rewritten using metric hierarchies. A node label is associated with each node in the metric hierarchies, the metric hierarchies arranged in arbitrary trees. Node labels associated with each term in a KPI expression are retrieved, and the terms in the KPI expression are sorted according to the node labels. The terms are grouped according to the node labels, and a collection of groups that covers all the terms in the KPI expression is found. Overlaps in the covering groups may be minimized. | 09-11-2008 |
Ma Lin, Webster, NY US
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20100129743 | UNDERCOAT LAYERS AND METHODS FOR MAKING THE SAME - The presently disclosed embodiments are directed to layers that are useful in imaging apparatus members and components, for use in electrostatographic, including digital, apparatuses. More particularly, the present embodiments provide a robust undercoat layer comprising TiSi in which the TiO | 05-27-2010 |
Qiao Lin, New York, NY US
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20100151465 | Selective Capture and Release of Analytes - The described subject matter includes techniques and components for minimally invasive, selective capture and release of analytes. An aptamer is selected for its binding affinity with a particular analyte(s). The aptamer is functionalized on a solid phase, for example, microbeads, polymer monolith, microfabricated solid phase, etc. The analyte is allowed to bind to the aptamer, for example, in a microchamber. Once the analyte has been bound, a temperature control sets the temperature to an appropriate temperature at which the captured analyte is released. | 06-17-2010 |
20100297733 | Systems And Methods For The Capture And Separation Of Microparticles - Systems and methods are provided for capturing and/or isolating target microparticles. In one aspect, a method for capturing target microparticles is disclosed. The method includes: forming a fluid including the target microparticles, non-target microparticles, and magnetic beads, the magnetic beads having a stronger affinity with the target microparticles than with the non-target microparticles; flowing the fluid through a multidirectional microchannel; and applying a magnetic field to the fluid while the fluid is flowing through at least a portion of the microchannel to effect capture of at least a portion of the target microparticles onto the magnetic beads. Such a method can further includes passing the fluid having exited from the microchannel through a separator while subjecting the fluid to a second magnetic field so as to isolate the target microparticles. In addition, devices and systems are disclosed for capturing and/or isolating target microparticles based on magnetic manipulation. | 11-25-2010 |
20120043203 | SENSORS FOR LONG-TERM AND CONTINUOUS MONITORING OF BIOCHEMICALS - The disclosed subject matter relates to a sensor or system for monitoring a target analyte by using a polymer solution that is capable of binding to the analyte. The sensor of the disclosed subject matter includes a viscosity-based sensor or a permittivity-based sensor. The viscosity-based sensor contains a semi-permeable membrane, a substrate, and a microchamber including a vibrational element. The permittivity-based sensor contains a semi-permeable membrane, a substrate, and a microchamber. The sensor discussed herein provides excellent reversibility and stability as highly desired for long-term analyte monitoring. | 02-23-2012 |
20140038301 | SELECTIVE CAPTURE AND RELEASE OF ANALYTES - The described subject matter includes techniques and components for minimally invasive, selective capture and release of analytes. An aptamer is selected for its binding affinity with a particular analyte(s). The aptamer is functionalized on a solid phase, for example, microbeads, polymer monolith, microfabricated solid phase, etc. The analyte is allowed to bind to the aptamer, for example, in a microchamber. Once the analyte has been bound, a temperature control sets the temperature to an appropriate temperature at which the captured analyte is released. | 02-06-2014 |
20140092935 | MEMS-BASED CALORIMETER, FABRICATION, AND USE THEREOF - MEMS-based calorimeter including two microchambers supported in a thin film substrate is provided. The thin film substrate includes a thermoelectric sensor configured to measure temperature differential between the two microchambers, and also includes a thermally stable and high strength polymeric diaphragm. Methods for fabricating the MEMS-based calorimeter, as well as methods of using the calorimeter to measure thermal properties of materials, such as biomolecules, or thermodynamic properties of chemical reactions or physical interactions, are also provided. | 04-03-2014 |
20140134607 | MEMS AFFINITY SENSOR FOR CONTINUOUS MONITORING OF ANALYTES - Techniques for monitoring a target analyte in a sample using a polymer capable of binding to the target analyte are disclosed. A microdevice useful for the disclosed techniques includes a semi-permeable membrane structure, a substrate, a first and second microchambers formed between the membrane structure and the substrate. The first microchamber can be adapted to receive a solution including the polymer, and the second microchamber can be adapted to receive a reference solution. Environmental target analyte can permeate the semi-permeable membrane structure and enters the first microchamber and the second microchamber. Based on the difference in a property associated with the polymer solution that is responsive to the target analyte-polymer binding, and the corresponding property associated with reference solution, the presence and/or concentration of the target analyte can be determined. | 05-15-2014 |
20140295424 | Isolation and Enrichment of Nucleic Acids on Microchip - Techniques for isolating, enriching, and/or amplifying target DNA molecules using MEMS-based microdevices are disclosed. The techniques can be used for detecting single nucleotide polymorphism, and for isolating and enriching desired DNA molecules, such as aptamers. | 10-02-2014 |
20140296095 | Spatially Selective Release of Aptamer-Captured Cells by Temperature Mediation - Methods and systems are provided for capturing and releasing target cells. The system includes a microdevice having a microchamber including surface-patterned aptamers capable of binding with the target cells. A sample including target cells is introduced to the microchamber, where the target cells bind to the aptamers at locally regulated temperatures. The captured target cells can be selectively released when the temperature of a region is changed to a second temperature. | 10-02-2014 |
Qin Lin, Ithaca, NY US
Patent application number | Description | Published |
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20100280201 | POLYMERS CONTAINING QUATERNIZED NITROGEN - The invention provides polymers, methods of preparing polymers, and compositions that include polymers, wherein said polymers include a plurality of two-carbon repeating units in a polymer chain, wherein one or more of the two-carbon repeating units of the polymer chain have tertiary amine or pyridine-containing substituents; and at least about 10% of the nitrogen atoms of the tertiary amine or pyridine-containing substituents are quaternized with alkyl groups or with an alkyl group that contains one or more ethylene glycol groups. The alkyl or ethoxylated alkyl groups can also be at least partially fluorinated. The polymers can be used to provide antimicrobial surfaces and antifouling coatings. | 11-04-2010 |
20110177343 | POLYMERS AND POLYMER COATINGS - The invention provides polymers, methods of preparing polymers, and compositions that include polymers, wherein said polymers include a plurality of two-carbon repeating units in a polymer chain, wherein one or more of the two-carbon repeating units of the polymer chain have a substituent that is covalently bonded to a semifluorinated alkyl ethoxy moiety, and the semifluorinated alkyl ethoxy moiety is attached to the polymer chain substituent through an ester, amide, ketone, carbamate, amine, or other suitable linking group. The polymers can be used to provide antifouling coatings. | 07-21-2011 |
Qinghuang Lin, Mt. Kisco, NY US
Shawn-Yu Lin, Niskayuna, NY US
Patent application number | Description | Published |
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20090126783 | USE OF VERTICAL ALIGNED CARBON NANOTUBE AS A SUPER DARK ABSORBER FOR PV, TPV, RADAR AND INFRARED ABSORBER APPLICATION - An optical absorber includes vertically aligned carbon nanotubes with an ultra-low reflectance less than 0.16% and an absorption efficiency greater than 99.84%. The index of refraction and the absorption constant are controlled by independently varying the nanotube diameter and nanotube spacing. The nanotubes are mostly double-walled. The density of the nanotube arrays is very low, around 0.015 g/cm | 05-21-2009 |
20110120554 | ULTRA-LOW REFLECTANCE BROADBAND OMNI-DIRECTIONAL ANTI-REFLECTION COATING - An anti-reflection coating has an average total reflectance of less than 10%, for example less than 5.9% such as from 4.9% to 5.9%, over a spectrum of wavelengths of 400-1100 nm and a range of angles of incidence of 0-90 degrees with respect to a surface normal of the anti-reflection coating. An anti-reflection coating has a total reflectance of less than 10%, for example less than 6% such as less than 4%, over an entire spectrum of wavelengths of 400-1600 nm and an entire range of angles of incidence of 0-70 degrees with respect to a surface normal of the anti-reflection coating. | 05-26-2011 |
20130161677 | INTEGRATED POLARIZED LIGHT EMITTING DIODE WITH A BUILT-IN ROTATOR - The invention is directed to an integrated polarized light emitting diode device that has a light emitting diode, a metal grating, an oxide layer, and a built-in photonic crystal rotator. Additional teachings include a method for making the integrated polarized light emitting diode, a method for improving the polarization selectivity and energy efficiency of a light emitting diode, and a method for rotating polarization of a light emitting diode. | 06-27-2013 |
20130221323 | EFFICIENT AND DIRECTED NANO-LIGHT EMITTING DIODE, AND METHOD FOR MAKING SAME - The invention relates to light-emitting devices, and related components, systems and methods. In one aspect, the present invention is related to light emitting diode (LED) light extraction efficiency. A non-limiting example, the application teaches a method for improving light emitting diode (LED) extraction efficiency, by providing a nano-rod light emitting diode; providing quantum wells; and reducing the size of said nano-rod LED laterally in the quantum-well plane (x and y), thereby improving LED extraction efficiency. | 08-29-2013 |
Tanya P. Lin, Bronx, NY US
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20110245185 | APO-2 ligand/trail formulations - The inventions include Apo2L/TRAIL formulations and methods of using such formulations. Lyophilized and crystal formulations of Apo-2L/TRAIL which are stable and have improved Apo2L/TRAIL trimer formation are provided. Methods of making Apo-2L/TRAIL formulations, as well as devices and kits containing such formulations are also provided. | 10-06-2011 |
Tseng-Hui Lin, Poughkeepsie, NY US
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20080288645 | COMPUTER PROGRAM PRODUCT USING TWO DIFFERENT PROGRAMS TO DETERMINE STATE OF A NETWORK NODE TO ELIMINATE MESSAGE RESPONSE DELAYS IN SYSTEM PROCESSING - The determination of node and/or adapter liveness in a distributed network data processing system is carried out via one messaging protocol that can be assisted by a second messaging protocol which is significantly less susceptible to delay, especially memory blocking delays encountered by daemons running on other nodes. The switching of protocols is accompanied by controlled grace periods for needed responses. This messaging protocol flexibility is also adapted for use as a mechanism for controlling the deliberate activities of node addition (birth) and node deletion (death). | 11-20-2008 |
20080291837 | COMPUTER PROGRAM PRODUCT FOR DETERMINATION OF REMOTE ADAPTER AND/OR NODE LIVENESS - The determination of node and/or adapter liveness in a distributed network data processing system is carried out via one messaging protocol that can be assisted by a second messaging protocol which is significantly less susceptible to delay, especially memory blocking delays encountered by daemons running on other nodes. The switching of protocols is accompanied by controlled grace periods for needed responses. This messaging protocol flexibility is also adapted for use as a mechanism for controlling the deliberate activities of node addition (birth) and node deletion (death). | 11-27-2008 |
Walt Lin, New York, NY US
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20110295828 | SYSTEMS AND METHODS FOR PROVIDING SEARCH RESULTS - A method includes generating search results in response to a user query, where at least one of the search results includes a group of links. The group of links may represent links to web pages within a same web site and may be identified based on at least one factor associated with the links. The method may also include providing the search results to the user. | 12-01-2011 |
Walton Lin, New York, NY US
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20100138425 | ENHANCED SEARCH RESULTS - A method includes receiving a search query from a user and generating search results based on the search query. The method may also include providing the search results and information identifying at least one of a telephone number or an address associated with a first one of the search results to the user. The method may further include providing a link to a map associated with at least the first search result to the user. | 06-03-2010 |
Walton W. Lin, New York, NY US
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20100114874 | PROVIDING SEARCH RESULTS - Methods, systems, and apparatus, including computer program products, for responding to a search query received from a user. From a web page a search result display object and template are identified. The search result display object specifies content available for display in a search result, and the template renders at least some of the content in the search result. The search result is presented responsive to a search query received from a user, where the search result is associated with the web page containing the search result display object and template. | 05-06-2010 |
Wayzen Lin, White Plains, NY US
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20080221715 | Method, system, and computer program product for managing controlled residential or non-residential environments - A control server, or similar central processor, manages the distribution of data (including audio and video), voice, and control signals among a plurality of devices connected via a wired and/or wireless communications network. The devices include audio/visual devices (such as, televisions, monitors, PDAs, notepads, notebooks, MP3, portable stereo, etc.) as well as household appliances (such as, lighting, ovens, alarm clocks, etc.). The control server supports video/audio serving, telephony, messaging, file sharing, internetworking, and security. A portable controller allows a user to access and control the network devices from any location within a controlled residential and/or non-residential environment, including its surrounding areas. The controllers are enhanced to support location-awareness and user-awareness functionality. | 09-11-2008 |
20100031295 | Method, system, and computer program product for managing controlled residential or non-residential environments - A control server, or similar central processor, manages the distribution of data (including audio and video), voice, and control signals among a plurality of devices connected via a wired and/or wireless communications network. The devices include audio/visual devices (such as, televisions, monitors, PDAs, notepads, notebooks, MP3, portable stereo, etc.) as well as household appliances (such as, lighting, ovens, alarm clocks, etc.). The control server supports video/audio serving, telephony, messaging, file sharing, internetworking, and security. A portable controller allows a user to access and control the network devices from any location within a controlled residential and/or non-residential environment, including its surrounding areas. The controllers are enhanced to support location-awareness and user-awareness functionality. | 02-04-2010 |
20120184300 | System and Method for Anticipating Wireless Signal loss to Provide Robust Location Based Services - A system and method for anticipating wireless signal loss and providing location based services in view of the anticipated wireless signal loss is disclosed. | 07-19-2012 |
Wei-Hao Lin, New York, NY US
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20120191630 | Updateable Predictive Analytical Modeling - Methods, systems, and apparatus, including computer programs encoded on one or more computer storage devices, for training and retraining predictive models. A series of training data sets for predictive modeling can be received, e.g., over a network from a client computing system. The training data included in the training data sets is different from initial training data that was used with multiple training functions to train multiple trained predictive models stored in a predictive model repository. The series of training data sets are used with multiple trained updateable predictive models obtained from the predictive model repository and multiple training functions to generate multiple retrained predictive models. An effectiveness score is generated for each of the retrained predictive models. A first trained predictive model is selected from among the trained predictive models included in the predictive model repository and the retrained predictive models based on their respective effectiveness scores. | 07-26-2012 |
20120191631 | Dynamic Predictive Modeling Platform - Methods, systems, and apparatus, including computer programs encoded on one or more computer storage devices, for training and retraining predictive models. A series of training data sets are received and added to a training data queue. In response to a first condition being satisfied, multiple retrained predictive models are generated using the training data queue, multiple updateable trained predictive models obtained from a repository of trained predictive models, and multiple training functions. In response to a second condition being satisfied, multiple new trained predictive models are generated using the training data queue, at least some training data stored in a training data repository and training functions. The new trained predictive models include static trained predictive models and updateable trained predictive models. The repository of trained predictive models is updated with at least some of the retrained predictive models and new trained predictive models. | 07-26-2012 |
20120284212 | Predictive Analytical Modeling Accuracy Assessment - A system includes a computer(s) coupled to a data storage device(s) that stores a training function repository and a predictive model repository that includes includes updateable trained predictive models each associated with an accuracy score. A series of training data sets are received, being training samples each having output data that corresponds to input data. The training data is different from initial training data that was used with training functions from the repository to train the predictive models initially. Upon receiving a first training data set included in the series and for each predictive model in the repository, the input data in the first training set is used to generate predictive output data that is compared to the output data. Based on the comparison and previous comparisons determined from the initial training data and from previously received training data sets, an updated accuracy score for each predictive model is determined. | 11-08-2012 |
20120284213 | Predictive Analytical Modeling Data Selection - A system includes a computer(s) coupled to a data storage device(s) that stores a training data repository and a predictive model repository. The training data repository includes retained data samples from initial training data and from previously received data sets. The predictive model repository includes at least one updateable trained predictive model that was trained with the initial training data and retrained with the previously received data sets. A new data set is received. A richness score is assigned to each of the data samples in the set and to the retained data samples that indicates how information rich a data sample is for determining accuracy of the trained predictive model. A set of test data is selected based on ranking by richness score the retained data samples and the new data set. The trained predictive model is accuracy tested using the test data and an accuracy score determined. | 11-08-2012 |
20120284600 | PREDICTIVE MODEL APPLICATION PROGRAMMING INTERFACE - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for utilizing predictive models from an application scripting language. | 11-08-2012 |
20130144819 | SCORE NORMALIZATION - Methods, systems, and apparatus, including computer programs encoded on computer storage media, for score normalization. One of the methods includes receiving initial training data, the initial training data comprising initial training records, each initial training record identifying input data as input and a category as output. The method includes generating a first trained predictive model using the initial training data and a training function. The method includes generating intermediate training records by inputting input data of the initial training records to a second trained predictive model, the second trained predictive model generated using the training function, each intermediate training record having a score. The method also includes generating a score normalization model using a score normalization training function and the intermediate training records. | 06-06-2013 |
20130346351 | ASSESSING ACCURACY OF TRAINED PREDICTIVE MODELS - A system includes a computer(s) coupled to a data storage device(s) that stores a training data repository and a predictive model repository. The training data repository includes retained data samples from initial training data and from previously received data sets. The predictive model repository includes at least one updateable trained predictive model that was trained with the initial training data and retrained with the previously received data sets. A new data set is received. A richness score is assigned to each of the data samples in the set and to the retained data samples that indicates how information rich a data sample is for determining accuracy of the trained predictive model. A set of test data is selected based on ranking by richness score the retained data samples and the new data set. The trained predictive model is accuracy tested using the test data and an accuracy score determined. | 12-26-2013 |
20140046880 | Dynamic Predictive Modeling Platform - Methods, systems, and apparatus, including computer programs encoded on one or more computer storage devices, for training and retraining predictive models. A series of training data sets are received and added to a training data queue. In response to a first condition being satisfied, multiple retrained predictive models are generated using the training data queue, multiple updateable trained predictive models obtained from a repository of trained predictive models, and multiple training functions. In response to a second condition being satisfied, multiple new trained predictive models are generated using the training data queue, at least some training data stored in a training data repository and training functions. The new trained predictive models include static trained predictive models and updateable trained predictive models. The repository of trained predictive models is updated with at least some of the retrained predictive models and new trained predictive models. | 02-13-2014 |
Wendy Lin, Niskayuna, NY US
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20120219424 | METHOD FOR MANUFACTURE OF AN INFUSED SPAR CAP USING A LOW VISCOSITY MATRIX MATERIAL - Embodiments of the present application generally provide for wind turbine blade spar caps comprising composite materials prepared using a low viscosity resin system and a high density fabric and methods for their manufacture. In particular embodiment, the low viscosity resin system has a viscosity in the range of about 1 to about 100 centipoises at a temperature in the range of about 0° C. to about 125° C. during the preparation of the composite material. By using low viscosity resin systems, composite materials have been prepared having a fiber volume fraction of greater than about 65% and a composite modulus of greater than 48000 MPa. | 08-30-2012 |
Wendy W. Lin, Niskayuna, NY US
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20090148300 | MODULAR WIND TURBINE BLADES WITH RESISTANCE HEATED BONDS - A blade for a wind turbine includes a first structural component; a second structural component; and at least one conductive bond for joining the first and second structural components. | 06-11-2009 |
20100132877 | VERTICAL MANUFACTURING OF COMPOSITE WIND TURBINE TOWER - A method of manufacturing a composite tower, includes at least partially filling a form with a curable resin; at least partially curing the resin in the form; raising the form partly over the at least partially cured resin; and at least partially filling the raised form with more curable resin applied against the cured resin. | 06-03-2010 |
Wen Y. Lin, New York, NY US
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20110270713 | METHODS AND SYSTEMS FOR FACILITATING THE PROVISION OF OPINIONS TO A SHOPPER FROM A PANEL OF PEERS - In accordance with one or more embodiments, a system determines an image, selects a panel of participants, and outputs the image to each of the participants of the panel of participants. Responses may be collected from the participants and an indication of the results may be output to a shopper. | 11-03-2011 |
20120278420 | Methods and Systems for Facilitating the Provision of Opinions to a Shopper from a Panel of Peers - In particular embodiments, a request for at least one opinion is received from one or more participants regarding an image of the user's appearance. An image of the user's appearance is determined, wherein the image showing how the user's appearance is changed by a product or changed after a service has been performed. The one or more participants from whom to obtain the at least one opinion are then selected. Each of the one or more participants may have a rating above a certain level. At least one response to the request is received from at least one of the one or more participants, each response comprising an opinion of the respective participant. An indication of at least one opinion of at least one participant from whom a response was received is then provided, the indication being based on the received responses regarding the user's appearance. | 11-01-2012 |
20120284085 | Methods and Systems for Facilitating the Provision of Opinions to a Shopper from a Panel of Peers - In particular embodiments, requests for opinions are received from shoppers. Each request is associated with an image of the respective shopper's appearance. A modified image of the shopper's appearance is determined in relation to a product or service, showing how the shopper's appearance is changed by the product or changed after the service has been performed. The request for opinions and the image of the shopper's appearance is sent to one or more participants. One or more opinions responsive to the request are received. Market intelligence information is determined in relation to the product or service, based on information associated with the requests for opinions. | 11-08-2012 |
Wuqin Lin, Briarcliff Manor, NY US
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20080263558 | METHOD AND APPARATUS FOR ON-DEMAND RESOURCE ALLOCATION AND JOB MANAGEMENT - The invention is a method and apparatus for on-demand resource planning for unified messaging services. In one embodiment, multiple clients are served by a single system, and existing system resources are allocated among all clients in a manner that optimizes system output and service provider profit without the need to increase system resources. In one embodiment, resource allocation and job scheduling are guided by individual service level agreements between the service provider and the clients that dictate minimum service levels that must be achieved by the system. Jobs are processed in a manner that at least meets the specified service levels, and the benefit or profit derived by the service provider is maximized by prioritizing incoming job requests within the parameters of the specified service levels while meeting the specified service levels. Thus, operation and hardware costs remain substantially unchanged, while system output and profit are maximized. | 10-23-2008 |
Xiaolan Lin, Flushing, NY US
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20120282305 | BIOLOGICAL SURFACTANTS FOR CONNECTION TO SILICONE-BASED MATERIALS AND MODULATING LEVELS OF IMMUNOLOGICALLY ACTIVE PROTEINS - Biological surfactants connected to surfaces of silicone-based materials are provided. Compositions of electrolytes and a biological surfactant are also provided. Methods for increasing the surface wettability of a silicone-based material by contacting the silicone-based material with a biological surfactant, methods for increasing evaporation from a silicone-based material by contacting a surface of the silicone-based material with a biological surfactant, methods for increasing levels of interleukin-8 during inflammation by contacting a cell with a biological surfactant, and methods for decreasing expression of a biological surfactant by contacting a cell with an siRNA are further provided. | 11-08-2012 |
Xin Lin, Rochester, NY US
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20110286990 | METHODS OF DIAGNOSING AND TREATING FIBROSIS - The present invention is directed to methods of diagnosing and treating a fibrotic condition in a mammalian subject. These methods involve measuring the levels of trimethylation at lysine residue 27 of histone-3 and/or measuring the expression levels of EZH2 or YY-1. Agents useful for treating fibrosis or a fibrotic condition are also disclosed. | 11-24-2011 |
Xinhua Lin, Plainview, NY US
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20090143566 | Growth Factor Analogs - The invention provides synthetic heparin-binding growth factor analogs of formulas I or II as given in the specification, having two peptide chains branched from a dipeptide branch moiety composed of at least one and preferably two trifunctional amino acid residues, which peptide chain or chains bind a heparin-binding growth factor receptor. The synthetic heparin-binding growth factor analogs are useful as pharmaceutical agents, soluble biologics or as surface coatings for medical devices. | 06-04-2009 |
20100267650 | Dual Chain Synthetic Heparin-Binding Growth Factor Analogs - The invention provides synthetic heparin-binding growth factor analogs having two peptide chains each branched from a branch moiety, such as trifunctional amino acid residues, the branch moieties separated by a first linker of from 3 to about 20 backbone atoms, which peptide chains bind a heparin-binding growth factor receptor and are covalently bound to a non-signaling peptide that includes a heparin-binding domain, preferably by a second linker, which may be a hydrophobic second linker. The synthetic heparin-binding growth factor analogs are useful as pharmaceutical agents, soluble biologics or as surface coatings for medical devices. | 10-21-2010 |
20100298218 | Single Branch Heparin-Binding Growth Factor Analogs - A heparin-binding growth factor (HBGF) analog having two substantially similar sequences (homodimeric sequences) branched from a single amino acid residue, where the sequences are analogs of a particular HBGF that binds to a heparin-binding growth factor receptor (HBGFR), or alternatively that bind to a HBGFR without being an analog of any particular HBGF. The homodimeric sequences may be derived from any portion of a HBGF. The synthetic HBGF analog may be an analog of a hormone, a cytokine, a lymphokine, a chemokine or an interleukin, and may bind to any HBGFR. Further provided are preparations for medical devices, pharmaceutical compositions and methods of using the same. | 11-25-2010 |
20120309694 | Dual Chain Synthetic Heparin-Binding Growth Factor Analogs - The invention provides synthetic heparin-binding growth factor analogs having two peptide chains each branched from a branch moiety, such as trifunctional amino acid residues, the branch moieties separated by a first linker of from 3 to about 20 backbone atoms, which peptide chains bind a heparin-binding growth factor receptor and are covalently bound to a non-signaling peptide that includes a heparin-binding domain, preferably by a second linker, which may be a hydrophobic second linker. The synthetic heparin-binding growth factor analogs are useful as pharmaceutical agents, soluble biologics or as surface coatings for medical devices. | 12-06-2012 |
20150030656 | Composition and Method for Delivery of BMP-2 Amplifier/Co-Activator for Enhancement of Osteogenesis - A composition comprising a synthetic growth factor analogue comprising a non-growth factor heparin binding region, a linker and a sequence that binds specifically to a cell surface receptor and an osteoconductive material where the synthetic growth factor analogue is attached to and can be released from the osteoconductive material and is an amplifier/co-activator of osteoinduction. | 01-29-2015 |
Yang-I Lin, Tappan, NY US
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20080312203 | Bicyclic 6-Alkylidene-Penems as Beta-Lactamase Inhibitors - The present invention provides a compound of formula I | 12-18-2008 |
Yea-Sen Lin, Lagrangeville, NY US
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20090241085 | SYSTEM AND METHOD FOR IMPLEMENTING OPTICAL RULE CHECKING TO IDENTIFY AND QUANTIFY CORNER ROUNDING ERRORS - A method for implementing optical rule checking to identify and quantify corner rounding errors includes receiving corner rounding data based on established ground rules; determining a simulated shape for a semiconductor device feature produced on a wafer, the simulated shape based on a designed shape for the semiconductor device feature; selecting a corner feature associated with the designed shape, and drawing one or more triangles at the selected corner feature. For each triangle, the presence or absence of an intersection between the triangle and the simulated shape is determined, wherein a degree of corner rounding is determined by a pair of successively sized triangles for which one of the pair intersects with the simulated shape and the other does not; and comparing the determined corner rounding with the corner rounding data for the designed shape to determine whether the simulated shape results in a rule violation. | 09-24-2009 |
Ying-Wei Lin, Penfield, NY US
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20080217416 | MAGNETIC WATERMARK FOR TEXT DOCUMENTS - The present disclosure is directed to a method and apparatus for applying magnetic ink character recognition (MICR) technology to enable the embedding of coded information within text characters of a document. | 09-11-2008 |
20110032575 | METHOD FOR ESTIMATION OF IMAGE DEFOCUS AND DEFOCUS RESTORATION - A method for determining local defocus distance in a scanned image of a non-planar original object is provided comprising scanning at least a portion of the non-planar original object to produce first scanned image data at a first focal plane and scanning same the at least a portion of the non-planar original object to produce at least second scanned image data at a second focal plane. The first scanned image data is different from the second scanned image data wherein a distance between the first focal plane and the second focal plane is a predetermined quantity. The method further comprises estimating an out-of-focus distance of the object from the first and the second scanned image data. | 02-10-2011 |
Yixin Lin, Stormvile, NY US
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20090233268 | DETECTION OF BIOMARKERS AND BIOMARKER COMPLEXES - The invention features methods and devices for the detection of biomarker complexes and their components and for the sequential detection of multiple epitopes of a biomarker. The invention also features methods for diagnosing disease and evaluating the efficacy of treatment of a subject with a disease. | 09-17-2009 |
Yong Lin, Brooklyn, NY US
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20110318741 | BIOMARKERS FOR THE TREATMENT OF PSORIASIS - Provided herein are the biomarkers for predicting or monitoring the efficacy of a treatment for psoriasis. The use of certain cell markers and mRNA levels as biomarkers to predict whether a psoriasis treatment is likely to be successful is also provided. Further, the expression of these genes or cell markers can be used to monitor progress of treatment effectiveness and patient compliance in psoriasis patients who are receiving treatment. | 12-29-2011 |
Yun-Chich "jack" Lin, Norwich, NY US
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20110025243 | ROBUST ROTATIONAL POSITION ALIGNMENT USING A RELATIVE POSITION ENCODER - A robust method for detecting a relative position of a feedback device, such as an encoder or resolver, coupled to a shaft, such as a motor shaft, is provided. To detect the relative position, electrical commands are issued in an open loop mode to spin the motor shaft an amount greater than the apparent rotational angle between two consecutive markers of the position feedback device, such that the net mechanical rotation is equal to or greater than the total rotational angle between two consecutive markers. | 02-03-2011 |
Yunqing Lin, New York, NY US
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20100247462 | SYNTHESIS OF RESVERATROL-BASED NATURAL PRODUCTS - Processes for synthesizing resveratrol-based oligomers are provided. In addition, resveratrol-based oligomer compounds free of plant extract are provided. | 09-30-2010 |
Yunting Lin, White Plains, NY US
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20130030874 | System and Method of Measuring Service Time Intervals - A system and method of measuring order fulfillment times for fast food incorporate video cameras to generate sequences of images of the fulfillment process. Time intervals to fulfillment are determined and stored. Average time intervals to fulfillment, based on multiple fulfillment records, are automatically generated. | 01-31-2013 |
Yun-Ting Lin, White Plains, NY US
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20100214413 | System and Method to Detect Tampering at ATM Machines - A system and method of detecting tampering at an automatic teller machine includes detecting start and end indicators of a transaction. A representation of a scene at the teller machine, prior to the start of the transaction can be compared to a representation of the scene after the end of the transaction. Variations therebetween can indicate tampering at the machine. | 08-26-2010 |
Yun-Ting Lin, Ossining, NY US
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20080226127 | LINKING TRACKED OBJECTS THAT UNDERGO TEMPORARY OCCLUSION - A method and system is configured to characterize regions of an environment by the likelihoods of transition of a target from each region to another. The likelihoods of transition between regions is preferably used in combination with conventional object-tracking algorithms to determine the likelihood that a newly-appearing object in a scene corresponds to a recently-disappeared target. The likelihoods of transition may be predefined based on the particular environment, or may be determined based on prior appearances and disappearances in the environment, or a combination of both. The likelihoods of transition may also vary as a function of the time of day, day of the week, and other factors that may affect the likelihoods of transitions between regions in the particular surveillance environment. | 09-18-2008 |
Yvonne Lin, New York City, NY US
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20120311831 | FASTENING ARRANGEMENT - A fastening arrangement comprises a first fastening member connected to a first strap and a second fastening member connected to a second strap. The first fastening member includes a first surface comprising at least one first interlocking member. The second fastening member includes a channel positioned between a second surface and a biasing member. The channel is configured to receive the first fastening member with the first surface facing the second surface. The second surface includes at least one second interlocking member configured to engage the first interlocking member in a manner that blocks the first interlocking member from moving relative to the second interlocking member in at least one direction. The biasing member is configured to urge the first interlocking member into engagement with the second interlocking member when the first fastening member is inserted into the channel of the second fastening member. | 12-13-2012 |
20140345095 | Fastening Arrangement With Interlocking Members - A fastening arrangement comprises a first fastening member connected to a first strap and a second fastening member connected to a second strap. The first fastening member includes a first surface comprising at least one first interlocking member. The second fastening member includes a channel positioned between a second surface and a biasing member. The channel is configured to receive the first fastening member with the first surface facing the second surface. The second surface includes at least one second interlocking member configured to engage the first interlocking member in a manner that blocks the first interlocking member from moving relative to the second interlocking member in at least one direction. The biasing member is configured to urge the first interlocking member into engagement with the second interlocking member when the first fastening member is inserted into the channel of the second fastening member. | 11-27-2014 |
Yvonne Lin, New York, NY US
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20090038092 | HAND HELD SPONGE IMPLEMENT - The present invention is directed to a cleaning implement for use in household cleaning applications. In accordance with the present invention, the cleaning implement comprises a base, a handle extending from said base and a cleaning pad, which is attached to the base. The cleaning pad of the present invention contains two separate cleaning surfaces that optionally can act on two separate planes, simultaneously. In one embodiment, the cleaning pad is removable and disposable. | 02-12-2009 |
Zhiqing Lin, Loudonville, NY US
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20090005498 | Curable silyl-containing polymer composition containing paint adhesion additive - A curable composition comprising a hydrolysable silyl-containing polymer and a silicone-containing paint adhesion additive that provide curable silyl-containing polymer composition which has improved adhesion of coatings, paints, adhesives, and other surface treatments thereto. | 01-01-2009 |