Patent application number | Description | Published |
20080217712 | Apparatus and method for forming optical black pixels with uniformly low dark current - An apparatus and method for forming optical black pixels having uniformly low dark current. Optical Black opacity is increased without having to increase Ti/TiN layer thickness. A hybrid approach is utilized combining a Ti/TiN OB layer in conjunction with in-pixel metal stubs that further occlude the focal radius of each pixel's incoming light beam. Additional metal layers can be used to increase the opacity into the infrared region. | 09-11-2008 |
20080218608 | Apparatus and method for reducing edge effect in an image sensor - A method and apparatus for forming dummy pixels exhibiting electrical characteristics virtually identical to the clear pixels of the imaging array. Arrays of such dummy pixels are used to form regions that isolate the main imaging array and sub-arrays of optical black pixels while preventing edge effects. The dummy pixels are preferably clear but can also be covered with optical black. By setting quiescent operation in soft reset, the dummy pixels exhibit the diode ideality and R | 09-11-2008 |
20080218615 | Apparatus and method for stabilizing image sensor black level - A black clamp stabilization circuit for an image sensor utilizes a mixed-signal SoC block comprising sub-blocks to dynamically and precisely adjust the black level based on comparison to a reference black level. The black level adjustments include a first level regulation using digital control of an analog signal in a feedback loop that includes a programmable gain amplifier and high-resolution A/D converter. By applying the black clamping in the analog domain, dynamic range is extended. Additional black level regulation is subsequently performed in the digital domain to differentially eliminate line noise and column noise generated within the imaging System-on-Chip. By providing information between the sub-blocks, the algorithms can converge more quickly. The technique enables multiple signal paths to separately handle individual colors and to increase imaging data throughput. | 09-11-2008 |
20080265354 | Image sensor - An image sensor, in which, a planarized layer is formed on a semiconductor substrate including a pixel array region, an optical black region, and a logic region to cover a photo sensing unit array in the pixel array region, a patterned metal layer is formed on the planarized layer corresponding to the pixel array region and the logic region, but not the optical black region. An optical black layer is formed in the optical black region after a passivation layer is formed and before a color filter array is formed at a temperature less than about 400° C., and preferably contains metal material. | 10-30-2008 |
20080316335 | Method and apparatus for minimizing noise pickup in image sensors - A method and apparatus for minimizing noise pickup in iSoC sensors using an improved Analog Capacitor Memory (ACM) design and optimized timing methods that together prevent direct connection of the electrical grounds between the low-speed signal processing circuit and high-speed signal processing circuit of an imaging System-on-Chip sensor. The ACM includes a two-terminal capacitor and two pairs of terminals. Each pair of terminals is connected via switches to separate circuits. The switches are controlled to isolate one side of the ACM from the other, thereby reducing the noise pickup between the circuits. | 12-25-2008 |
20080316342 | ACCURATE GAIN IMPLEMENTATION IN CMOS SENSOR - The claimed subject matter provides systems and/or methods that facilitate combining analog and digital gain for utilization with CMOS sensor imagers. The analog gain can provide coarse gain steps and the digital gain can provide finer gain steps between adjacent coarse analog gain values. Further, since analog gain can suffer from low precision, dispersion, etc., on-chip calibration can be implemented to calibrate the analog and digital gain. For example, a digital amplifier can be calibrated to compensate for differences between actual and nominal analog gains associated with one or more analog amplifiers. | 12-25-2008 |
20090141156 | REFERENCE VOLTAGE GENERATION IN IMAGING SENSORS - The claimed subject matter provides systems and/or methods that facilitate generating and/or maintaining low noise reference voltages for CMOS imaging System-on-Chip (iSoC) sensors. A primary reference voltage can be generated utilizing a low noise bandgap. Further, the primary reference voltage can be filtered via a low pass filter. The filtered, primary reference voltage can thereafter be distributed to a plurality of isolated domains. Each of the isolated domains can generate an independent set of reference voltages based upon the filtered, primary reference voltage. Moreover, subsets of these reference voltages can be employed by programmable digital to analog converters (DACs). Each of the reference voltages can be isolated from switching noise and/or clock glitches generated within each domain. Further, each DAC output can be buffered to have adequately low impedance with appropriate drive capability and requisite signal swing. | 06-04-2009 |
20090278951 | Apparatus and methods for multi-sensor synchronization - Apparatus and methods for synchronizing a plurality of image sensors in a video camera system. In one embodiment, a method includes generating a video sync signal, and resetting at least one internal clock divider in each image sensor in synchronization with the video sync signal at the beginning of each video frame. Another embodiment of a method of synchronizing a plurality of image sensors in a video camera system includes detecting a phase state of a signal of at least one internal clock divider in each sensor, wherein the phase state is relative to a system sync signal, and selecting a video output signal for each sensor based on the detected phase state of the at least one internal divider. In a third embodiment, the method includes asserting an asynchronous reset signal, stopping the system clocks in the system, de-asserting the asynchronous reset signal, while the system clocks are stopped, and restarting the system clocks. Each method may be used individually, or the methods can be combined in any combination. A video camera apparatus is also described. | 11-12-2009 |
20100149390 | STAGGERED RESET IN CMOS DIGITAL SENSOR DEVICE - Systems and methods are provided that facilitate staggering resets of rows of pixels in a CMOS imaging iSoC sensor. Reset signals and select signals can be provided to pixels in a pixel array in a coordinated manner when employing full frame integration or sub-frame integration. Further, reset signals and select signals can be transferred to a first row of pixels, while reset signals can be transferred to a second row of pixels during a unique readout time interval when utilizing sub-frame integration. Within the unique readout time interval, reset signals can be transferred to the first row of pixels during a first time period, while reset signals can be transferred to the second row of pixels during a second time period, where the first and second time periods are non-overlapping. Accordingly, cross-talk between rows of pixels during reset can be mitigated, which leads to enhanced uniformity. | 06-17-2010 |
20110063483 | Image sensor with wide dynamic range - An image sensor, system and method that alternates sub-sets of pixels with long exposure times and pixels with short exposure times on the same sensor to provide a sensor having improved Wide Dynamic Range (WDR). The sub-sets of pixels are reset at different time intervals after being read, which causes the respective integration times to vary. By combining information contained in the both the short and long integration pixels, the dynamic range of the sensor is improved. | 03-17-2011 |
20110090374 | SUB-FRAME TAPERED RESET - Systems and methods are provided that facilitate employing a plurality of independent reset buses for a column of pixels in a pixel array of a CMOS sensor imager. Utilization of the plurality of independent reset buses for the column of pixels can enable independent reset to be effectuated when employing sub-frame integration. For example, rows to be read and reset during a given readout time interval can be selected based upon one or more criteria. Further, each of the rows selected during the given readout time interval can be associated with a respective distinct reset bus. By leveraging the plurality of independent reset buses, uniformity in pixel operation can be maintained whether operating in full frame integration mode or sub-frame integration mode. Thus, noise resultant from changing between integration modes can be mitigated by using the plurality of independent reset buses. | 04-21-2011 |