Patent application number | Description | Published |
20090251181 | Method and apparatus for tuning phase of clock signal - A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result. | 10-08-2009 |
20100148819 | Majority voter circuits and semiconductor device including the same - A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority. | 06-17-2010 |
20110158030 | METHOD AND APPARATUS FOR TUNING PHASE OF CLOCK SIGNAL - A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result. | 06-30-2011 |
Patent application number | Description | Published |
20140068159 | MEMORY CONTROLLER, ELECTRONIC DEVICE HAVING THE SAME AND METHOD FOR OPERATING THE SAME - A memory controller includes first and second interfaces, a microprocessor, a register and a plane control unit. The first interface is configured to receive a first command and plane logic information of a plurality of planes in a memory device from a host. The microprocessor is coupled to the first interface, and configured to decode the first command to provide a corresponding second command, and to map the plane logic information to be suited to a non-volatile memory device. The register is configured to queue the second command and the mapped plane logic information. The second interface is configured to provide the second command and the queued plane logic information to the memory device. The plane control unit is configured to control multiple planes corresponding to portions of the queued plane logic information to perform concurrently the second command in the non-volatile memory device. | 03-06-2014 |
20140068161 | MEMORY CONTROLLER, AND ELECTRONIC DEVICE HAVING THE SAME AND METHOD FOR OPERATING THE SAME - A memory controller includes a first interface and a microprocessor. The first interface is configured to receive a first command, a first address, an address state separation command, and a second address, the first address corresponding to the first command, and the address state separation command separating the first and second addresses from each other. The microprocessor is configured to decode the first command, map the first address to a non-volatile memory device, execute the first command relative to the first address mapped to the non-volatile memory device, and determine a relation between the first address and the second address. The microprocessor is further configured to selectively execute the second command relative to the second address mapped to the non-volatile memory device concurrently with the first command based on the relation between the first address and the second address. | 03-06-2014 |
Patent application number | Description | Published |
20130127019 | SEMICONDUCTOR DEVICES INCLUDING THROUGH SILICON VIA ELECTRODES AND METHODS OF FABRICATING THE SAME - A semiconductor device may include a semiconductor substrate, a through via electrode, and a buffer. The through via electrode may extend through a thickness of the semiconductor substrate with the through via electrode surrounding an inner portion of the semiconductor substrate so that the inner portion of the semiconductor substrate may thus be isolated from the outer portion of the semiconductor substrate. The buffer may be in the inner portion of the semiconductor substrate with the through via electrode surrounding and spaced apart from the buffer. Related methods are also discussed. | 05-23-2013 |
20130200526 | SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES AND METHODS FOR FABRICATING THE SAME - Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode. | 08-08-2013 |
20140035144 | Semiconductor Devices Having Through Electrodes and Methods of Fabricating the Same - Provided are semiconductor devices having through electrodes and methods of fabricating the same. The method includes providing a substrate including top and bottom surfaces facing each other, forming a hole and a gap extending from the top surface of the substrate toward the bottom surface of the substrate, the gap surrounding the hole and being shallower than the hole, filling the hole with an insulating material, forming a metal interconnection line on the top surface of the substrate on the insulating material, recessing the bottom surface of the substrate to expose the insulating material, removing the insulating material to expose the metal interconnection line via the hole, filling the hole with a conductive material to form a through electrode connected to the metal interconnection line, recessing the bottom surface of the substrate again to expose the gap, and forming a lower insulating layer on the bottom surface of the substrate. | 02-06-2014 |
20140084473 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Provided are semiconductor devices and methods of fabricating the same. The device may include a substrate including a first surface and a second surface opposing each other, a through-silicon-via (TSV) electrode provided in a via hole that may be formed to penetrate the substrate, and an integrated circuit provided adjacent to the through electrode on the first surface. The through electrode includes a metal layer filling a portion of the via hole and an alloy layer filling a remaining portion of the via hole. The alloy layer contains at least two metallic elements, one of which may be the same as that contained in the metal layer, and the other of which may be different from that contained in the metal layer. | 03-27-2014 |
20150137326 | SEMICONDUCTOR DEVICES HAVING THROUGH-ELECTRODES AND METHODS FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer. | 05-21-2015 |
20150332967 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Provided are semiconductor devices and methods of fabricating the same. The device may include a substrate including a first surface and a second surface opposing each other, a through-silicon-via (TSV) electrode provided in a via hole that may be formed to penetrate the substrate, and an integrated circuit provided adjacent to the through electrode on the first surface. The through electrode includes a metal layer filling a portion of the via hole and an alloy layer filling a remaining portion of the via hole. The alloy layer contains at least two metallic elements, one of which may be the same as that contained in the metal layer, and the other of which may be different from that contained in the metal layer. | 11-19-2015 |
20160133545 | SEMICONDUCTOR DEVICES HAVING THROUGH-ELECTRODES - Semiconductor devices having through-electrodes are provided. The semiconductor devices may include a substrate, a through-electrode penetrating vertically through the substrate, a circuit layer on the substrate and metal lines in the circuit layer. The metal lines may include two first metals on opposing edges of a top surface of the through-electrode and second metals above the top surface of the through-electrode. At least some of the second metals may not vertically overlap the two first metals. | 05-12-2016 |
Patent application number | Description | Published |
20130119547 | INTEGRATED CIRCUIT DEVICE INCLUDING THROUGH-SILICON VIA STRUCTURE HAVING OFFSET INTERFACE - An integrated circuit device includes a substrate through which a first through-hole extends, and an interlayer insulating film on the substrate, the interlayer insulating film having a second through-hole communicating with the first through-hole. A Through-Silicon Via (TSV) structure is provided in the first through-hole and the second through-hole. The TSV structure extends to pass through the substrate and the interlayer insulating film. The TSV structure comprises a first through-electrode portion having a top surface located in the first through-hole, and a second through-electrode portion having a bottom surface contacting with the top surface of the first through-electrode portion and extending from the bottom surface to at least the second through-hole. Related fabrication methods are also described. | 05-16-2013 |
20130140697 | Electrode Connecting Structures Containing Copper - Provided are electrode-connecting structures or semiconductor devices, including a lower device including a lower substrate, a lower insulating layer formed on the lower substrate, and a lower electrode structure formed in the lower insulating layer, wherein the lower electrode structure includes a lower electrode barrier layer and a lower metal electrode formed on the lower electrode barrier layer, and an upper device including an upper substrate, an upper insulating layer formed under the upper substrate, and an upper electrode structure formed in the upper insulating layer, wherein the upper electrode structure includes an upper electrode barrier layer extending from the inside of the upper insulating layer under a bottom surface thereof and an upper metal electrode formed on the upper electrode barrier layer. The lower metal electrode is in direct contact with the upper metal electrode. | 06-06-2013 |
20140070426 | INTEGRATED CIRCUIT DEVICES INCLUDING A VIA STRUCTURE AND METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES INCLUDING A VIA STRUCTURE - Integrated circuit devices are provided. The integrated circuit devices may include a via structure including a conductive plug, a conductive barrier layer spaced apart from the conductive plug, and an insulating layer between the conductive plug and conductive barrier layer. Related methods of forming integrated circuit devices are also provided. | 03-13-2014 |
20150028450 | INTEGRATED CIRCUIT DEVICE INCLUDING THROUGH-SILICON VIA STRUCTURE AND DECOUPLING CAPACITOR AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device is provided which includes a through-silicon via (TSV) structure and one or more decoupling capacitors, along with a method of manufacturing the same. The integrated circuit device may include a semiconductor structure including a semiconductor substrate, a TSV structure passing through the semiconductor substrate, and a decoupling capacitor formed in the semiconductor substrate and connected to the TSV structure. The TSV structure and the one or more decoupling capacitors may be substantially simultaneously formed. A plurality of decoupling capacitors may be disposed within a keep out zone (KOZ) of the TSV structure. The plurality of decoupling capacitors may have the same or different widths and/or depths. An isopotential conductive layer may be formed to reduce or eliminate a potential difference between different parts of the TSV structure. | 01-29-2015 |
20150028494 | INTEGRATED CIRCUIT DEVICE HAVING THROUGH-SILICON-VIA STRUCTURE AND METHOD OF MANUFACTURING THE INTEGRATED CIRCUIT DEVICE - Provided is an integrated circuit device including a through-silicon-via (TSV) structure and a method of manufacturing the integrated circuit device. The integrated circuit device includes a semiconductor structure including a substrate and an interlayer insulating film, a TSV structure passing through the substrate and the interlayer insulating film, a via insulating film substantially surrounding the TSV structure, and an insulating spacer disposed between the interlayer insulating film and the via insulating film. | 01-29-2015 |
20150102395 | SEMICONDUCTOR DEVICE INCLUDING DECOUPLING CAPACITOR AND METHOD OF FORMING THE SAME - An integrated circuit device includes a semiconductor substrate having first and second semiconductor regions therein, a gate trench in the first semiconductor region and a gate electrode in the gate trench. The gate electrode has an upper surface below a surface of the semiconductor substrate. A semiconductor well region is provided in the second semiconductor region. A capacitor trench extends in the semiconductor well region and an upper capacitor electrode extends in the capacitor trench. An electrical interconnect (e.g., conductive plug) is provided, which is electrically connected to the upper capacitor electrode at an interface therebetween. This interface has an upper surface below the surface of the semiconductor substrate. | 04-16-2015 |
20150102497 | Integrated Circuit Devices Including a Through-Silicon Via Structure and Methods of Fabricating the Same - Integrated circuit (IC) devices are provided including: a first multi-layer wiring structure including a plurality of first wiring layers in a first region of a substrate at different levels and spaced apart from one another, and a plurality of first contact plugs between the plurality of first wiring layers and connected to the plurality of first wiring layers; a through-silicon via (TSV) landing pad including a first pad layer in a second region of the substrate at a same level as that of at least one first wiring layer from among the plurality of first wiring layers, and a second pad layer at a same level as that of at least one first contact plug from among the plurality of first contact plugs and contacts the first pad layer; a second multi-layer wiring structure on the TSV landing pad; and a TSV structure that passes through the substrate and is connected to the second multi-layer wiring structure through the TSV landing pad. | 04-16-2015 |
20150108605 | Integrated Circuit Devices Having Through Silicon Via Structures and Methods of Manufacturing the Same - An integrated circuit device is provided. The integrated circuit device includes: a capacitor including an electrode formed in a first area on a substrate; a through-silicon-via (TSV) landing pad formed in a second area on the substrate, the TSV landing pad including the same material as the electrode; a multi-layered interconnection structure formed on the capacitor and the TSV landing pad; and a TSV structure passing through the substrate, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad. | 04-23-2015 |
20150129978 | SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD FOR FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE - A semiconductor integrated circuit device includes a TSV (Through Silicon Via) extending through a substrate, a first well in the substrate adjacent a first surface of the substrate, a gate of an active device on the first well, a charging protection well, and a charging protection gate on the charging protection well. The charging protection well is disposed in the substrate adjacent the first surface of the substrate, is interposed between the TSV hole and the first well, and surrounds the TSV hole. The charging protection gate prevents the gate of the active device from being damaged when the TSV is formed especially when using a plasma etch process to form a TSV hole in the substrate. | 05-14-2015 |
20160086874 | SEMICONDUCTOR DEVICES INCLUDING THROUGH-SILICON-VIAS AND METHODS OF MANUFACTURING THE SAME AND SEMICONDUCTOR PACKAGES INCLUDING THE SEMICONDUCTOR DEVICES - A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure. | 03-24-2016 |
Patent application number | Description | Published |
20120189944 | SOLID ELECTROLYTE FOR SOLID OXIDE FUEL CELL, AND SOLID OXIDE FUEL CELL INCLUDING THE SOLID ELECTROLYTE - A solid electrolyte for a solid oxide fuel cell, the solid electrolyte including: a zirconia layer; and a hybrid layer including a hybrid phase according to Formula 1: | 07-26-2012 |
20120308915 | CATHODE MATERIAL FOR FUEL CELL, CATHODE INCLUDING THE CATHODE MATERIAL, SOLID OXIDE FUEL CELL INCLUDING THE CATHODE - A cathode material for a fuel cell, the cathode material including a first metal oxide having a perovskite structure; and a second metal oxide having a spinel structure. | 12-06-2012 |
20130295484 | MATERIAL FOR SOLID OXIDE FUEL CELL, CATHODE FOR SOLID OXIDE FUEL CELL AND SOLID OXIDE FUEL CELL INCLUDING THE SAME, AND METHOD OF MANUFACTURE THEREOF - A material for a solid oxide fuel cell, the material including: a first metal oxide represented by Formula 1 and having a perovskite crystal structure; a second metal oxide having an electronic conductivity which is greater than an electrical conductivity of the first metal oxide, a thermal expansion coefficient which is less than a thermal expansion coefficient of the first metal oxide, and having a perovskite crystal structure; and a third metal oxide having a fluorite crystal structure: | 11-07-2013 |
20130295489 | ANODE SUPPORT FOR SOLID OXIDE FUEL CELL, METHOD OF MANUFACTURING THE SAME, AND SOLID OXIDE FUEL CELL INCLUDING THE SAME - An anode support for a solid oxide fuel cell, the anode support having a bimodal pore distribution comprising a first pore having an average pore size of about 3 micrometers to about 10 micrometers, and a second pore having an average pore size of about 0.1 micrometer to about 1 micrometer. | 11-07-2013 |
20140308177 | HYDROGEN SEPARATION MEMBRANE AND DEVICE INCLUDING HYDROGEN SEPARATION MEMBRANE - A hydrogen separation membrane including: a metal layer including the at least one Group 5 element; and a transition metal catalyst layer on the metal layer, the transition metal catalyst layer including at least one transition metal and at least one of phosphorus (P) or boron (B). | 10-16-2014 |
20150344305 | CONDUCTIVE MATERIAL AND ELECTRICAL DEVICE INCLUDING THE SAME - A conductive material including a first element selected from a transition metal, a platinum-group element, a rare earth element, and a combination thereof, a second element having an atomic radius which is 10 percent less than to 10 percent greater than an atomic radius of the first element, and a chalcogen element, wherein the conductive material has a layered crystal structure. | 12-03-2015 |
20150344307 | ELECTRICALLY CONDUCTIVE THIN FILMS - An electrically conductive film including a compound represented by Chemical Formula 1 and having a layered crystal structure: | 12-03-2015 |
20150360944 | ELECTRICALLY CONDUCTIVE THIN FILMS - An electrically conductive thin film including a compound represented by Chemical Formula 1 or Chemical Formula 2 and having a layered crystal structure: | 12-17-2015 |
20150380122 | ELECTRICALLY CONDUCTIVE THIN FILMS - An electrically conductive thin film including a compound represented by Chemical Formula 1 and having a layered crystal structure: | 12-31-2015 |
Patent application number | Description | Published |
20080203507 | Image sensors for zoom lenses and fabricating methods thereof - An image sensor includes a semiconductor substrate on which a plurality of photo diodes are formed. A plurality of interlayer dielectrics are formed above the semiconductor substrate, and a plurality of metal lines are formed on each of the interlayer dielectrics. A plurality of micro lenses are formed above the uppermost one of the interlayer dielectrics. The light passing through the zoom lenses is incident on the respective micro lenses. The plurality metal lines formed on at least one of the plurality of interlayer dielectrics have the same width. | 08-28-2008 |
20090072281 | CMOS image sensor layout capable of removing difference between Gr and Gb sensitivities and method of laying out the CMOS image sensor - Provided is a layout of a CMOS image sensor having an asymmetrical pixel structure in which a plurality of photodiodes may share a transistor block. The layout may include a first region in which a plurality of photodiodes are arranged asymmetrically on a semiconductor substrate, a second region including a metal shield layer arranged on an upper surface of the first region, and a third region arranged on an upper surface of the second region. The metal shield layer may be arranged asymmetrically according to the layout of the photodiodes. | 03-19-2009 |
20090200627 | Image sensor with high conversion efficiency - An image sensor includes a photoelectric converter, a reflector, and a charge carrier guiding region. The reflector is disposed under the photoelectric converter, and the charge carrier guiding region is disposed between the photoelectric converter and the reflector. The reflector reflects incident light passed by the photoelectric converter back through the photoelectric converter for increasing photoelectric conversion efficiency and reduced crosstalk. The charge carrier guiding region dissipates undesired charge carriers for further increasing photoelectric conversion efficiency. | 08-13-2009 |
20090219266 | Pixel circuit arrays - A pixel circuit array may include pixel circuits and/or a global reset transistor that has a first end connected to a second end of a reset transistor and is turned on or off in response a global reset signal. Each pixel circuit may include: a transmission transistor that may receive and/or transmit photocharges through ends of the transmission transistor in response to a transmission control signal; the reset transistor that may have a first end connected to the second end of the transmission transistor and may be turned on or off in response a reset control signal; a source-follower transistor that may receive a signal from the second end of the reset transistor and/or may be turned on or off in response the received signal; and/or a selection transistor that may be connected to the source-follower transistor and/or may be turned on or off in response a selection control signal. | 09-03-2009 |
Patent application number | Description | Published |
20130113233 | SEAT APPARATUS FOR VEHICLE - A seat apparatus for a vehicle, in which a seat back may be foldable toward a seat cushion of a seat, may include a storage space provided at the bottom of a floor and storing the seat to provide a luggage space in the vehicle, a link member pivotally connected between a cushion link of the seat cushion and the storage space such that the seat may be foldable to be stored in the storage space, a locking device provided on the seat back to maintain an unfolded or folded state of the seat back, and an elastic member provided on the link member to pop up the cushion link and the seat back out of the storage space when the seat back may be unfolded. | 05-09-2013 |
20130147224 | STORING APPARATUS OF REAR SEAT FOR MULTI PURPOSE VEHICLE - A storing apparatus of a rearmost seat for a multipurpose vehicle may include a storage space provided under a floor panel, wherein the rearmost seat may be selectively stored in the storage space, and wherein the rearmost sear includes a plurality of links disposed to pivotally connect the rearmost seat with the storage space to implement a storage mode in which the seat may be moved down and received in the storage space and a sitting mode in which the seat may be drawn upward out of the storage space. | 06-13-2013 |
20140239662 | STORAGE APPARATUS FOR SEAT OF VEHICLE - A storage apparatus for a seat of a vehicle, in which the seat is stored in a storage space formed therebelow, so that it is possible to secure a wider luggage space as compare with the related art and reduce unit cost without using a separate slide rail. In addition, the storage apparatus variously uses the space of a back seat when shifted between a passenger space (seating mode) and a luggage space (luggage mode) of the multi-functional back seat, which is vertically movable and foldable. | 08-28-2014 |
20140339848 | HEADREST APPARATUS FOR MULTI-PURPOSE VEHICLE - A headrest apparatus for an MPV includes a headrest that can be automatically completely housed in a storage space in such a way as to slide without requiring a user to perform an additional operation of pushing the headrest downwards, thus being more convenient for the user. The headrest apparatus has a simple structure and a reduced size, thus reducing the weight of the vehicle. The headrest apparatus includes a headrest sliding unit, a sinking seat folding unit, and a seat support frame supporting a sinking seat on a floor of the MPV, wherein, when the sinking seat is housed in a seat storage space formed in the floor of the MPV, the upper surface of the sinking seat that is in a housed state is level with the upper surface of the floor of the MPV. | 11-20-2014 |
20150291066 | APPARATUS FOR BACK-FOLDING STANDUP SEAT OF VEHICLE - An apparatus for back-folding a standup seat of a vehicle may include a standup associated back-folding unit that is installed between a hook mounted to a lower frame of a seat cushion to be locked to or unlocked from a striker of a floor panel, and a recliner mounted to a side frame of a seatback such that a forward folding operation of the seatback and a forward folding operation of a headrest that is automatically performed by operating the recliner during a standup operation. | 10-15-2015 |
Patent application number | Description | Published |
20100243309 | Connecting structure for circuit board and connecting method using the same - Disclosed is a connection structure for a circuit board using a solder bump to arrange circuit boards. The circuit board connection structure includes a solder bump prepared on one of two circuit boards and a perforated part formed at the other of the circuit boards to receive the solder bump. Facing both circuit boards towards each other and inserting the solder bump into the perforated part, the circuit boards are desirably arranged. | 09-30-2010 |
20100248505 | Printed circuit board assembly and connecting method thereof - Disclosed herein is a printed circuit board and a connecting method thereof. The connecting method of the circuit board assembly may include molding the printed circuit board assembly by applying a resin to the printed circuit board assembly, exposing ends of the electrode terminals of a connector mounted on a printed circuit board by partially removing the molded printed circuit board assembly, and connecting a connection member to the exposed ends of the electrode terminals of the connector. Therefore, even if the whole of the printed circuit board assembly is molded, the connection member may be freely connected to the connector of the printed circuit board assembly. | 09-30-2010 |
20110026233 | Apparatus and method for manufacturing elastic cable and electronic device using the same - Disclosed herein is an apparatus for manufacturing an elastic cable including conductor tracks arranged in a zigzag shape between elastic films. The apparatus may include a conductor track supplying unit to supply at least one conductor track, an aligning unit to align the at least one conductor track supplied from the conductor track supplying unit, a film supplying unit to supply elastic films such that the at least one conductor track is surrounded by the elastic films, and a thermal lamination roller unit to thermally laminate the at least one conductor track arranged between the elastic films, wherein the aligning unit is reciprocally movable to arrange the at least one conductor track in a zigzag shape between the elastic films when the at least one conductor track is supplied to the thermal lamination roller unit. | 02-03-2011 |
20110154661 | Method of fabricating printed circuit board assembly - Disclosed herein is a method for fabricating a printed circuit board assembly by adhering an element to a printed circuit board without using any solder. The printed circuit board may be fabricated by sequentially applying a conductor-containing first ink and an insulator-containing second ink onto a base substrate by ink-jet printing to form a printed circuit board, mounting an element on the printed circuit board such that an electrode of the element contacts a conductive layer and curing the conductive layer at a high temperature. | 06-30-2011 |
20110272181 | Multilayer Stretchable Cable - According to an example embodiment, the multilayer stretchable cable includes a multilayer stretchable film and a plurality of conductive lines in the stretchable film. The conductive lines are in at least two different layers of the multilayer stretchable film in a thickness direction of the stretchable film, at least one conductive line is a signal line and at least one other conductive line in a layer adjacent to the signal line is a ground line. The signal line and the ground line are in zigzag patterns and are parallel to a width direction of the multilayer stretchable film. | 11-10-2011 |
20120018084 | Printed Circuit Board Assembly Manufacturing Device And Method - Disclosed herein is a printed circuit board assembly manufacturing device and method of manufacturing a printed circuit board assembly. The printed circuit board assembly manufacturing device may include a fusing unit configured to cure a conductive adhesive used to fix electronic components having different heights to a printed circuit board. The fusing unit may be configured to cure the conductive adhesive while simultaneously applying pressure to the electronic components having different heights. | 01-26-2012 |
20120018186 | CASE STRUCTURE HAVING FILM TYPE ELECTRONIC CIRCUIT AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a case structure of an electronic product to which a film-type electronic circuit is adhered. The case structure may include a case of an electronic product and a first film adhered to the case. The case structure may further include a second film adhered to the first film such that one surface of the second film contacts the first film, and an electronic circuit layer adhered to the first film. The electronic circuit layer may be arranged between the first film and the second film, wherein the first film is thermally adhered to the case. The first film may have a melting at a melting point that is lower than a heat-resistant temperature of the case. | 01-26-2012 |
20120043116 | Interconnection Structure Of Interposer With Low CTE And Packaging Component Having The Same - Disclosed herein are printed circuit board assemblies made of a brittle material such as silicon, glass or ceramic and provided with a connector to electrically connect the same to an external connection member, and a method for molding the printed circuit board assembly wherein the printed circuit board assembly is molded by applying a polymer resin thereto to impart hardness to the printed circuit board assembly, and an electrode terminal to connect the same to the external connection member is exposed to the outside. Disclosed herein is also an interconnection structure of an interposer, the interconnection structure electrically connected to a main printed circuit board (PCB) through a solder joint is interposed between the interposer and the solder joint to prevent or reduce concentration of stress on the solder joint caused by differences in coefficients thermal expansion between the interposer and the main PCB. | 02-23-2012 |
20120045910 | MOLDING METHOD OF PRINTED CIRCUIT BOARD ASSEMBLY - Disclosed is a printed circuit board assembly PBA on which a connector for electrical connection to an external connection element is mounted. Such an assembly may be formed with a molding method of a PBA which includes applying a polymer resin to the PBA to mold the PBA in order to offer stiffness thereto. The foregoing method of molding the PBA according to the present disclosure is a molding method of a PBA including a PCB and a connector mounted on the PCB to electrically connect the same to an external connection element. The method includes combining the connector with a connector cover, applying a resin to the PBA combined with the connector cover to execute molding of the PBA, and separating the connector cover from the molded PBA to expose the electrode terminal for an external connection element. | 02-23-2012 |
20120212917 | Three-Dimensional Stack Structure Of Wafer Chip Using Interposer - The three-dimensional stack structure includes a printed circuit board, a first wafer chip mounted on the printed circuit board, a second wafer chip stacked above the first wafer chip, and first interposers interposed between the second wafer chip and the printed circuit board. The first interposers are configured to electrically connect the second wafer chip to the printed circuit board. | 08-23-2012 |
20130077265 | PRINTED CIRCUIT BOARD ASSEMBLY - A printed circuit board assembly capable of having an electronic component mounted at a wafer level by using a wafer itself as a printed circuit board, the printed circuit board assembly including a plurality of electronic components, a printed circuit board having the plurality of electronic components mounted thereon, a protection body configured to entirely cover the printed circuit board, and a connection unit having one end that is exposed to an outside of the protection body for the printed circuit board to be electrically connected to a sub board, wherein the printed circuit board comprises a wafer printed circuit board formed with a wafer. | 03-28-2013 |
20130213247 | STENCIL APPARATUS FOR PRINTING SOLDER PASTE - A solder paste printing stencil apparatus for printing a solder paste on a printed circuit board includes a plate-shaped stencil mask made of fine stainless steel grains to suppress a phenomenon in which the solder paste adheres to the stencil mask. | 08-22-2013 |