Patent application number | Description | Published |
20100012990 | MOSFETS INCLUDING CRYSTALLINE SACRIFICIAL STRUCTURES - A sub-micron channel length MOSFET includes a seamless epitaxial channel region in a substrate of the MOSFET and a buried device isolation layer beneath the seamless epitaxial channel region. In some embodiments according to the invention, a buried device isolation layer includes the buried device isolation layer beneath a central portion of the seamless epitaxial channel and absent from sidewalls of source/drain regions of the MOSFET. | 01-21-2010 |
20100205468 | APPARATUS AND METHOD FOR REDUCING POWER CONSUMPTION IN SYSTEM ON CHIP - An apparatus and method for reducing power consumption in a System on Chip (SoC) are provided. The SoC includes a clock unit for providing clocks to all elements included in the SoC, a Central Processing Unit (CPU) for controlling the SoC to perform designated functions, a main regulator for supplying power provided from an external battery to remaining elements included in the SoC other than a PMU, and a restoration processor for storing, in the PMU, registration information on the CPU and all peripherals included in the SoC when a transition from an active state to a sleep state is made. The PMU stops provision of a clock from the CPU by controlling the clock unit for stopping provision of all clocks by controlling the clock unit and for controlling the main regulator to be powered off when the restoration processor, wherein the PMU requests the restoration processor to store the registration information, completes the register information storing, when the transition from the sleep state to the active state is made. | 08-12-2010 |
20110086186 | ANTI-STATIC ADHESIVE COMPOSTION, POLARIZING PLATE AND SURFACE PROTECTIVE FILM USING THE COMPOSITION - Disclosed are an anti-static adhesive composition, and a polarizing plate and/or a surface protective film fabricated using the same. More particularly, an anti-static adhesive composition for imparting enhanced anti-static properties, including a metal salt represented by Formula 1 as an anti-static agent so as to sufficiently inhibit generation of static electricity while not deteriorating inherent physical properties of an adhesive such as adhesiveness, durability and reliability, etc., is provided. In addition, a polarizing plate and and/or a surface protective film fabricated using the foregoing anti-static adhesive composition are provided. | 04-14-2011 |
20120154243 | WIDEBAND SINGLE RESONANCE ANTENNA - Wideband single resonance antenna. An antenna may include a first conductor unit and a second conductor unit. The first conductor unit may be configured to have one end electrically coupled to a power. The second conductor unit may be configured to have one end electrically coupled to a ground, to surround at least one side of the first conductor unit, and to be electrically separated from the first conductor unit. | 06-21-2012 |
20120169567 | ANTENNA HAVING LINEAR ARRAY ANTENNA UNIT - An antenna may include a linear array antenna unit, a first switch, and a second switch. The linear array antenna unit may be configured to include a plurality of cable elements linearly arranged and coupled to each other. The first switch may include one end coupled to a ground and another end coupled to at least one of the plurality of cable elements of the linear array antenna unit. The second switch may include one end coupled to a power feed point and another end coupled to at least one of the plurality of cable elements. The plurality of cable elements of the linear array antenna unit may form one of a first antenna structure and a second antenna structure according to the switching operations of the first and second switches. | 07-05-2012 |
20130264371 | Medical Anastomosis Apparatus - A medical anastomosis apparatus is provided. The medical anastomosis apparatus includes a cylindrical body which has a hollow portion and extends in a longitudinal direction, a pressing rod which is provided inside of the hollow portion of the body to translate along the hollow portion, a knob which is coupled to the pressing rod to provide a driving force to translate the pressing rod, a guide member which is inserted into one end of the body and simultaneously coupled to expose a portion of the body and has a pressing unit formed therein to move radially upon translation of the pressing rod, and a staple cartridge which is inserted around an outer circumferential surface of the guide member and then coupled to the body and has built-in staple clips that protrude outward upon movement of the pressing unit. | 10-10-2013 |
20140039273 | METHOD OF TRACKING A POSITION OF AN EYE AND A MEDICAL HEAD LAMP USING THE SAME - A method of tracking a position of an eye is provided. The method of tracking a position of an eye includes converting an obtained image into a binary number image, classifying the corner of the eye, maximum and minimum values of a pupil of the eye, and extracting a feature point from the binary number image on which the binarization step is completed, calculating a distance and inclination between the corner and the pupil of the eye using the feature point extracted through the feature point extraction step, and determining a gaze direction of the eye based on the distance and inclination calculated through the distance and inclination calculation step. | 02-06-2014 |
Patent application number | Description | Published |
20090057761 | Fin field effect transistor and method of manufacturing the same - Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at least one active fin may be formed on a substrate. The at least one gate insulating layer pattern may be formed on the at least one active fin. The first electrode pattern may be formed on the at least one gate insulating layer pattern. Further, the first electrode pattern may be intersected with the at least one active fin. The second electrode pattern may be formed on the first electrode pattern. Further, the second electrode pattern may have a width greater than that of the first electrode pattern. The at least one pair of source/drain expansion regions may be formed on a surface of the at least one active fin on both sides of the first electrode pattern. Thus, the FinFET may have improved capacity and reduced GIDL current. | 03-05-2009 |
20090115009 | Multibit electro-mechanical memory device and manufacturing method thereof - Provided are a multibit electro-mechanical memory device and a method of manufacturing the same. The device may include at least one bit line in a first direction on a substrate; at least one gate line and at least one lower word line in parallel by a given interval and in a second direction intersecting the first direction on the at least one bit line; at least one contact pad adjacent to the at least one gate line on the at least one bit line; and at least one cantilever electrode coupled to the at least one contact pad, configured to float with a void above and beneath the at least one cantilever electrode and configured to curve in a third direction vertical to the first and second directions. | 05-07-2009 |
20090239346 | SEMICONDUCTOR DEVICE WITH FINFET AND METHOD OF FABRICATING THE SAME - A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in a central portion of the active region. Upper surfaces and side surfaces of the first projection and the second projection comprise a channel region. A channel ion implantation layer is provided at a bottom of the central trench and at a lower portion of the fin. A gate oxide layer is provided on the fin. A gate electrode is provided on the gate oxide layer. A source region and a drain region are provided in the active region at sides of the gate electrode. A method of forming such a device is also provided. | 09-24-2009 |
20100059807 | Semiconductor device having bar type active pattern - A semiconductor device having a bar type active pattern and a method of manufacturing the same are provided. The semiconductor device may include a semiconductor substrate having a semiconductor fin configured to protrude from a surface of the semiconductor substrate in a first direction, the semiconductor substrate having a first width and a second width crossing the first width, wherein the first width and the second width extend in a second direction. A plurality of active patterns may be arranged in the first direction with a separation gap from the semiconductor fin. A plurality of support patterns may be arranged between the semiconductor fin and one of the plurality of active patterns arranged closer to the semiconductor fin in the first direction, and between the plurality of active patterns arranged in the first direction to support the plurality of active patterns. A gate may be arranged to cross the plurality of active patterns in the second direction and to cover a portion of the at least one of the plurality of active patterns. | 03-11-2010 |
20100197094 | Fin field effect transistor and method of manufacturing the same - Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at least one active fin may be formed on a substrate. The at least one gate insulating layer pattern may be formed on the at least one active fin. The first electrode pattern may be formed on the at least one gate insulating layer pattern. Further, the first electrode pattern may be intersected with the at least one active fin. The second electrode pattern may be formed on the first electrode pattern. Further, the second electrode pattern may have a width greater than that of the first electrode pattern. The at least one pair of source/drain expansion regions may be formed on a surface of the at least one active fin on both sides of the first electrode pattern. Thus, the FinFET may have improved capacity and reduced GIDL current. | 08-05-2010 |
20100197099 | SCHOTTKY BARRIER FiNFET DEVICE AND FABRICATION METHOD THEREOF - A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies. | 08-05-2010 |
20100221876 | FIELD EFFECT TRANSISTORS WITH VERTICALLY ORIENTED GATE ELECTRODES AND METHODS FOR FABRICATING THE SAME - In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device. | 09-02-2010 |
Patent application number | Description | Published |
20090097315 | Multibit electro-mechanical memory device and method of manufacturing the same - A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever electrodes, and first and second upper word lines on the first and second trap sites. | 04-16-2009 |
20090197383 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths. | 08-06-2009 |
20100105181 | METHODS OF FABRICATING VERTICAL TWIN-CHANNEL TRANSISTORS - A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions. | 04-29-2010 |
20100129976 | Methods of Fabricating Electromechanical Non-Volatile Memory Devices - Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes portions of a surface of the semiconductor substrate therethrough. A conformal bit line is provided on the first electrode pattern and the exposed surface of semiconductor substrate. The bit line is spaced apart from a sidewall of the first electrode pattern and includes a conductive material having an elasticity generated by a voltage difference. An insulating layer pattern is provided on an upper surface of the bit line located on the semiconductor substrate. A second electrode pattern is spaced apart from the bit line and provided on the insulating layer pattern. The second electrode pattern faces the first electrode pattern. Related methods are also provided. | 05-27-2010 |
20100155827 | Semiconductor device having a multi-channel type MOS transistor - In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern. Mask pattern structures including a gate trench are formed on the active channel pattern and the source/drain layer. The patterns are selectively etched to form tunnels. The gate trench is then filled with a gate electrode. The gate electrode surrounds the active channel pattern. The gate electrode is protruded from the active channel pattern. The mask pattern structures are then removed. Impurities are implanted into the source/drain regions to form source/drain regions. A silicidation process is carried out on the source/drain regions to form a metal silicide layer, thereby completing a semiconductor device having a MOS transistor. | 06-24-2010 |
20110189829 | METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES HAVING STACKED STRUCTURES - A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure. | 08-04-2011 |
20110230001 | MULTIBIT ELECTRO-MECHANICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever electrodes, and first and second upper word lines on the first and second trap sites. | 09-22-2011 |
20120223373 | SEMICONDUCTOR DEVICE INCLUDING A CRYSTAL SEMICONDUCTOR LAYER, ITS FABRICATION AND ITS OPERATION - In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer covers the preliminary active pattern and the semiconductor substrate. By crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern are changed to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern, respectively. The crystalline semiconductor pattern and the barrier pattern constitute an active pattern. The sacrificial crystalline semiconductor layer is removed. | 09-06-2012 |
20140264572 | METHODS OF FORMING SEMICONDUCTOR DEVICES USING HARD MASK LAYERS - A method of forming a semiconductor structure can include forming a photolithography mask on a silicon fin having a hard mask layer thereon extending in a first direction. A trench can be formed through the hard mask layer into the silicon fin using the photolithography mask, where the trench extends in a second direction to separate the silicon fin into first and second fin structures extending end-to-end in the first direction. A portion of the trench formed by the hard mask layer can be widened relative to a lower portion of the trench defined by the first and second fin structures. | 09-18-2014 |
20140357061 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor device and a method for fabricating the same. The method for fabricating a semiconductor device comprises, providing an active fin and a field insulating film including a first trench disposed on the active fin; forming a second trench through performing first etching of the field insulating film that is disposed on side walls and a lower portion of the first trench; forming a first region and a second region in the field insulating film through performing second etching of the field insulating film that is disposed on side walls and a lower portion of the second trench, the first region is disposed adjacent to the active fin and has a first thickness, and the second region is disposed spaced apart from the active fin as compared with the first region and has a second thickness that is thicker than the first thickness; and forming a gate structure on the active fin and the field insulating film. | 12-04-2014 |
20150228722 | SEMICONDUCTOR DEVICE INCLUDING FIN-TYPE FIELD EFFECT TRANSISTOR - Provided is a semiconductor device including: a substrate; a first fin-field effect transistor comprising a first fin-type semiconductor layer having a first height and a first width, formed on the substrate; and a second fin-field effect transistor comprising a second fin-type semiconductor layer having a second height and a second width, formed on the substrate. The first fin-field effect transistor and the second fin-field effect transistor are separated by a predetermined distance. The first height is greater than the second height and the first width is less than the second width. | 08-13-2015 |
20160005738 | SEMICONDUCTOR DEVICE HAVING A FIN STRUCTURE AND METHOD OF MANUFACTURE THE SAME - A semiconductor device is provided. In some examples, the semiconductor device includes: a substrate, a fin structure disposed with the substrate, a source and a drain that are formed in the fin structure, a channel area disposed between the source and the drain, a gate dielectric layer disposed on the channel area, and a gate line disposed on the gate dielectric layer. The fin structure may include an anti-punch through layer, an upper fin structure disposed on the anti-punch through layer, the upper fin structure including a material having a lattice constant to receive a compressive strain. The fin structure may also include a lower fin structure disposed under the anti-punch through layer, and may comprise the same material as the substrate. | 01-07-2016 |
20160005852 | SEMICONDUCTOR DEVICES HAVING LOWER AND UPPER FINS AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin. | 01-07-2016 |
Patent application number | Description | Published |
20080233693 | COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) DEVICES INCLUDING A THIN-BODY CHANNEL AND DUAL GATE DIELECTRIC LAYERS AND METHODS OF MANUFACTURING THE SAME - A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer. The CMOS device further includes a p-channel metal-oxide semiconductor (PMOS) transistor including a PMOS thin body channel including a silicon epitaxial layer. A PMOS insulating layer is formed on a surface of and surrounds the PMOS thin body channel. A PMOS metal gate is formed on the PMOS insulating layer. The NMOS insulating layer includes a silicon oxide layer and the PMOS insulating layer includes an electron-trapping layer, the NMOS insulating layer includes a hole trapping dielectric layer and the PMOS insulating layer includes a silicon oxide layer, or the NMOS insulating layer includes a hole-trapping dielectric layer and the PMOS insulating layer includes an electron-trapping dielectric layer. | 09-25-2008 |
20090168493 | SEMICONDUCTOR MEMORY DEVICE WITH STACKED MEMORY CELL AND METHOD OF MANUFACTURING THE STACKED MEMORY CELL - In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells. | 07-02-2009 |
20090215238 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH ENLARGED RECESSED GATE ELECTRODES - A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed. | 08-27-2009 |
20090275177 | SEMICONDUCTOR DEVICE WITH MULTIPLE CHANNELS AND METHOD OF FABRICATING THE SAME - A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer. | 11-05-2009 |
20090294864 | MOS FIELD EFFECT TRANSISTOR HAVING PLURALITY OF CHANNELS - A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed. | 12-03-2009 |
20120161247 | Gate-All-Around Integrated Circuit Devices and Methods of Manufacturing the Same - Gate-all-around integrated circuit devices include first and second source/drain regions on an active area of an integrated circuit substrate. The first and second source/drain regions form p-n rectifying junctions with the active area. A channel region extends between the first and second source/drain regions. An insulated gate electrode surrounds the channel region. | 06-28-2012 |