Patent application number | Description | Published |
20090019449 | Load balancing method and apparatus in symmetric multi-processor system - Provided are a load balancing method and a load balancing apparatus in a symmetric multi-processor system. The load balancing method includes selecting at least two processors based on a load between a plurality of processors, from among the plurality of processors, migrating a predetermined task stored in a run queue of a first processor to a migration queue of a second processor, and migrating the predetermined task stored in the migration queue of the second processor to a run queue of the second processor. Accordingly, a run queue of a processor is not blocked while migrating a task, an immediate response of the run queue is possible, and a waiting time of a scheduler is reduced. Consequently, the scheduler can speedily perform context switching, and thus performance of the entire operating system is improved. | 01-15-2009 |
20090063790 | Method and apparatus for managing configuration memory of reconfigurable hardware - Provided is a method of managing a configuration memory of reconfigurable hardware which can reconfigure hardware according to hardware configuration information. The method includes: determining at least one slot capable of currently storing the hardware configuration information on the basis of the states of a plurality of slots of the configuration memory; and storing hardware configuration information, which is stored in an external memory, in the determined at least one slot capable of currently storing the hardware configuration information. Accordingly, memory utilization can be improved even in dynamic environment such as data dependent control flow or multi-tasking. | 03-05-2009 |
20100115169 | Processor and interrupt handling method - Disclosed are a processor and an interrupt handling method. The processor of the present exemplary embodiments may include a plurality of processing elements and may predict whether a periodic interrupt occurs during a parallel processing mode before entering a mode in which the plurality of processing elements share a single task to process the single task in parallel. The processor may delay entering the parallel processing mode based on the prediction. The processor may reduce overhead that stores a context of the plurality of processing elements when the interrupt occurs. | 05-06-2010 |
20100115529 | Memory management apparatus and method - A memory management apparatus and a memory management method may divide an external memory area assigned to a task into a first area and a second area, and load data stored in the first area into an internal memory of a processor while the task is performed by the processor. | 05-06-2010 |
20110016285 | Apparatus and method for scratch pad memory management - Disclosed is a scratch pad memory management device and a method thereof. The scratch pad memory management device divides a scratch pad memory into a plurality of unit blocks, maintains a memory allocation table corresponding to indices of the plurality of unit blocks in a main memory, and manages the scratch pad memory. | 01-20-2011 |
20110119656 | Computing system, method and computer-readable medium processing debug information in computing system - Disclosed are a system, method and computer-readable medium related to processing debug information from an embedded system. Source code of an application program to be used in an embedded system may be compiled by a computing system. The application program may include a debug code line. A minimum amount of debug information is stored in an embedded system, reducing memory overhead and waste of clock cycles of a processor. | 05-19-2011 |
20110252258 | HARDWARE ACCELERATION APPARATUS, METHOD AND COMPUTER-READABLE MEDIUM EFFICIENTLY PROCESSING MULTI-CORE SYNCHRONIZATION - Provided is a hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization. A processor core that fails to acquire a lock variable may be switched to a low power sleep mode and a waste of power may be reduced. Additionally, when a lock variable is returned, a wakeup signal may be transmitted to a processor core operated in the low power sleep mode, and the processor core may be activated. | 10-13-2011 |
20120198206 | APPARATUS AND METHOD FOR PROTECTING MEMORY IN MULTI-PROCESSOR SYSTEM - Memory mapping in small units using a segment and subsegments is described, and thus it is possible to control a memory access even using a small amount of hardware, and it is possible to reduce costs incurred by hardware. Additionally, it is possible to prevent a memory from being destroyed due to a task error in the multi-processor system. | 08-02-2012 |
20130179674 | APPARATUS AND METHOD FOR DYNAMICALLY RECONFIGURING OPERATING SYSTEM (OS) FOR MANYCORE SYSTEM - An apparatus and method for dynamically reconfiguring an Operating System (OS) for a manycore system are provided. The apparatus may include an application type determining unit to determine a type of an executed application, and an OS reconfiguring unit to activate only at least one function in an OS, based on the determined type of the application, and to reconfigure the OS. | 07-11-2013 |
20130205298 | APPARATUS AND METHOD FOR MEMORY OVERLAY - A memory overlay apparatus includes an internal memory that includes a dirty bit indicating a changed memory area, a memory management unit that controls an external memory to store only changed data so that only data actually being used by a task during overlay is stored and restored, and a direct memory access (DMA) management unit that confirms the dirty bit when the task is changed and that moves a data area of the task between the internal memory and the external memory. | 08-08-2013 |
20140019782 | APPARATUS AND METHOD FOR MANAGING POWER BASED ON DATA - Provided is an apparatus and method for managing power based on data. The apparatus may include a code segment searching unit configured to search for at least one code segment in which a power type is inserted, a block determining unit configured to determine at least one block based on the at least one found code segment, and a power mode control unit configured to control the at least one determined block to operate in a power mode corresponding to the power type. | 01-16-2014 |
Patent application number | Description | Published |
20120070191 | DEVELOPMENT DEVICE ATTACHMENT UNIT AND IMAGE FORMING APPARATUS HAVING THE SAME - An image forming apparatus includes a guide member to guide movement of a developing device receiving member, which receives a plurality of developing devices, between the exterior and the interior of an image forming apparatus body. The guide member supports the developing device receiving member to enable rotation of the developing device receiving member within the body. | 03-22-2012 |
20130129382 | IMAGE FORMING APPARATUS - An image forming apparatus capable of easily achieving installation of developing units on a developing tray is disclosed. The disclosed image forming apparatus includes a tray section, a plurality of developing units each provided with guide protrusions, and a developing tray including a plurality of supports to support the guide protrusions of the developing units, and a plurality of guides each adapted to guide a corresponding one of the guide protrusions to a corresponding one of the supports. The guides have widths gradually increasing in a direction from a first end of the tray section to a second end of the tray section, respectively. | 05-23-2013 |
20140204406 | IMAGE FORMING APPARATUS, HOST APPARATUS, IMAGE FORMING METHOD, PRINT CONTROL METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - An image forming apparatus, a method, and a computer-readable recording medium are provided. The image forming apparatus includes an input unit which receives image data, a detection unit which detects a printing concentration of the received image data, an image processing unit which composes a copy protection pattern and the image data so that the copy protection pattern is printed with a concentration corresponding to the detected printing concentration, and an image forming unit which prints image data composed with the copy protection pattern. | 07-24-2014 |
Patent application number | Description | Published |
20150114705 | MULTILAYER CERAMIC CAPACITOR AND BOARD HAVING THE SAME - There are provided a multilayer ceramic capacitor and a board having the same. The multilayer ceramic capacitor may include: three external electrodes disposed on a mounting surface of a ceramic body to be spaced apart from each other and connected to lead portions of internal electrodes, wherein an interval between adjacent lead portions is 500.7 μm or less, widths of one-side margin portions of the external electrodes in a length direction of the ceramic body that are not in contact with the corresponding lead portions are 20.2 μm or more. | 04-30-2015 |
20150124370 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor may include a ceramic body having a plurality of dielectric layers; first and second internal electrodes disposed in the ceramic body to be alternately exposed to the first and second end surfaces of the ceramic body, having the dielectric layers interposed therebetween; and first and second external electrodes electrically connected to the first and second internal electrodes, respectively. The first and second external electrodes may include: first and second internal conductive layers; first and second insulating layers; and first and second external conductive layers. | 05-07-2015 |
20150243438 | MULTILAYER CERAMIC CAPACITOR AND BOARD HAVING THE SAME - A multilayer ceramic capacitor and a board having the same are provided. The multilayer ceramic capacitor includes three external electrodes including a conductive layer, a nickel plating layer, and a tin plating layer sequentially stacked on a mounting surface of the ceramic body, and spaced apart from each other. When an outermost portion of a lead-out portion of an internal electrode exposed to the mounting surface is P, a total thickness of the conductive layer, the nickel plating layer, and the tin plating layer in a normal line direction of the conductive layer from P is a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is b | 08-27-2015 |
20150318113 | MULTILAYER CERAMIC CAPACITOR AND MOUNTING BOARD FOR MOUNTING THEREOF - A multilayer ceramic capacitor includes: a ceramic body including a plurality of dielectric layers and a plurality of first and second internal electrodes stacked in a width direction; a pair of first external electrodes disposed on a mounting surface of the ceramic body to be spaced apart from one another and connected to the plurality of first internal electrodes; a second external electrode disposed between the pair of first external electrodes on the mounting surface of the ceramic body and connected to the plurality of second internal electrodes; and a dummy electrode disposed on a surface of the ceramic body opposing the mounting surface of the ceramic body. | 11-05-2015 |
20150318114 | MULTILAYER CERAMIC CAPACITOR AND BOARD HAVING THE SAME - A multilayer ceramic capacitor and a board having the same are provided. The multilayer ceramic capacitor includes three external electrodes including a conductive layer, a nickel plating layer, and a tin plating layer sequentially stacked on a mounting surface of the ceramic body, and spaced apart from each other. When an outermost portion of a lead-out portion of an internal electrode exposed to the mounting surface is P, a total thickness of the conductive layer, the nickel plating layer, and the tin plating layer in a normal line direction of the conductive layer from P is a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is b | 11-05-2015 |
20160049250 | MULTILAYER CERAMIC CAPACITOR AND BOARD HAVING THE SAME - There are provided a multilayer ceramic capacitor and a board having the same. The multilayer ceramic capacitor may include: three external electrodes disposed on a mounting surface of a ceramic body to be spaced apart from each other and connected to lead portions of internal electrodes, wherein an interval between adjacent lead portions is 500.7 μm or less, widths of one-side margin portions of the external electrodes in a length direction of the ceramic body that are not in contact with the corresponding lead portions are 20.2 μm or more. | 02-18-2016 |
Patent application number | Description | Published |
20120285165 | ENGINE SYSTEM BASED ON TURBO CHARGER AND FUEL RATIO IMPROVING METHOD THEREOF - An engine system may include an electric or mechanical supercharger and an LP-EGR, basically with a turbocharger, an EGR valve, a channel control valve, and a bypass valve, which control the flow rate of external air and exhaust gas, may be integrally operated, and a operation section may be divided into a turbo-lag and low torque section, a mid-load section, and mid/high-load section such that the open amount of EGR valve, channel control valve, and bypass valve may be optimally controlled, such that it may be possible to improve availability for a low-speed/high-load section with turbo-lag reduced, using supercharger and considerably increase the ratio of fuel efficiency improvement in the low-speed/high-load section, using LP-EGR operating with supercharger. | 11-15-2012 |
20130146006 | Continuous Variable Valve Duration Apparatus - A continuous variable valve duration apparatus may vary an opening duration of a valve. The continuous variable valve duration apparatus may include a camshaft in which a camshaft slot is formed, a cam portion of which a cam and a cam slot are formed thereto and of which a rotation center is identical to a rotation center of the camshaft and the cam portion of which a phase angle to the cam shaft is variable, and a duration control portion which varies the phase angle between the camshaft slot and the cam slot. | 06-13-2013 |
20130146037 | MILLER CYCLE ENGINE SYSTEM AND CONTROL METHOD THEREOF - A miller cycle engine system is provided, which includes a motorized supercharger, and a miller cycle engine (having low compression and high explosion) having the motorized supercharger mounted thereon to improve a low-revolution performance of an engine using a scavenging phenomenon due to an operation of a variable valve device (variable valve timing, variable valve lift and variable valve duration) during an operation of the motorized supercharger and to improve a fuel efficiency through down-speeding of a gear ratio of a vehicle. | 06-13-2013 |
20130333360 | SECONDARY AIR INJECTION SYSTEM - A secondary air injection system supplying some of air introduced into an intake manifold to an exhaust manifold may include: an electric supercharger compressing air introduced through an air duct; throttle valves installed at an upstream of the intake manifold and controlling the amount of air introduced into the intake manifold by controlling the amount of air passing through the electric supercharger; secondary air valves installed on branching paths branched from intake, lines that link the electric supercharger and the throttle vales and controlling the amount of air for secondary air injection; and an injector that post-combusts exhaust gas discharged from an engine by injecting secondary air passing through the secondary air valve to a runner of the manifold. | 12-19-2013 |
20140165959 | ENGINE HAVING VARIABLE VALVE TIMING DEVICE AND VARIABLE TUMBLE DEVICE - An engine having a variable valve timing device and a variable tumble device, may include the variable valve timing device advancing or delaying a rotation of an intake camshaft or an exhaust camshaft, an intake valve or an exhaust valve configured to be operated by the intake camshaft or the exhaust camshaft respectively to open and close an intake port or an exhaust port, and the variable tumble device that may be disposed on an upstream side of the intake valve in the intake port and changes a flow of a gas being suck to form a tumble in a combustion chamber. | 06-19-2014 |
20140165960 | VARIABLE INTAKE MANIFOLD FOR INTERNAL COMBUSTION ENGINE AND VARIABLE AIR INTAKE DEVICE USING THE SAME - A variable intake manifold apparatus for an internal combustion engine, may include an inlet drawing in outside air and being connected to a main passage, first and second outlets branched from the main passage and fluid-connected to the inlet through the main passage and releasing the outside air drawn through the main passage through the first and second outlets, and a partition dividing the main passage and one of the first and second intake passages. | 06-19-2014 |
20140172271 | METHOD OF CONTROLLING ELECTRIC CONTINUOUS VARIABLE VALVE TIMING APPARATUS - A method of controlling an electric continuous variable valve timing apparatus improves starting performance of an engine by a simplified phase control for the camshaft. The method, in which intake and exhaust timing of an engine is changed in accordance with a phase of the camshaft, may include: determining whether starting off of the engine is required during driving; recognizing a target phase of the camshaft for next starting of the engine; controlling the phase of the camshaft so that the intake timing of the engine is advanced in accordance with the target phase; and ending the phase control of the camshaft in accordance with a state of the engine or the camshaft. | 06-19-2014 |
20150020522 | ENGINE SYSTEM - An engine system may include a first intake line connected to an intake manifold and supplying the intake manifold disposed on a cylinder block with outside air, an intake bypass valve disposed on the first intake line, a second intake line that bypasses the first intake bypass valve to the intake manifold, a first exhaust line through which exhaust gas flows from an exhaust manifold disposed on the cylinder block, an exhaust bypass valve disposed on the first exhaust line, a second exhaust line connected to the exhaust manifold and bypasses the exhaust bypass valve, a turbo charger disposed between the second intake line and the second exhaust line and operated by exhaust gas passing the second exhaust line to pump intake air flowing the second intake line, and a control portion that controls the intake bypass valve and the exhaust bypass valve depending on a driving condition. | 01-22-2015 |
20150068204 | ENGINE SYSTEM - An engine system may include a main intake line, a supplementary intake line branched from the main intake line and joined to the main intake line, an intake bypass valve mounted to the main intake line, a main exhaust line mounted to an exhaust manifold, a supplementary exhaust line branched from the exhaust manifold and joined to the main exhaust line, an exhaust bypass valve mounted to the main exhaust line and selectively opening the main exhaust line, a turbocharger disposed adjacent to the supplementary exhaust line and operated by exhaust gas passing through the supplementary exhaust line, and a control unit for controlling the intake bypass valve and the exhaust bypass valve depending on an operation condition, wherein the exhaust gas is re-circulated from an upstream side of the exhaust bypass valve to the main intake line passing through an EGR (Exhaust Gas Recirculation) cooler and an EGR valve. | 03-12-2015 |
20150152777 | CONTROL METHOD FOR TURBOCHARGER - A control method for a turbocharger system may include controlling opening levels of an intake bypass valve, an exhaust bypass valve, and a throttle valve according to a driving condition of a vehicle by a controller, and executing a series of commands by the controller, including determining whether an engine rpm satisfies a set low/medium speed condition, determining whether an acceleration request condition is satisfied when the engine rpm satisfies the set low/medium speed condition, closing the intake bypass valve, and controlling an opening angle of the exhaust bypass valve according to the acceleration request condition. | 06-04-2015 |
Patent application number | Description | Published |
20080310227 | SEMICONDUCTOR MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A NOR flash memory device and related programming method are disclosed. The programming method includes programming data in a memory cell and, during a program verification operation, controlling the supply of current from a sense amplifier to the memory cell in relation to the value of the programmed data. Wherein a program verification operation is indicated, current is provided from the sense amplifier to the memory cell. Where a program verification operation is not indicated, current is cut off from the sense amplifier. | 12-18-2008 |
20090052253 | Memory device and method reducing fluctuation of read voltage generated during read while write operation - Provided is a device and method for reducing a fluctuation of a read voltage generated during a read while write (RWW) operation. A semiconductor memory device may include a write voltage generator configured to generate a write voltage to perform the write operation to at least one of a plurality of banks where the write voltage generator generates the write voltage to have a voltage level of a read voltage before the write operation changes to a read operation. The semiconductor device may also include a read voltage generator configured to generate a read voltage to perform the read operation to at least one of the other plurality of banks and/or a plurality of switches configured to switch a voltage applied to at least one of the banks to one of the write voltage and the read voltage in response to a plurality of control signals. | 02-26-2009 |
20090185418 | FLASH MEMORY DEVICE CONFIGURED TO SWITCH WORDLINE AND INITIALIZATION VOLTAGES - Provided is a flash memory device including a wordline voltage generating unit, a switch unit, a row decoder and a control circuit. The wordline voltage generating unit generates at least one wordline voltage for read operations of a multi-level cell in the flash memory device. The switch unit receives the at least one wordline voltage and an initialization voltage, and selectively outputs the at least one wordline voltage and the initialization voltage through a switching operation. The row decoder operates the wordline of the multi-level cell based on an output of the switch unit. The control circuit provides at least one control signal to the switch unit, which outputs the initialization voltage in at least one section of the read operation in response to the at least one control signal. | 07-23-2009 |
20110019472 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A nonvolatile semiconductor memory device and a programming method thereof are provided. The programming method includes first programming a cell among a plurality of adjacent memory cells to the highest threshold voltage distribution corresponding to a data state, and subsequently programming the other adjacent cells to the lower threshold voltage distributions corresponding to second and third data states. The second data state and the third data state may have the second highest threshold voltage distribution and the third highest threshold voltage distribution, respectively, or the third highest threshold voltage distribution and the second highest threshold voltage distribution, respectively. | 01-27-2011 |
20120106251 | FLASH MEMORY DEVICE CONFIGURED TO SWITCH WORDLINE AND INITIALIZATION VOLTAGES - Provided is a flash memory device including a wordline voltage generating unit, a switch unit, a row decoder and a control circuit. The wordline voltage generating unit generates at least one wordline voltage for read operations of a multi-level cell in the flash memory device. The switch unit receives the at least one wordline voltage and an initialization voltage, and selectively outputs the at least one wordline voltage and the initialization voltage through a switching operation. The row decoder operates the wordline of the multi-level cell based on an output of the switch unit. The control circuit provides at least one control signal to the switch unit, which outputs the initialization voltage in at least one section of the read operation in response to the at least one control signal. | 05-03-2012 |
Patent application number | Description | Published |
20150118282 | TRANSDERMALLY ABSORBABLE PREPARATION CONTAINING ROTIGOTINE - A method for preventing the precipitation of rotigotine crystals, including a step of mixing rotigotine and one or more crystallization prevention agents selected from the group consisting of fatty alcohols, fatty acids, fatty acid esters, fatty acid amides, and the derivatives thereof, and to a transdermally absorbable preparation that includes rotigotine and crystallization prevention agents. | 04-30-2015 |
20150118309 | PREPARATION FOR PERCUTANEOUS ABSORPTION CONTAINING ROTIGOTINE - Exemplary embodiments of the present invention relate to a method for preparing a preparation for percutaneous absorption, which includes rotigotine as an active ingredient, and more specifically, to a method for preparing a preparation for percutaneous absorption including mixing rotigotine and an ethylene-vinyl acetate adhesive so as to have a weight ratio of 1:(0.1 to 20), a preparation for percutaneous absorption manufactured by the method, and a percutaneous treatment system. The preparation and the system may prevent separation of the rotigotine, thereby increasing long-term storage stability, and effectively release the rotigotine, and thus can be effectively applied to preparing patch medication containing the rotigotine. | 04-30-2015 |
Patent application number | Description | Published |
20090165532 | JIG frame for drop test of flat panel display - A jig frame for a drop test of a flat panel display, which is designed to allow a tester to effectively identify if the flat panel display is damaged and to easily adjust its weight and degree of deformation is provided. The jig frame for a drop test of a flat panel display includes a base plate having a groove for receiving the flat panel display and a cover plate fixing the flat panel display by covering the flat panel display and being coupled to the base plate. The cover plate is formed of transparent material so that the flat panel display installed in the jig frame is visible to outside of the cover plate. | 07-02-2009 |
20090168318 | Organic light emitting diode display - An organic light emitting diode (OLED) display has an increased mechanical strength by improving the shape of a bezel combined to a panel assembly. The OLED display includes a panel assembly having a display area and a pad area, and a bezel accommodating the panel assembly. The bezel includes a bottom part on which the panel assembly is mounted, a side wall provided on a side of the bezel, and a hemming flange provided at another side of the bezel on which the side wall is not provided. The panel assembly is mounted in a manner that the pad area is turned towards the another side. | 07-02-2009 |
20090185339 | Flat panel display apparatus - A flat panel display apparatus includes a flat display panel including first and second substrates facing each other with a display unit therebetween, the first substrate extending beyond the second substrate, a portion of the first substrate extending beyond the second substrate defining a protruding portion, an outermost edge of the protruding portion defining a protruding edge of the first substrate, and corners of the protruding portion being chamfered, and a bezel surrounding the flat display panel. | 07-23-2009 |
20090195485 | Organic light emitting diode display - An OLED display that is enhanced in mechanical strength by improving a structure of a bezel supporting a panel assembly. The OLED display includes a panel assembly that includes a display region, a pad region, and a plurality of OLEDs arranged in the display region and a bezel coupled to the panel assembly, the bezel including synthetic resin, wherein, when a diagonal length of the display region is in the range of 25.4 to 101.6 mm, the bezel being designed to satisfy the following inequality t≧0.0003×a, where t(mm) is a thickness of the bezel and a(mm | 08-06-2009 |
20090257181 | Organic light emitting diode display and method of manufacturing the same - An organic light emitting diode display that includes a display panel and a bezel to receive the display panel, the bezel including a first bezel and a second bezel, each of the first bezel and the second bezel including different materials and including a bottom portion and a skirt portion protruding from edges of the bottom portion. | 10-15-2009 |
20120319123 | Display Device and Method of Manufacturing the Same - A display device may include a first substrate comprising a display region and a non-display region surrounding the display region, a first metal wiring formed in the display region of the first substrate, a second metal wiring formed in the non-display region of the first substrate, a sealing member formed on the second metal wiring, and a second substrate disposed on the sealing member so as to face the first substrate. The first metal wiring and the second wiring are made of the same material. | 12-20-2012 |
Patent application number | Description | Published |
20090066643 | TOUCH SCREEN PANEL TO INPUT MULTI-DIMENSION VALUES AND METHOD FOR CONTROLLING TOUCH SCREEN PANEL - A touch screen panel to input multi-dimension values and a method of controlling the touch screen panel are provided. In the touch screen panel, a touch screen unit displays a multi-dimensional coordinate system, and senses whether a certain point of the multi-dimensional coordinate system is touched, a control unit calculates coordinates of the touched point if the touched point is sensed, and a coordinate display unit displays values of the calculated coordinates. | 03-12-2009 |
20100060921 | IMAGE FORMING APPARATUS, IMAGE FORMING SYSTEM AND CONTROL METHOD IN IMAGE FORMING APPARATUS - An image forming apparatus, an image forming system including the same, and a control method of the image forming apparatus, the image forming apparatus including: an output unit; a scanning unit to scan a damaged bank note and generate image data therefrom; and a controller to calculate an area of the damaged bank note using the generated image data of the scanned damaged bank note and to control the output unit to output damaged bank note information including the calculated area of the damaged bank note and/or an exchangeable value of the damaged bank note corresponding to the area of the damaged bank note. | 03-11-2010 |
20110130173 | MOBILE DEVICE AND CONTROL METHOD THEREOF - The mobile device for providing a haptic function includes a vibration unit which generates vibration for a tactile effect as the haptic function; and a control unit which includes a platform providing an application programming interface (API) corresponding to the haptic function and having a plurality of parameters, executes an application prepared by the API, determines a characteristic of the vibration based on the plurality of parameters set up in the application, and controls the vibration unit to generate the vibration having the determined characteristic. | 06-02-2011 |
20120270611 | METHOD FOR CONTROLLING MOBILE TERMINAL - A method for controlling a mobile terminal is provided. The method includes obtaining operation mode switching information made by a sensor, and determining whether an operation mode switching condition of the mobile terminal is satisfied based on the information; and switching an operation mode of the mobile terminal, if the switching condition is satisfied, wherein obtaining and switching are performed by an application that invokes and uses an Application Programming Interface (API). | 10-25-2012 |
Patent application number | Description | Published |
20090196383 | CORRELATION APPARATUS AND METHOD FOR FREQUENCY SYNCHRONIZATION IN BROADBAND WIRELESS ACCESS COMMUNICATION SYSTEM - A correlation apparatus and method for frequency synchronization are provided. A frequency synchronization method of a receiver in a broadband wireless access communication system includes acquiring a highest correlation value by conducting a differential correlation of a variable interval between a received signal and a reference signal and performing a frequency synchronization according to the highest correlation value. | 08-06-2009 |
20120134453 | METHOD FOR DEMODULATING RECEIVED SIGNALS AND APPARATUS THEREFORE - Disclosed are a method for demodulating received signals and an apparatus therefore which can maintain quality of signals and can reduce computational complexity. A demodulation method of a receiving device for receiving a plurality of signals modulated through a M-ary (M is a natural number of 1 or more) modulation method includes: comparing channel frequency response power of a first channel with channel frequency response power of a second channel, selecting M reference signals on the basis of the compared result, selecting corresponding signals paired with respective selected M reference signals, and estimating transmitting signals from the M signal pairs including pairs of the reference signal and the corresponding signal. Accordingly, the computational complexity is reduced from O (M | 05-31-2012 |
20160061490 | Cooking Appliance - Provided is a cooking appliance having an improved structure in which superheated steam is capable of being used during a cooking operation. The cooking appliance supplies superheated steam while food is cooked, and includes: a main body, a front of which is opened and in which a cooking compartment is disposed; a heating chamber disposed in the main body to be in communication with the cooking compartment; a steam generator disposed to generate steam sprayed into the heating chamber; and a convection heater disposed in the heating chamber to heat the heating chamber and the cooking compartment. The convection heater heats steam discharged from the steam generator, and the steam discharged from the steam generator, in a superheated steam state, is sprayed into the heating chamber and supplied into the cooking compartment. | 03-03-2016 |
Patent application number | Description | Published |
20150179594 | PACKAGE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A package substrate and a method for manufacturing the same are disclosed. The method for manufacturing a package substrate in accordance with an aspect of the present invention includes: forming a first open hole corresponding to a shape of a bonding pad in a first photo resist; laminating a second photo resist on the first photo resist and forming a second open hole corresponding to shapes of a soldering pad, a circuit pattern layer and the bonding pad in the second photo resist; and forming a pattern plating layer up to a predetermined height in the first open hole and the second open hole. | 06-25-2015 |
20150364407 | PACKAGE BOARD AND PACKAGE USING THE SAME - There are provided a package board and a package using the same. The package board according to an exemplary embodiment of the present disclosure includes: an insulating layer; a circuit pattern formed in the insulating layer; a capacitor formed on a whole surface of a horizontal plane in the insulating layer; and a first via penetrating through the capacitor and electrically connecting the circuit patterns each formed on upper and lower portions of the capacitor to each other. | 12-17-2015 |
20150364539 | PACKAGE BOARD AND PACKAGE USING THE SAME - There are provided a package board and a package using the same. The package board according to an exemplary embodiment of the present disclosure includes: an insulating layer; a dielectric layer formed on the insulating layer; a lower electrode formed on a whole surface of an upper surface of the insulating layer; and an upper electrode formed on a whole surface of an upper surface of the dielectric layer. | 12-17-2015 |
20150366059 | CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - A seed layer and a resist layer are formed on a solder resist layer, and the resist layer is patterned to form connection pads and pad plating layers. Then, the resist layer is removed, and the seed layer exposed to the outside is removed. A device may be mounted on this circuit board, and a connection terminal of the device and the connection pad of the circuit board may be connected to each other by a wire, or the like. | 12-17-2015 |
20160105956 | PRINTED CIRCUIT BOARD AND METHOD OF FABRICATING THE SAME - The present invention provides a printed circuit board includes an insulating member, a first plating layer buried in a bottom region of the insulating member, a second plating layer buried in a top region of the insulating member and a plating via for electrically connecting the first plating layer and the second plating layer by being buried in any one among the top region and the bottom region of the insulating member. | 04-14-2016 |