Chun-Wei
Chun Wei Chen, Science - Based Industrial Park Hs TW
Patent application number | Description | Published |
---|---|---|
20110261231 | DISPLACEMENT DETECTION DEVICE AND DISPLACEMENT DETECTION METHOD THEREOF - A displacement detection method includes the steps of: acquiring an image frame; calculating a characteristic index of the image frame; maintaining the image frame when the characteristic index is larger than a threshold value; and adding a fixed pattern to the image frame when the characteristic index is smaller than the threshold value. The present invention further provides a displacement detection device. | 10-27-2011 |
Chun Wei Chen, Science - Based Industrial Park Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110150363 | DISPLACEMENT DETECTION APPARATUS AND METHOD - A displacement detection method includes the steps of: capturing a first frame and a second frame; selecting a first block with a predetermined size in the first frame and selecting a second block with the predetermined size in the second frame; determining a displacement according to the first block and the second block; comparing the displacement with at least one threshold; and adjusting the predetermined size according to a comparison result of comparing the displacement and the threshold. The present invention further provides a displacement detection apparatus. | 06-23-2011 |
20130301880 | DISPLACEMENT DETECTION APPARATUS AND METHOD - A displacement detection method includes the steps of: capturing a first frame and a second frame; selecting a first block with a predetermined size in the first frame and selecting a second block with the predetermined size in the second frame; determining a displacement according to the first block and the second block; comparing the displacement with at least one threshold; and adjusting the predetermined size according to a comparison result of comparing the displacement and the threshold. The present invention further provides a displacement detection apparatus. | 11-14-2013 |
Chun Wei Huang, Hsinchu City TW
Patent application number | Description | Published |
---|---|---|
20090248907 | Method for automatically identifying an operating system for a USB device - A method for automatically identifying an operating system for a USB device begins at initializing the USB device, and recording USB commands sent from the operating system. The USB device determines the operating system as a first operating system when there are two successive USB commands of Get Product String, there is one USB command of Get Vender String, there is no USB command of Reset ahead of a USB command of Set Address, there is no USB command of Get Language ID, or there is no USB command of Set Feature Report. The USB device determines the operating system as a second operating system when there is no USB command of Get Vender String, there are two USB commands of Get Language ID and two USB commands of Get Product String, there is one USB command of Get Device Descriptor following a USB command of Get Product String, or there is one USB command of Set Interface Report. | 10-01-2009 |
20110261016 | Optical touch screen system and method for recognizing a relative distance of objects - An optical touch screen system for recognizing a relative distance of an object based on optical sensors includes a display screen to display visual prompts to solicit actions from a user; first and second lighting and sensing modules mounted on two adjacent corners of the display screen for forming first and second visual fields above the display screen respectively, wherein the first and the second visual fields intersect to form a touch area on the display screen, and the first and the second lighting and sensing modules detect an object entering the touch area and generate a first electrical position signal and a second electrical position signal respectively; and a processor for calculating a position of the object based on the first electrical position signal and the second electrical position signal. | 10-27-2011 |
Chun Wei Tsai, Taichung City TW
Patent application number | Description | Published |
---|---|---|
20140089178 | MOBILE FINANCIAL TRANSACTION SYSTEM AND METHOD - Mobile financial transaction system and method are disclosed for use with mobile payment and secure financial service platform. With the method and system disclosed, users can perform mobile financial transactions with a handheld mobile device. First, a billing information is acquired through the Internet and/or image capturing, and then a microSD flash memory card embedded with security chip and containing a personal financial information and/or near field communication technology is used to communicate with nearby payment devices to acquire a payment information. The payment information is then transferred to a payment gateway to finish a financial transaction. In addition, a secure value added service platform provides follow-up financial services. | 03-27-2014 |
Chun Wei Wu, Taishan Township TW
Patent application number | Description | Published |
---|---|---|
20120237858 | PHOTOMASK AND A METHOD FOR DETERMINING A PATTERN OF A PHOTOMASK - The present invention relates to a photomask and a method for determining a pattern of the photomask. The photomask includes a base and a plurality of square areas, wherein the light transmittancy of the square areas is different from that of the base. The square areas are arranged on the base with an array arrangement, and the gaps between adjacent square areas are not even. Whereby, the photomask has better normalized image log-slope (NILS) or depth of focus (DOF). | 09-20-2012 |
Chun-Wei Chan, New Taipei City TW
Patent application number | Description | Published |
---|---|---|
20130179710 | MULTI-CORE PROCESSOR SYSTEM, DYNAMIC POWER MANAGEMENT METHOD THEREOF AND CONTROL APPARATUS THEREOF - A multi-core processor system, a dynamic power management method thereof and a control apparatus thereof are provided. In the method, a workload of a multi-core processor during a runtime stage is obtained. Next, a hot-plug operation is respectively performed on a plurality of slave cores according to the workload and a working state of each slave core. Then, a bus master status and the working state of a boot core are monitored to determine whether to power off the boot core, in which the bus master status is generated by combining a plurality of device statuses reflected by a plurality of peripheral devices. Finally, when the bus master status is determined as idle, the boot core is powered off. | 07-11-2013 |
20140115314 | ELECTRONIC DEVICE AND SECURE BOOT METHOD - An embodiment of the invention provides a secure boot method for an electronic device including an embedded controller and a processor. The method includes the steps of verifying a secure loader by the embedded controller, unlocking a peripheral hardware of the electronic device by the embedded controller, and executing the secure loader by the processor. | 04-24-2014 |
Chun-Wei Chang, Taipei City TW
Patent application number | Description | Published |
---|---|---|
20130027877 | ELECTRONIC DEVICE - An electronic device including a main body, a rotating base, a motherboard and a driving module is provided. The rotating base has a first vent. The rotating base is pivoted to the main body and suitable for being rotated between an operating position and a retracting position. When the rotating base is located at the operating position, the first vent is exposed from the main body, and when the rotating base is located at the retracting position, the first vent is retracted in the main body. The driving module includes a controlling element and a first locking element. The controlling element is disposed on the main body and suitable for moving between an enable position and a disable position. The first locking element is connected to the controlling element, and the controlling element drives the first locking element to position the rotating base. | 01-31-2013 |
20130139355 | HINGE MECHANISM AND FOLDABLE ELECTRONIC DEVICE - A hinge mechanism suitable for a foldable electronic device has a first body, a second body and a hinging-body. The hinge mechanism includes a first cradle, a second cradle, a pair of pivoting-shafts, a pair of position-limiting elements, a set of gears and a positioning element. The positioning-element is fixed to the hinging-body and structurally independent from the position-limiting elements, pivoted to the pivoting-shafts so as to be detachably assembled with the position-limiting elements. The first body rotates relatively to the hinging-body through the first cradle rotates the pivoting-shaft fixed to the first cradle relatively to the positioning element so as to rotate the set of gears, make the second cradle rotate the pivoting-shaft fixed to the second cradle relatively to the positioning-element and bring the second body for rotation relatively to the hinging-body. Additionally, a foldable electronic device is also provided. | 06-06-2013 |
20140215286 | SOFT ERROR PROTECTION DEVICE - A soft error protection device is disclosed, which comprises a soft error resilient latch (SERL) and a latch coupled to a detection device and receiving a soft error pulse and a clock (CLK) signal respectively outputted by an electronic element and a CLK generator. The SERL delays the soft error pulse. In the period of a negative level of the CLK signal, the SERL stores the delayed soft error pulse corresponding to the negative level and used as a first detection data. Meanwhile, the latch stores the soft error pulse as a second detection data. The detection device receives the CLK signal, the first and second detection datum, and compares the first and second detection datum to send out a detection signal when the CLK signal rises from the negative level to a positive level. | 07-31-2014 |
Chun-Wei Chang, Taipei County TW
Patent application number | Description | Published |
---|---|---|
20090236707 | ELECTRONIC DEVICES WITH ENHANCED HEAT SPREADING - An electronic device with enhanced heat spread. A printed circuit board is disposed in a casing and includes a first metal ground layer, a second metal ground layer, and a metal connecting portion. The first metal ground layer is opposite the second metal ground layer. The metal connecting portion is connected between the first and second metal ground layers. The second metal ground layer is connected to the casing. A chip is electrically connected to the printed circuit board and includes a die and a heat-conducting portion connected to the die and soldered with the first metal ground layer. Heat generated by the chip is conducted to the casing through the heat-conducting portion, first metal ground layer, metal connecting portion, and second metal ground layer. | 09-24-2009 |
20100283141 | SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package includes a chip; first and second connection pads arranged in a matrix and disposed about the chip, and the first and second connection pads have different bottom surface shapes when viewed from a bottom of the QFN package; bonding pads provided on an active surface of the chip and being electrically connected with corresponding said connection pads through bonding wires; and a package body encapsulating the chip, the bonding wires and an upper portion of each of the connection pads such that a lower portion of each of the connection pads extends outward from a bottom of the package body. | 11-11-2010 |
Chun-Wei Chang, Tainan City TW
Patent application number | Description | Published |
---|---|---|
20130273740 | FILM PORTION AT WAFER EDGE - A film layer on a substrate of the wafer is patterned to form a first plurality of areas of the film layer and a second plurality of areas of the film layer. The first plurality of areas of the film layer is removed. The second plurality of areas of the film layer is kept on the substrate. A first portion of the film layer is kept on the substrate. A first edge of the first portion of the film layer is substantially near an edge of the wafer. The first portion of the film layer defines a boundary for the wafer. | 10-17-2013 |
20140061738 | Method to Form a CMOS Image Sensor - The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions. | 03-06-2014 |
20140065843 | Method of Forming a Photoresist Layer - A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material. | 03-06-2014 |
20140272704 | THICKENING PHASE FOR SPIN COATING PROCESS - Among other things, one or more techniques and systems for performing a spin coating process associated with a wafer and for controlling thickness of a photoresist during the spin coating process are provided. In particular, a thickening phase is performed during the spin coating process in order to increase a thickness of the photoresist. For example, air temperature of down flow air, flow speed of the down flow air, and heat temperature of heat supplied towards the wafer are increased during the thickening phase. The increase in down flow air and heat increase a vaporization factor of the photoresist, which results in an increase in viscosity and thickness of the photoresist. In this way, the wafer can be rotated at relatively lower speeds, while still attaining a desired thickness. Lowering rotational speed of wafers allows for relatively larger wafers to be stably rotated. | 09-18-2014 |
20140272715 | Lithography Process on High Topology Features - A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist. | 09-18-2014 |
20150206873 | Alignment Marks in Non-STI Isolation Formation and Methods of Forming the Same - A method includes forming a photo resist over a semiconductor substrate of a wafer, patterning the photo resist to form a first opening in the photo resist, and implanting the semiconductor substrate using the photo resist as an implantation mask. An implanted region is formed in the semiconductor substrate, wherein the implanted region is overlapped by the first opening. A coating layer is coated over the photo resist, wherein the coating layer includes a first portion in the first opening, and a second portion over the photo resist. A top surface of the first portion is lower than a top surface of the second portion. The coating layer, the photo resist, and the implanted region are etched to form a second opening in the implanted region. | 07-23-2015 |
20150212420 | FILM PORTION AT WAFER EDGE - A method for preparing a wafer includes forming a film layer on a substrate of the wafer; coating the film layer with a photoresist layer; exposing a first portion of the photoresist layer to a beam of light; and patterning a second portion of the photoresist layer after performing exposing the first portion of the photoresist layer. A cross-link reaction is caused on the first portion of the photoresist layer and the first portion of the photoresist layer is converted to a reacted first portion of the photoresist layer. The reacted first portion of the photoresist layer is near an edge of the wafer. The second portion of the photoresist layer is different from the reacted first portion of the photoresist layer. The second portion of the photoresist layer is converted to a patterned second portion of the photoresist layer. | 07-30-2015 |
20150243500 | METHOD OF FORMING A PHOTORESIST LAYER - A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material. | 08-27-2015 |
20150255400 | Method for Forming Alignment Marks and Structure of Same - A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks. | 09-10-2015 |
Chun-Wei Chang, Chung Li TW
Patent application number | Description | Published |
---|---|---|
20110181890 | IMAGING AND MEASURING APPARATUS FOR SURFACE AND INTERNAL INTERFACE OF OBJECT - The present invention provides an imaging and measuring apparatus for the surface and the internal interface of an object, which comprises a broadband wave source, a wave-splitting structure, a wave-delaying device, a reflecting component, and a sensor. The broadband wave source transmits a broadband incident wave. The wave-splitting structure splits the broadband incident wave into a first incident beam, a second incident beam, and a third incident beam. The first incident beam is illuminated on an object under test, which reflects a measuring beam. The wave-delaying device receives the second incident beam and reflects a reference beam. The reflecting component receives the third incident beam and reflects a calibration beam. The sensor receives a first interference signal of the measuring beam and the reference beam, and a second interference signal of the reference beam and the calibration beam. By means of the broadband incident wave, the morphologies of the surface and the internal interface of the object can be imaged and measured in a non-destructive way. In addition, by means of the calibration beam, the accuracy of imaging and measuring the surface and the internal interface of the object can be improved. | 07-28-2011 |
Chun-Wei Chang, New Taipei City TW
Patent application number | Description | Published |
---|---|---|
20110248394 | LEADFRAME PACKAGE FOR HIGH-SPEED DATA RATE APPLICATIONS - A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm. | 10-13-2011 |
20130093073 | HIGH THERMAL PERFORMANCE 3D PACKAGE ON PACKAGE STRUCTURE - A package on package (PoP) structure is disclosed. The PoP structure includes a top package and a bottom package disposed thereunder. The top package includes a first substrate and a first die mounted onto the first substrate. The first substrate has a thermal conductivity which is more than 70 W/(m×K). The bottom package includes a second substrate and a second die mounted onto the second substrate. An upper surface of the second die is in thermal contact with a lower surface of the first substrate. | 04-18-2013 |
20130234668 | UNIVERSAL SERIAL BUS APPARATUS AND POWER SUPPLY METHOD THEREOF - A power supply method for an universal serial bus apparatus is provided. The USB apparatus includes an upstream port module and a plurality of downstream port modules. The power supply method comprises the following steps: setting a maximum charging port number for the downstream port modules according to the connection configuration between the upstream port module and a host, and the condition of power supply from an external power supply; detecting the coupling condition of the electronic apparatuses to the downstream port modules so as to customize a specific charging specification for one of the electronic apparatuses; respectively providing a plurality of power to the electronic apparatuses according to the specific charging specification and the maximum charging port number. Thus, the electronic apparatuses enable to be charged with maximum charging currents and operate normally under the USB specification without being affected. | 09-12-2013 |
20140252659 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad. | 09-11-2014 |
20140312482 | WAFER LEVEL ARRAY OF CHIPS AND METHOD THEREOF - A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided. | 10-23-2014 |
20140319668 | HIGH THERMAL PERFORMANCE 3D PACKAGE ON PACKAGE STRUCTURE - A package on package (PoP) structure is disclosed. The PoP structure comprises a top package and a bottom package disposed thereunder. The top package comprises a first substrate and a first die mounted onto the first substrate. At least one electrically floating pad is disposed on a lower surface of the first substrate. The bottom package comprises a second substrate and a second die mounted onto the second substrate. An upper surface of the second die is in thermal contact with the electrically floating pad. | 10-30-2014 |
20150097299 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A method for forming a chip package is provided. A first substrate is provided. A second substrate is attached on the first substrate, wherein the second substrate has a plurality of rectangular chip regions separated by a scribed-line region. A portion of the second substrate corresponding to the scribed-line region is removed to form a plurality of chips on the first substrate, wherein at least one bridge portion is formed between adjacent chips. A chip package formed by the method is also provided. | 04-09-2015 |
20150189773 | COVER OPENING STRUCTURE - A cover opening structure including a case, a cover, a pushing button, a pushing unit and an axle is provided. The cover has a first portion having a first side, a second portion having a second side connected to the case, and a connecting portion connected therebetween, wherein the connecting portion is softer than the first and second portions. The pushing button disposed on the case has a body and an inserting portion extended from the body. The pushing unit has a first end, a second end and a leaning portion connected therebetween and is inserted between the body and the first end. The axle is disposed at the case while the leaning portion leans against the axle. The pushing unit rotates about the axle while the first end moves downward and the second end moves upward to push up the first portion when the pushing button is moved. | 07-02-2015 |
Chun-Wei Chang, New Taipei TW
Patent application number | Description | Published |
---|---|---|
20140294537 | FASTENING DEVICE AND FASTERNER FOR FAN - A fastener includes a resilient head, a position pole extending out from a first end of the head, and a resilient latching portion protruding out from the position pole away from the head. A circumference of the head defines a mounting slot. A second end of the head opposite to the position pole defines an operation hole extending to the position pole. | 10-02-2014 |
Chun-Wei Chang, Hsinchu TW
Patent application number | Description | Published |
---|---|---|
20140254038 | COLOR FILTER AND DISPLAY - A color filter provided in the invention includes a substrate, a first color filter pattern and a second color filter pattern. The substrate has at least one first pixel region and at least one second pixel region adjacent to the first pixel region. The first color filter pattern is disposed on the substrate and includes a first central pattern and first protruding patterns connected to the first central pattern and protruding outwardly from the first central pattern so that a portion of the first protruding patterns are located in the second pixel region. The second color filter pattern includes a second central pattern located within the second pixel region. | 09-11-2014 |
20150076536 | LIGHT-EMITTING ELEMENT HAVING A PLURALITY OF LIGHT-EMITTING STRUCTURES - A light-emitting element comprises a first semiconductor layer, a first light-emitting structure and a second light-emitting structure on the first semiconductor layer, a first electrode on the first semiconductor layer, a second electrode on the first light-emitting structure, and a first trench between the first light-emitting structure and the second light-emitting structure, exposing the first semiconductor layer, wherein the first trench is devoid of the first electrode and the second electrode formed therein. | 03-19-2015 |
20150123152 | LIGHT-EMITTING ELEMENT - A light-emitting element includes a light-emitting stacked layer including an upper surface, wherein the upper surface includes a first flat region; a protective layer including a current blocking region on the first flat region; and a cap region on the upper surface, wherein the current blocking region is spatially separate from the cap region; and a first electrode covering the current blocking region. | 05-07-2015 |
Chun-Wei Chang, Hsinchu City TW
Patent application number | Description | Published |
---|---|---|
20090268907 | Optical Media Recording Device for Protecting Device Keys and Related Method - To protect device keys, an optical media recording device capable of performing AACS encryption on data does not have any device keys, and the optical media recording device performs AACS encryption by activating recording software stored in a memory the optical media recording device, and utilizing a pre-calculated media key stored in the memory of the optical media recording device to perform AACS encryption on the data. | 10-29-2009 |
20140110741 | LIGHT-EMITTING DEVICE - A light-emitting device, includes: a substrate; a light-emitting structure formed on the substrate and including a first portion, and a second portion where no optoelectronic conversion occurs therein; and a first electrode located on both the first portion and the second portion. | 04-24-2014 |
20160086978 | DISPLAY - A display is disclosed. The display includes a display panel including pixel units in an image-displaying region. Each of the pixel units includes an AND gate and a pixel electrode electrically connected to an output terminal of the AND gate. | 03-24-2016 |
Chun-Wei Hsu, Taipei City TW
Patent application number | Description | Published |
---|---|---|
20120264302 | CHEMICAL MECHANICAL POLISHING PROCESS - A chemical mechanical polishing (CMP) process includes steps of providing a substrate, performing a first polishing step to the substrate with an acidic slurry, and performing a second polishing step to the substrate with a basic slurry after the first polishing step. | 10-18-2012 |
20120322265 | POLY OPENING POLISH PROCESS - A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit. | 12-20-2012 |
20120326238 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region thereon; forming a high-k dielectric layer, a barrier layer, and a first metal layer on the substrate; removing the first metal layer of the second region; forming a polysilicon layer to cover the first metal layer of the first region and the barrier layer of the second region; patterning the polysilicon layer, the first metal layer, the barrier layer, and the high-k dielectric layer to form a first gate structure and a second gate structure in the first region and the second region; and forming a source/drain in the substrate adjacent to two sides of the first gate structure and the second gate structure. | 12-27-2012 |
20120329261 | MANUFACTURING METHOD FOR METAL GATE - A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function. | 12-27-2012 |
20130015524 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOFAANM Hsu; Chun-WeiAACI Taipei CityAACO TWAAGP Hsu; Chun-Wei Taipei City TWAANM Huang; Po-ChengAACI Chiayi CityAACO TWAAGP Huang; Po-Cheng Chiayi City TWAANM Tsai; Teng-ChunAACI Tainan CityAACO TWAAGP Tsai; Teng-Chun Tainan City TWAANM Hsu; Chia-LinAACI Tainan CityAACO TWAAGP Hsu; Chia-Lin Tainan City TWAANM Lin; Chih-HsunAACI Ping-Tung CountyAACO TWAAGP Lin; Chih-Hsun Ping-Tung County TWAANM Chen; Yen-MingAACI New Taipei CityAACO TWAAGP Chen; Yen-Ming New Taipei City TWAANM Chen; Chia-HsiAACI Kao-Hsiung CityAACO TWAAGP Chen; Chia-Hsi Kao-Hsiung City TWAANM Kung; Chang-HungAACI Kaohsiung CityAACO TWAAGP Kung; Chang-Hung Kaohsiung City TW - A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate. | 01-17-2013 |
20130020657 | METAL OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor. | 01-24-2013 |
20130052825 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer. | 02-28-2013 |
20130059544 | METHOD AND DEVICE FOR DETERMINISTIC DIRECTIONAL DISCOVERY OF WIRELESS DEVICES - A method for deterministic directional discovery of neighbor devices by a device in a wireless network comprises dividing equally an access time to a discovery channel to predefined number of sector scanning periods ( | 03-07-2013 |
20130105912 | SEMICONDUCTOR DEVICE | 05-02-2013 |
20140035070 | METAL OXIDE SEMICONDUCTOR TRANSISTOR - A MOS transistor including a silicon substrate, a first gate structure and a second gate structure disposed on the silicon substrate is provided. The first gate structure and the second gate structure each includes a high-k dielectric layer disposed on the silicon substrate, a barrier layer disposed on the high-k dielectric layer, and a work function layer disposed on and contacted with the barrier layer. The MOS transistor further includes a dielectric material spacer. The dielectric material spacer is disposed on the barrier layer of each of the first gate structure and the second gate structure and surrounding the work function layer of each of the first gate structure and the second gate structure. | 02-06-2014 |
20140094017 | MANUFACTURING METHOD FOR A SHALLOW TRENCH ISOLATION - A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided. | 04-03-2014 |
20140106558 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate. | 04-17-2014 |
20140273371 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the resistor region of the substrate; forming a tank in the STI; and forming a resistor in the tank and on two sides of the top surface of the STI outside the tank. | 09-18-2014 |
Chun-Wei Hsu, Taoyuan County TW
Patent application number | Description | Published |
---|---|---|
20140009362 | MOBILE COMMUNICATION DEVICE AND IMPEDANCE MATCHING METHOD THEREOF - A mobile communication device and an impedance matching method thereof are provided. The mobile communication device includes an antenna, a power amplifier, a tunable matching circuit, a power detection circuit and a controller. The tunable matching circuit determines an output impedance encountered by a radio frequency (RF) signal transmitted by the power amplifier to the antenna when the RF signal enters the tunable matching circuit. The power detection circuit detects a forward power of the RF signal entering the antenna and a reflected power of the antenna. The controller tunes the tunable matching circuit according to a frequency range currently used by the mobile communication device, the forward power and the reflected power to steer the output impedance toward a corresponding load-pull impedance that the power amplifier has in the frequency range. | 01-09-2014 |
20140315546 | METHOD FOR SEARCHING WIRELESS SIGNAL, MOBILE ELECTRONIC DEVICE USING THE SAME, AND NON-TRANSITORY STORAGE MEDIUM - A method for searching wireless signal, a mobile electronic device using the same, and a non-transitory storage medium are provided. In the method, after a motion sensor of the mobile electronic device is activated, a motion status of the mobile electronic device is determined by using the motion sensor. Then, a frequency of the mobile electronic device performing a wireless signal searching procedure is adjusted according to the motion status, so as to reduce power wasted due to the unnecessary wireless signal searching procedure being performed. | 10-23-2014 |
Chun-Wei Hsu, Taichung City TW
Patent application number | Description | Published |
---|---|---|
20130015460 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAMEAANM CHEN; Po-ChihAACI Hsinchu CityAACO TWAAGP CHEN; Po-Chih Hsinchu City TWAANM YU; Jiun-Lei JerryAACI Zhudong TownshipAACO TWAAGP YU; Jiun-Lei Jerry Zhudong Township TWAANM YAO; Fu-WeiAACI Hsinchu CityAACO TWAAGP YAO; Fu-Wei Hsinchu City TWAANM HSU; Chun-WeiAACI Taichung CityAACO TWAAGP HSU; Chun-Wei Taichung City TWAANM YANG; Fu-ChihAACI Fengshan CityAACO TWAAGP YANG; Fu-Chih Fengshan City TWAANM TSAI; Chun LinAACI HsinchuAACO TWAAGP TSAI; Chun Lin Hsinchu TW - An embodiment of the disclosure includes a semiconductor structure. The semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. An interface is defined between the first III-V compound layer and the second III-V compound layer. A gate is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on opposite side of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second III-V compound layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface. | 01-17-2013 |
20130069116 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A semiconductor structure is disclosed. The semiconductor structure includes a first layer. A second layer is disposed on the first layer and different from the first layer in composition. An interface is between the first layer and the second layer. A third layer is disposed on the second layer. A gate is disposed on the third layer. A source feature and a drain feature are disposed on opposite sides of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second and the third layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface. | 03-21-2013 |
20130087804 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A carrier channel depleting layer is disposed on the second III-V compound layer. The carrier channel depleting layer is deposited using plasma and a portion of the carrier channel depleting layer is under at least a portion of the gate electrode. | 04-11-2013 |
20130105808 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME | 05-02-2013 |
20130112986 | Gallium Nitride Semiconductor Devices and Method Making Thereof - The present disclosure relates to an enhancement mode gallium nitride (GaN) transistor device. The GaN transistor device has an electron supply layer located on top of a GaN layer. An etch stop layer (e.g., AlN) is disposed above the electron supply layer. A gate structure is formed on top of the etch stop layer, such that the bottom surface of the gate structure is located vertically above the etch stop layer. The position of etch stop layer in the GaN transistor device stack allows it to both enhance gate definition during processing (e.g., selective etching of the gate structure located on top of the AlN layer) and to act as a gate insulator that reduces gate leakage of the GaN transistor device. | 05-09-2013 |
20130134435 | HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE WITH IMPROVED BREAKDOWN VOLTAGE PERFORMANCE - A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided. | 05-30-2013 |
20130134482 | SUBSTRATE BREAKDOWN VOLTAGE IMPROVEMENT FOR GROUP III-NITRIDE ON A SILICON SUBSTRATE - A method of making a high-electron mobility transistor (HEMT) includes forming an unintentionally doped gallium nitride (UID GaN) layer over a silicon substrate, a donor-supply layer over the UID GaN layer, a gate, a passivation layer over the gate and portions of the donor-supply layer, an ohmic source structure and an ohmic drain structure over the donor-supply layer and portions of the passivation layer. The source structure includes a source contact portion and an overhead portion. The overhead portion overlaps the passivation layer between the source contact portion and the gate, and may overlap a portion of the gate and a portion of the passivation layer between the gate and the drain structure. | 05-30-2013 |
20130140578 | CIRCUIT STRUCTURE HAVING ISLANDS BETWEEN SOURCE AND DRAIN - A circuit structure includes a substrate, an unintentionally doped gallium nitride (UID GaN) layer over the substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. A number of islands are over the donor-supply layer between the gate structure and the drain. The gate structure disposed between the drain and the source. The gate structure is adjoins at least a portion of one of the islands and/or partially disposed over at least a portion of at least one of the islands. | 06-06-2013 |
20130161638 | HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE WITH IMPROVED BREAKDOWN VOLTAGE PERFORMANCE - A HEMT includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer, and a passivation material layer having one or more buried portions contacting or almost contacting the UID GaN layer. A carrier channel layer at the interface of the donor-supply layer and the UID GaN layer has patches of non-conduction in a drift region between the gate and the drain. A method for making the HEMT is also provided. | 06-27-2013 |
20130168685 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. The gate electrode includes a refractory metal. A depletion region is disposed in the carrier channel and under the gate electrode. | 07-04-2013 |
20130168686 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. Each of the source feature and the drain feature comprises a corresponding intermetallic compound at least partially embedded in the second III-V compound layer. Each intermetallic compound is free of Au and comprises Al, Ti or Cu. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A depletion region is disposed in the carrier channel and under the gate electrode. | 07-04-2013 |
20130221364 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. Two slanted field plates are disposed on the two side walls of the combined opening of the opening in a protection layer and the opening in a dielectric cap layer disposed on the second III-V compound layer. | 08-29-2013 |
20130240952 | PLASMA PROTECTION DIODE FOR A HEMT DEVICE - The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. A first III-V compound layer is disposed over the silicon substrate. A second III-V compound layer is disposed over the first III-V compound layer. The semiconductor device includes a transistor disposed over the first III-V compound layer and partially in the second III-V compound layer. The semiconductor device includes a diode disposed in the silicon substrate. The semiconductor device includes a via coupled to the diode and extending through at least the first III-V compound layer. The via is electrically coupled to the transistor or disposed adjacent to the transistor. | 09-19-2013 |
20130256679 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature. | 10-03-2013 |
20140021560 | HIGH VOLTAGE DEVICE WITH A PARALLEL RESISTOR - Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart. | 01-23-2014 |
20140170819 | HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE WITH IMPROVED BREAKDOWN VOLTAGE PERFORMANCE - A method comprises epitaxially growing a gallium nitride (GaN) layer over a silicon substrate, epitaxially growing a donor-supply layer over the GaN layer, and etching a portion of the donor-supply layer. The method also comprises depositing a passivation layer over the donor-supply layer and filling the etched portion of the donor-supply layer, forming a source and a drain on the donor-supply layer, and forming a gate structure between the source and the etched portion of the donor-supply layer. The method further comprises depositing contacts over the gate structure, the source, and the drain. | 06-19-2014 |
20140187002 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure having a substrate is disclosed. The semiconductor structure includes a first layer formed in contact with the substrate. The first layer made of a first III-V semiconductor material selected from GaN, GaAs and InP. A second layer is formed on the first layer. The second layer made of a second III-V semiconductor material selected from AlGaN, AlGaAs and AlInP. An interface is between the first layer and the second layer forms a carrier channel. An insulating layer is formed on the second layer. Portions of the insulating layer and the second layer are removed to expose a top surface of the first layer. A metal feature is formed in contact with the carrier channel and the metal feature is annealed to form a corresponding intermetallic compound. | 07-03-2014 |
20140242761 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A method of forming a semiconductor structure, the method includes epitaxially growing a second III-V compound layer on a first III-V compound layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. The method further includes forming a source feature and a drain feature on the second III-V compound layer, forming a third III-V compound layer on the second III-V compound layer, depositing a gate dielectric layer on a portion of the second III-V compound layer and a top surface of the third III-V compound layer, treating the gate dielectric layer on the portion of the second III-V compound layer with fluorine and forming a gate electrode on the treated gate dielectric layer between the source feature and the drain feature. | 08-28-2014 |
20140361310 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is over the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located at an interface of the first III-V compound layer and the second III-V compound layer. A dielectric cap layer is over the second III-V compound layer and a protection layer is over the dielectric cap layer. Slanted field plates are in a combined opening in the dielectric cap layer and protection layer. | 12-11-2014 |
20140370677 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor structure includes forming a second III-V compound layer over a first III-V compound layer, wherein a carrier channel is located between the first III-V compound layer and the second III-V compound layer. The method further includes forming a source feature and a drain feature over the second III-V compound layer. The method further includes forming a gate dielectric layer over the second III-V compound layer, wherein the gate dielectric layer is over a top surface of the source feature and over a top surface of the drain feature. The method further includes treating a portion of the gate dielectric layer with fluorine, wherein treating the portion of the gate dielectric layer comprises performing an implantation process using at least one fluorine-containing compound. The method further includes forming a gate electrode over the portion of the gate dielectric layer. | 12-18-2014 |
20150056766 | METHOD OF MAKING HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE - A method includes epitaxially growing a gallium nitride (GaN) layer over a silicon substrate. The method further includes epitaxially growing a donor-supply layer over the GaN layer. The method further includes forming a source and a drain on the donor-supply layer. The method further includes forming a gate structure between the source and the drain on the donor-supply layer. The method further includes plasma etching a portion of a drift region of the donor-supply layer to a depth of less than 60% of a donor-supply layer thickness. The method further includes depositing a dielectric layer over the donor-supply layer. | 02-26-2015 |
20150076563 | METHOD OF MAKING A CIRCUIT STRUCTURE HAVING ISLANDS BETWEEN SOURCE AND DRAIN AND CIRCUIT FORMED - A method of making a circuit structure includes growing a bulk layer over a substrate, and growing a donor-supply layer over the bulk layer. The method further includes depositing a doped layer over the donor-supply layer, and patterning the doped layer to form a plurality of islands. The method further includes forming a gate structure over the donor-supply layer, wherein the gate structure is partially over a largest island of the plurality of islands. The method further includes forming a drain over the donor-supply layer, wherein at least one island of the plurality of islands is between the gate structure and the drain. | 03-19-2015 |
20150115328 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A semiconductor structure comprises a first layer. The first layer comprises a first III-V semiconductor material. The semiconductor structure also comprises a second layer over the first layer. The second layer comprises a second III-V semiconductor material different from the first III-V semiconductor material. The semiconductor structure further comprises an insulating layer over the second layer. The insulating layer is patterned to expose a portion of the first layer. The exposed portion of the first layer comprises electrons of the second layer. The semiconductor structure additionally comprises an intermetallic compound over the exposed portion of the first layer. | 04-30-2015 |
20150140745 | METHOD OF FORMING A HIGH ELECTRON MOBILITY TRANSISTOR - A method of forming a high electron mobility transistor (HEMT) includes forming a second III-V compound layer on a first III-V compound layer, forming a source feature and a drain feature on the second III-V compound layer, depositing a p-type layer on a portion of the second III-V compound layer between the source feature and the drain feature, and forming a gate electrode on the p-type layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. | 05-21-2015 |
20150349087 | METHOD OF FORMING HIGH ELECTRON MOBILITY TRANSISTOR - A method of forming a high electron mobility transistor (HEMT) includes epitaxially growing a second III-V compound layer on a first III-V compound layer. The method further includes partially etching the second III-V compound layer to form two through holes in the second III-V compound layer. Additionally, the method includes forming a silicon feature in each of two through holes. Furthermore, the method includes depositing a metal layer on each silicon feature. Moreover, the method includes annealing the metal layer and each silicon feature to form corresponding salicide source/drain features. The method also includes forming a gate electrode over the second III-V compound layer between the salicide source/drain features. | 12-03-2015 |
20150357453 | CIRCUIT STRUCTURE, TRANSISTOR AND SEMICONDUCTOR DEVICE - A circuit structure includes a substrate, a III-V semiconductor compound over the substrate, a Al | 12-10-2015 |
20160005823 | HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE AND METHOD OF MAKING THE SAME - A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view. | 01-07-2016 |
20160027698 | PLASMA PROTECTION DIODE FOR A HEMT DEVICE - A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer. | 01-28-2016 |
20160049505 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor structure includes growing a second III-V compound layer over a first III-V compound layer, wherein the second III-V compound layer has a different band gap from the first III-V compound layer. The method further includes forming a source feature and a drain feature over the second III-V compound layer. The method further includes forming a gate dielectric layer over the second III-V compound layer, the source feature and the drain feature. The method further includes implanting at least one fluorine-containing compound into a portion of the gate dielectric layer. The method further includes forming a gate electrode over the portion of the gate dielectric layer. | 02-18-2016 |
Chun-Wei Huang, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110298770 | ACTIVE MATRIX DISPLAY DEVICE - An exemplary active matrix display device includes a plurality of gate signal lines, a plurality of data signal lines and a plurality of pixel rows. The gate signal lines are independently driven from one another. Each of the pixel rows is electrically coupled to one of the gate signal lines and a part of the data signals lines. The pixel rows include a first pixel row and a second pixel row. The first pixel row and the second pixel row are not neighboring with each other. The gate signal line electrically coupled with the first pixel row and the gate signal line electrically coupled with the second pixel row are synchronously enabled. | 12-08-2011 |
Chun-Wei Huang, Tainan City TW
Patent application number | Description | Published |
---|---|---|
20140329149 | METHOD FOR PREPARING ELECTRODE MATERIALS AND ELECTRODE MATERIALS PRODUCED THEREFROM - The present invention provides a method for preparing an electrode material, comprising providing an acidic plating bath; adding titanium dioxide in the form of powder, metal salt, and reductant to said acidic plating bath to obtain a precursor; and heat treating said precursor to obtain an electrode material. When the electrode material obtained by said method is applied to batteries, the batteries have not only high capacity, but also long lifetime. | 11-06-2014 |
Chun-Wei Huang, Lukang Town TW
Patent application number | Description | Published |
---|---|---|
20160064195 | Plasma Treatment Of An Elastomeric Material For Adhesion - Elastomeric components, such as a shoe outsole, are treated with a plasma application to clean and activate the elastomeric component. The application of plasma is controlled to achieve a sufficient surface composition change to enhance adhesion characteristics while not adversely physically deforming the elastomeric component. The plasma treatment is applied to increase carbonyl functional group concentrations within an altered region of the elastomeric component to within at least a range of 2%-15% of carbon atomic percentage composition. The cleaning and activation is controlled, in part, by ensuring a defined height offset range is maintained between the elastomeric component and the plasma source by a generated tool path. The elastomeric component may then be adhered, with an adhesive, to another component. | 03-03-2016 |
Chun-Wei Huang, Hsinchu County TW
Patent application number | Description | Published |
---|---|---|
20140306676 | COMPENSATION MODULE and VOLTAGE REGULATOR - A compensation module for a voltage regulation device having a gain stage, an output stage and a miller compensation module includes a low-output-impedance non-inverting amplifier unit coupled to a gain output of the gain stage and an output-stage input of the output stage. | 10-16-2014 |
20150042297 | Voltage Converting Device and Electronic System thereof - A voltage converting device with a self-reference feature for an electronic system includes a differential current generating module, implemented in a Complementary metal-oxide-semiconductor (CMOS) processing for generating a differential current pair according to a converting voltage; and a voltage converting module, coupled to the differential current generating module, a first supply voltage and a second supply voltage of the electronic system for generating the converting voltage according to the differential current pair, the first supply voltage and the second supply voltage. | 02-12-2015 |
Chun-Wei Huang, Hsinchu TW
Patent application number | Description | Published |
---|---|---|
20090189925 | LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF - A liquid crystal display (LCD) and a driving method thereof are provided. The driving method includes the steps of: transmitting video data to the LCD according to a first frequency, and processing the video data according to a first gamma look-up table to obtain a bright region image; transmitting the video data to the LCD according to the first frequency, and processing the video data according to a second gamma look-up table to obtain a dark region image; and stacking the bright region image and the dark region image in sequence so as to display an image displayed on an LCD panel of the LCD. | 07-30-2009 |
Chun-Wei Huang, Taichung City TW
Patent application number | Description | Published |
---|---|---|
20150231657 | NOZZLE HAVING REAL TIME INSPECTION FUNCTIONS - A nozzle for emitting a fluid comprises a channel, a light source and a light sensor. The channel is configured to flow the fluid. The light source is configured to emit light towards a surface on which the fluid is applied and the light sensor is configured to receive reflected light from the surface. | 08-20-2015 |
Chun-Wei Huang, Chang Hwa TW
Patent application number | Description | Published |
---|---|---|
20120118115 | DUAL-PURPOSE PLIERS FOR CONNECTING AND DISCONNECTING A MASTER LINK OF A CHAIN - A pair of dual-purpose pliers for connecting and disconnecting a master link of a chain comprises a single jaw handle and a double-jaw handle. The single jaw handle is formed with a grip at a first end thereof and a single jaw at a second end thereof. The double jaw handle is formed with a grip at a first end thereof and a left jaw and a right jaw at a second end thereof. After the single jaw handle and the double jaw handle are pivotally connected, the single jaw is located between the left and the right jaws, a groove of the single jaw and a groove of the left jaw are arranged in a face-to-face manner, and the groove of the single jaw and a groove of the right jaw are arranged in back-to-back manner. | 05-17-2012 |
Chun-Wei Kuo, Dasi Township TW
Patent application number | Description | Published |
---|---|---|
20090309481 | Field emission device and method for fabricating cathode emitter and zinc oxide anode - The present invention relates to methods for fabricating a cathode emitter and a zinc oxide anode for a field emission device to improve the adhesion between emitters and a substrate and enhance the luminous efficiency of a zinc oxide thin film so that the disclosed methods can be applied in displays and lamps. In comparison to a conventional method for fabricating a field emission device, the method according to the present invention can reduce the cost and time for manufacture and is suitable for fabricating big-sized products. In addition, the present invention further discloses a field emission device comprising a zinc oxide/nano carbon material cathode, a zinc oxide anode and a spacer. | 12-17-2009 |
Chun-Wei Lee, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20130176729 | LENS STRUCTURE, LIGHT SOURCE DEVICE AND LIGHT SOURCE MODULE - A lens structure, a light source device, and a light source module are provided. The light source device includes a light emitting device and a lens structure. The light emitting device is capable of emitting a light beam. The lens structure includes a first surface, a second surface opposite to the first surface and four total internal reflection surfaces connected to the second surface. Some of the total internal reflection surfaces connect to the first surface. The first surface has a recess. The light emitting device is disposed at the recess. The second surface is a free-form surface. The light beam is capable of entering the lens structure through the first surface, and leaving the lens structure through the second surface. | 07-11-2013 |
Chun-Wei Lee, Hsinchu TW
Patent application number | Description | Published |
---|---|---|
20150018247 | METHOD OF MANUFACTURING BIOMEDICAL MOLECULAR DETECTION PLATFORM AND THE DETECTION PLATFORM MANUFACTURED THEREFROM - The present invention provides a method of manufacturing biomedical molecular detection platform, comprising providing a plurality of reagent droplets on a first surface of a substrate; forming a plurality of hydrophilic regions and a water-repellant region on a second surface of a test paper, and the plurality of hydrophilic regions separated individually by the water-repellant region; and contacting the first surface of the substrate with the second surface of the test paper for transferring each reagent droplet on the substrate to each hydrophilic region of the test paper. The present invention also provides a biomedical molecular detection platform manufactured therefrom. The method of present invention can rapidly manufacture large quantity of biomedical molecular detection platforms, and the biomedical molecular detection platform can be used to any test that use pigmentation to determine results. | 01-15-2015 |
Chun-Wei Li, Chu-Nan TW
Patent application number | Description | Published |
---|---|---|
20100035380 | Method for fabricating package structure of stacked chips - The invention relates to a method for fabricating a package structure of stacked chips, comprising the following steps: firstly, providing a substrate; attaching a first chip and a second chip on the upper surface of the substrate, in which the second chip is stacked on the upper side of the first chip; then connecting a first bonding wire between a second solder pad of the second chip and a first region of a first solder pad of the first chip; and connecting a second bonding wire between a second region of the first solder pad of the first chip and the metal contact of the substrate, whereby the invention is capable of tremendously reducing the volume as a whole, effectively solving the problem of having much bonding wire circuit, and reducing the volume and quantity occupied by the solder pads on the substrate, thereby reducing complexity of the circuit layout on the substrate. | 02-11-2010 |
Chun-Wei Liang, New Taipei City TW
Patent application number | Description | Published |
---|---|---|
20120182757 | LIGHT-GUIDE TYPE ILLUMINATION DEVICE - A light-guide type illumination device includes a heat-dissipating unit, a conductive unit, a light-emitting unit and a light-guiding unit. The heat-dissipating unit includes a heat-dissipating body. The conductive unit and the light-emitting unit are respectively disposed on a first side and a second side of the heat-dissipating body. The light-emitting unit includes at least one light-emitting element electrically connected to the conductive unit for generating light beams. The light-guiding unit includes at least one light-guiding element disposed above the light-emitting unit. The light-guiding element has a light input surface formed on a bottom side thereof for receiving the light beams and an optical surface-treated layer formed on at least one lateral surface thereof. Hence, the instant disclosure can provide an annular 360-degree light-emitting range by matching the light-emitting unit and the light-guiding unit, thus any type of conventional energy-saving bulb can be replaced by the illumination device. | 07-19-2012 |
20120320580 | LIGHT-GUIDING COVER AND ILLUMINATION DEVICE HAVING THE SAME - The present invention relates to a light-guiding cover and an illumination device having the same. The light-guiding cover, for guiding light beams emitted by at least one light-emitting diode (LED), has a light-guiding portion and a light output portion. The light-guiding portion has a light input surface for transmitting light beams thereto and a connecting surface. The light output portion formed on one end of the light-guiding portion has an optical surface adjoining the connecting surface. The light-guiding cover is substantially symmetrical and defines a central axis. The light beams received by the light-guiding portion are guided by the light input surface for light reflection from one side to another side of the optical surface across the central axis to exit from the light-output portion. Thus, the illumination device having the light-guiding cover can illuminate in an omni-directional manner. | 12-20-2012 |
20140211481 | LIGHT-GUIDING COVER AND ILLUMINATION DEVICE HAVING THE SAME - A light-guiding cover includes a light input surface defining a central axis and a light output surface. The light-guiding cover has a reflecting portion formed therein and substantially symmetrical about the central axis. The reflecting portion surrounding the central axis has an outer reflecting surface and an inner reflecting surface. The light input surface is defined into two regions, an inner region and an outer region, by the reflecting portion. The outer reflecting surface of the reflecting portion is arranged away from the central axis, the inner reflecting surface of the reflecting portion is arranged near to the central axis. Thus, the light-guiding cover of the instant disclosure can guide the light beams emanated from a LED to travel in certain optical paths and provide uniformly distributed lighting. Moreover, the instant disclosure also provides an illumination device having the light-guiding cover that can omni-directionally illuminate. | 07-31-2014 |
Chun-Wei Lin, Douliu City TW
Patent application number | Description | Published |
---|---|---|
20130093489 | SIGNAL CONVERTER EQUIPPED WITH OVERVOLTAGE PROTECTION MECHANISM - A signal converter equipped with an overvoltage protection mechanism includes a pulse width modulation unit, a timing processing unit, an overvoltage detection unit, a pulse width control unit and a multi-level conversion unit. The pulse width modulation unit converts an analog signal into a pulse signal. The timing processing unit converts the pulse signal into a digital signal and outputs the digital signal to the overvoltage detection unit. When the digital signal is higher than the maximum limitation or less than the minimum limitation, the overvoltage detection unit outputs an over-threshold signal to the pulse width control unit to allow the pulse width modulation unit to perform feedback adjustment and prevent the multilevel conversion unit connected to the timing processing unit from causing burnout of downstream circuits because the multilevel conversion unit outputs maximum power intensity of signal over a long time. | 04-18-2013 |
Chun-Wei Lin, Wu-Jih Hsiang TW
Patent application number | Description | Published |
---|---|---|
20090297794 | LAMINATE AND ARTICLE FOR DAILY USE - A laminate includes a base layer being made from one of woven fabrics, knitted fabrics, and non-woven fabrics, and having two surfaces, and a thin film layer made of a polyvinyl butyral-based composition and covering one of the two surfaces of the base layer. An article for daily use, at least one part of which is made of the laminate, is also disclosed. | 12-03-2009 |
Chun-Wei Lin, Taoyuan County TW
Patent application number | Description | Published |
---|---|---|
20090284491 | METHOD FOR FILTERING SIGNALS OF TOUCH SENSITIVE DEVICE - A method for filtering signals of a touch sensitive device is used to judge whether or not a touch signal output from a touch sensitive device is noise by utilize the arrangement pattern of sensing areas. If the sensing areas corresponding to the touch signal are arranged partially conforming to a noise arrangement pattern the touch signal will be discarded. The present invention uses a scheme of comparing the arrangement diagram of a touch signal with a plurality of noise arrangement patterns to decide whether or not to discard the touch signal so as to increase the accuracy and the stability of a capacitive touch sensitive device. | 11-19-2009 |
20150034778 | HOLDER STAND - A holder stand includes an adjustable support arm assembly, a holder member pivotally connected to one end of the support arm assembly by a ball-and-socket joint for holding a mobile electronic device, a base member defining a position-limited groove and two retaining holes at two opposite sides of the position-limited groove, and a mating connection block assembly including a housing pivotally connected to an opposite end of the support arm assembly and detachably insertable into the position-limited groove of the base member, two spring members mounted in the housing and two press members coupled to two opposite lateral sides of the housing and respectively forced by the spring members into engagement with the retaining holes of the base member to releasably lock the mating connection block assembly to the base member. | 02-05-2015 |
Chun-Wei Lin, Taipei County TW
Patent application number | Description | Published |
---|---|---|
20080219829 | Conveying and stacking device for corrugated boards - The present invention discloses a conveying and stacking device for corrugated boards, which is used in a conveyor of a corrugated board production line to stack corrugated boards by a specified number and comprises an exhaust facing the downstream of the conveyor and a sucker arranged at the upstream of the exhaust and facing the procession of the corrugated boards. The sucker and the exhaust are arranged in an elevator for elevating the corrugated boards and respectively suck air and exhaust air simultaneously. | 09-11-2008 |
Chun-Wei Lin, Tainan County TW
Patent application number | Description | Published |
---|---|---|
20120187107 | SYSTEM AND METHOD FOR CONTROLLING QUASI-RESONANT INVERTER AND ELECTRIC HEATING DEVICE EMPLOYING THE SAME - A quasi-resonant inverter control system includes a mains zero-crossing detection circuit and a controller. The mains zero-crossing detection circuit is operable to detect a plurality of zero-crossing points of an input alternating-current voltage and output a zero-crossing detection signal based on the zero-crossing points. The controller is operable to control a plurality of burst mode period and receives the zero-crossing detection signal. Each of the burst mode periods includes a working duration and a non-working duration. Each of the working durations includes a start point and an end point. The controller is operable to determine the start points and the end points of the working durations based on the zero-crossing detection signal and outputs a control signal based on the start points and the end points of the working durations. An electric heating device and a method for controlling the quasi-resonant inverter are also disclosed herein. | 07-26-2012 |
Chun-Wei Lin, Taipei TW
Patent application number | Description | Published |
---|---|---|
20120216167 | Routing Method for Flip Chip Package and Apparatus Using the Same - Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads. | 08-23-2012 |
20140033156 | ROUTING METHOD FOR FLIP CHIP PACKAGE AND APPARATUS USING THE SAME - Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads. | 01-30-2014 |
Chun-Wei Lin, Daxi Township TW
Patent application number | Description | Published |
---|---|---|
20110099133 | Systems and methods for capturing and managing collective social intelligence information - A method for capturing and managing training data collected online includes: receiving a first dataset from one or more online sources; sampling the first dataset and generating a second dataset, the second dataset including the data sampled from the first dataset; receiving an annotated second dataset with predefined labels; and dividing the annotated second dataset into a training dataset and a test dataset. The disclosed method further includes: configuring a machine learning based classifier based on the training dataset; predicting at least one data point based on the training dataset and calculating a confidence score; comparing the at least one predicted data point to the test dataset; sorting the at least one predicted data point based on its confidence score; and receiving corrected training data associated with the at least one predicted data point. | 04-28-2011 |
20110112995 | Systems and methods for organizing collective social intelligence information using an organic object data model - A method for capturing and organizing intelligence data using an organic data model includes: receiving one or more webpages containing social intelligence data; segmenting content of the one or more webpages containing social intelligence data; identifying named entities in the segmented content of the one or more webpages; identifying topics in the segmented content of the one or more webpages; identifying opinions in the segmented content of the one or more webpages; integrating the identified named entities, topics, and opinions to construct an organic object data model; and storing organic object data associated with the constructed organic object data model in an organic object database. | 05-12-2011 |
Chun-Wei Lin, New Taipei City TW
Patent application number | Description | Published |
---|---|---|
20150018755 | SUBSTANCE DELIVERY DEVICE AND SUBSTANCE DELIVERY METHOD USING THE SAME - A substance delivery device comprises a substrate, a plurality of dissolvable supporting structures and a plurality of carriers. The substrate attaches to a tissue. The dissolvable supporting structures are disposed on the substrate. The carriers are disposed on the dissolvable supporting structures and encapsulating substances. The present invention further provides a substance delivery method. The substance delivery device and the substance delivery method of present invention is advantageous for providing sustained release effect and rising the applicability of transdermal or transmucosal delivery techniques. | 01-15-2015 |
Chun-Wei Lin, Tainan City TW
Patent application number | Description | Published |
---|---|---|
20150104751 | GAS STOVE WITH FLAME DETECTION - A gas stove with flame detection comprises a switch module, a flame detection module and a processing module. The switch module generates an ignition signal when a gas stove flame is lit. The flame detection module generates a first light wave signal when the flame detection module detects light wave having wavelengths of about 400 nm to 500 nm, and the flame detection module generates an second light wave signal when the flame detection module detects light wave having wavelengths of about 600 nm to 780 nm. The processing module turns on an air drafting device and an alarm device when the processing module receives the first light wave signal and the second light wave signal at the same time or only receives the second light wave signal. | 04-16-2015 |
Chun-Wei Lin, Hsinchu TW
Patent application number | Description | Published |
---|---|---|
20150252954 | LIGHTING APPARATUS - A lighting apparatus comprises: a board, a plurality of light-emitting units disposed on the board, and a package structure enclosing all of the light-emitting units and having a volume less than 5000 mm | 09-10-2015 |
Chun-Wei Liu, Miao-Li County TW
Patent application number | Description | Published |
---|---|---|
20150070934 | BACKLIGHT MODULE AND DISPLAY DEVICE USING THE SAME - The invention provides a backlight module including: a planar illuminant portion having a first surface and emitting light from the first surface; an optical film assembly adhered to the first surface of the planar illuminant portion and having a bottom optical film and at least an upper optical film layered above the bottom optical film; and a ring-shaped frame surrounding the planar illuminant portion and having a first extension portion extending along a direction parallel to the first surface, wherein the bottom optical film extends toward the ring-shaped frame more than the upper optical film such that the first extension portion covers at least an edge of the bottom optical film. | 03-12-2015 |
Chun-Wei Peng, Taoyuan Hsien TW
Patent application number | Description | Published |
---|---|---|
20090297919 | GAS DIFFUSION LAYER OF PROTON EXCHANGE MEMBRANE FUEL CELL SYSTEM - A fuel cell unit of a proton exchange membrane fuel cell system includes a pair of flow field plates and a membrane electrode assembly. The membrane electrode assembly is interposed between the pair of flow field plates to define respective reactant flow channels with the pair of flow field plates. The membrane electrode assembly includes an anode catalyst layer, a cathode catalyst layer, a proton exchange membrane and a pair of gas diffusion layers. The gas diffusion layers are respectively disposed adjacent to the anode catalyst layer and the cathode catalyst layer and face to the flow field plates. At least one of the gas diffusion layers has a fluid permeability distribution profile increasing first and then decreasing from an inlet to an outlet of the reactant flow channel. The gas diffusion layer has the maximum fluid permeability at the site with the highest rate of reaction. | 12-03-2009 |
20130264524 | ELECTRODE AND FABRICATION METHOD THEREOF - The present disclosure provides a method for fabricating an electrode, including the steps of: providing a plurality of carbon nanotubes; shaping the carbon nanotubes to form a plurality of carbon nanotube granules; and mixing the carbon nanotube granules with one or more polymers to form the electrode. The present disclosure also provides an electrode. | 10-10-2013 |
Chun-Wei Su, Yonghe City TW
Patent application number | Description | Published |
---|---|---|
20100143708 | RELEASE LAYER MATERIALS, SUBSTRATE STRUCTURES COMPRISING THE SAME AND FABRICATION METHOD THEREOF - A release layer material of cyclic olefin copolymers (COC) applied in flexible electrical devices represented by Formula (I) or (II) is provided. The invention also provides a substrate structure including the release layer. The substrate structure includes a carrier, a release layer overlying the carrier with one or more blocks with a first area, wherein the release layer includes cyclic olefin copolymers (COC) represented by the disclosed Formula (I) or (II), and a flexible substrate overlying the release layer and the carrier with a second area, wherein the second area is larger than the first area and the flexible substrate has a greater adhesion force than that of the release layer to the carrier. The invention further provides a method for fabricating the substrate structure. | 06-10-2010 |
20120201961 | SUBSTRATE STRUCTURES APPLIED IN FLEXIBLE ELECTRICAL DEVICES AND FABRICATION METHOD THEREOF - A substrate structure applied in flexible electrical devices is provided. The substrate structure includes a carrier, a release layer overlying the carrier with a first area and a flexible substrate overlying the release layer and the carrier with a second area, wherein the second area is larger than the first area and the flexible substrate has a greater adhesion force than that of the release layer to the carrier. The disclosure also provides a method for fabricating the substrate structure. | 08-09-2012 |
Chun-Wei Su, New Taipei City TW
Patent application number | Description | Published |
---|---|---|
20120164050 | ORGANIC DISPERSION OF INORGANIC NANO-PLATELETS AND METHOD FOR FORMING THE SAME - The present invention provides an organic dispersion of inorganic platelets, which includes an organic solvent and H-form inorganic platelets dispersed therein. The H-form inorganic platelets have a particle size of between about 20 and 80 mm and the organic dispersion has a sold content of between about 1 and 20 wt %. A method for forming the organic dispersion is also provided. | 06-28-2012 |
20120164423 | ORGANIC/INORGANIC COMPOSITE FILM AND METHOD FOR FORMING THE SAME - The present invention provides an organic/inorganic composite film, which includes a poly(vinylidene fluoride) (PVDF) and inorganic nano-platelets dispersed therein. A weight ratio of the PVDF and the inorganic nano-platelets is between about 97:3 and 20:80. The inorganic nano-platelets have a particle size of about 20-80 nm, wherein the organic/inorganic composite film has a transparency of greater than about 85% at a wavelength between 380 and 780 nm. In addition, a method for forming the organic/inorganic composite film is also provided. | 06-28-2012 |
20120182517 | METHOD FOR MANUFACTURING MICRO RETARDER WITHOUT ALIGNMENT LAYER - A method for manufacturing a micro retarder without alignment layer includes providing a substrate, forming a liquid crystal (LC) layer having a plurality of LC molecules, a plurality of photosensitive monomers and a plurality of thermal reactive monomers, performing a first exposure treatment to form at least a first patterned retarder in the LC layer, performing a second exposure treatment to form at least a second patterned retarder in the LC layer, and performing a baking treatment to form the micro retarder without alignment layer. | 07-19-2012 |
20120313039 | PHOTOPOLYMERIZABLE LIQUID CRYSTAL MIXTURE AND MANUFACTURING METHOD OF PHOTOPOLYMERIZABLE LIQUID CRYSTAL - A photopolymerizable liquid crystal mixture includes a first photopolymerizable monomer, a second photopolymerizable monomer, a first photoinitiator, a second photoinitiator, and a liquid crystal material. A manufacturing method of photopolymerizable liquid crystal includes the following steps. A first light source is provided to irradiate the photopolymerizable liquid crystal mixture without providing a driving voltage, for inducing photopolymerization of the first photoinitiator and the first photopolymerizable monomer. A second light source is provided to irradiate the photopolymerizable liquid crystal mixture without providing a driving voltage, for inducing photopolymerization of the second photoinitiator and the second photopolymerizable monomer and aligning the liquid crystal material along a direction. | 12-13-2012 |
20130087815 | HYBRID DISPLAY DEVICE - The disclosure provides a hybrid display device, comprising: a substrate, wherein the substrate comprises a first surface and a second surface; a TFT array layer formed on the first surface of the substrate; a first display device formed on the TFT array layer; and a second display device formed on the second surface of the substrate, wherein there exists a corresponding relationship between a dielectric constant (k) of the substrate and a thickness (t) of the substrate to drive at least one of the first display device and the second display device, or to drive both of the first display device and the second display device by the TFT array layer, especially the TFT array layer actively drive the first display device, the second display device or combinations thereof. The dielectric constant of the substrate is about 1-100 and the thickness of the substrate is about 0.1-60 μm. | 04-11-2013 |
20130157126 | ELECTRODE ASSEMBLY OF LITHIUM SECONDARY BATTERY - Disclosed is an electrode assembly of a lithium secondary battery, including an anode plate, a cathode plate, a separator for separating the anode plate and the cathode plate and conducting lithium ions of an electrolyte, and a composite film disposed between the anode plate and the separator and/or between the cathode plate and the separator. The composite film includes 5 to 95 parts by weight of an inorganic clay and 95 to 5 parts by weight of an organic polymer binder. | 06-20-2013 |
20130169895 | Three-Dimensional Imaging Device - A three-dimensional imaging device is provided which includes a display device and a viewing device. The display device includes a first substrate, a second substrate, a black absorbing layer and a cholesteric liquid crystal layer including a first levo-cholesteric liquid crystal layer and a first dextro-cholesteric liquid crystal layer. The viewing device includes a second levo-cholesteric liquid crystal layer and a second dextro-cholesteric liquid crystal layer. The first levo-cholesteric liquid crystal layer is made of a same material as the second levo-cholesteric liquid crystal layer, and the first dextro-cholesteric liquid crystal layer is made of a same material as the second dextro-cholesteric liquid crystal layer. | 07-04-2013 |
20130207908 | CHOLESTERIC LIQUID CRYSTAL TOUCH DISPLAY PANEL AND TOUCH POSITIONING METHOD THEREOF - A cholesteric liquid crystal touch display panel includes an upper substrate, a lower substrate, a cholesteric liquid crystal display layer, and a color sensor array. The cholesteric liquid crystal display layer is disposed between the upper substrate and the lower substrate. The cholesteric liquid crystal display layer includes a plurality of liquid crystal display units, which are used to reflect light within a wavelength range and allow light beyond the wavelength range to pass through. The color sensor array is disposed between the cholesteric liquid crystal display layer and the lower substrate. The color sensor array includes a plurality of color sensors. Each of the color sensors is disposed correspondingly to at least one liquid crystal display unit. Each of the color sensors is used to sense variations of light from the corresponding liquid crystal display unit. | 08-15-2013 |
20130215340 | LIQUID CRYSTAL LENS FOR 3D DISPLAY AND MANUFACTURING METHOD THEREOF - The present invention provides a liquid crystal lens for a 3D display, which includes a first substrate, a second substrate, a liquid crystal layer, a first electrode layer, and a first alignment layer. The second substrate is disposed corresponding to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate. The first electrode layer is disposed on a side of the first substrate facing the second substrate. The first alignment layer is disposed on the first electrode layer. The first alignment layer has a plurality of first regions, and alignment directions of the first regions gradually change from one end to an opposite end and are symmetrical. A manufacturing method thereof is also disclosed. | 08-22-2013 |
20130227830 | MANUFACTURING METHOD OF OPTICAL FILM AND MANUFACTURING METHOD OF STEREOSCOPIC DISPLAY - A manufacturing method of an optical film includes following steps. An alignment solution is coated onto a first substrate having a first area and a second area. The alignment solution on the first substrate is exposed to a polarized light to form an optical alignment film having a first alignment direction and a second alignment direction on the two areas, respectively. A composite liquid crystal (LC) material containing a reactive LC material and a monomer material is coated onto the optical alignment film. The optical alignment film is sequentially exposed to a first non-polarized light having a monomer material absorption wavelength and a second non-polarized light having a reactive LC material absorption wavelength, thus the monomer material reacts with the reactive LC material, and the reactive LC material is solidified along the first and second alignment directions in sequence. A manufacturing method of a stereoscopic display is also provided. | 09-05-2013 |
20130258252 | TRANSPARENT LIQUID CRYSTAL DISPLAY DEVICE AND MANUFACTURING METHOD FOR THE SAME - The present invention discloses a transparent liquid crystal display device and manufacturing method thereof. By adding dichroic dyes and the dichroic dyes having characteristic of rotating with liquid crystal materials, light absorption ability of polymer network liquid crystals is increased. The present invention is capable of solving a problem which a dark state is not sufficiently dark, thus enhances contrast performance of the transparent liquid crystal display device. | 10-03-2013 |
20130260030 | METHOD FOR MANUFACTURING FLEXIBLE DISPLAY PANEL - Disclosed is a method for manufacturing a flexible display panel. The method includes the following steps: forming a patterned thermal adhesive layer including at least one hollow area on a substrate; coating a polyimide solution; baking the patterned thermal adhesive layer and the polyimide solution, so that an adhesion force between the patterned thermal adhesive layer and the substrate is enhanced and the polyimide solution is formed into a polyimide layer; manufacturing a plurality of display elements on the polyimide layer in the hollow area for forming the flexible display panel; and cutting the flexible display panel. The present invention is capable of achieving an objective of easily separating the flexible display panel and the substrate from each other. | 10-03-2013 |
20140016078 | LIQUID CRYSTAL COMPOSITION, LIQUID CRYSTAL DISPLAY PANEL AND FABRICATING METHOD THEREOF - A liquid crystal display panel including a first substrate, a second substrate, a liquid crystal molecule layer, a first liquid crystal cell layer and a second liquid crystal cell layer is provided. The second substrate is disposed opposite to the first substrate. The liquid crystal molecule layer has a plurality of liquid crystal molecules and disposed between the first substrate and the second substrate. The first liquid crystal cell layer has a plurality of first liquid crystal cells and disposed between the first substrate and the liquid crystal molecule layer. The second liquid crystal cell layer has a plurality of second liquid crystal cells and disposed between the second substrate and the liquid crystal molecule layer. Moreover, a liquid crystal composition used to make the liquid crystal display panel and a fabricating method of liquid crystal panel are also provided. | 01-16-2014 |
20140049707 | LIQUID CRYSTAL COMPOSITION FOR LC LENS AND 3D DISPLAY CONTAINING THE SAME - A liquid crystal composition for liquid crystal lens and a stereoscopic (3D) display containing the same are provided. The liquid crystal composition includes a main liquid crystal (chemical formula I), a first optical modifier (R811 or S811), a second optical modifier (CB15), and a dielectric constant modifier (chemical formula IV). The 3D display utilizes a horizontal electric field to make the above liquid crystal composition form crystal lens. | 02-20-2014 |
20140120019 | ORGANIC DISPERSION OF INORGANIC NANO-PLATELETS AND METHOD FOR FORMING THE SAME - Disclosed is an organic dispersion of inorganic platelets, which includes an organic solvent and H-form inorganic platelets dispersed therein. The H-form inorganic platelets have a particle size of between about 20 and 80 nm and the organic dispersion has a sold content of between about 1 and 20 wt %. A method for forming the organic dispersion is also provided. | 05-01-2014 |
20140264982 | FABRICATING METHOD OF TRANSPARENT LIQUID CRYSTAL DISPLAY - A fabricating method of a transparent liquid crystal display includes the following steps. First, a first substrate and a second substrate are assembled. Then, a liquid crystal composition is injected between the first substrate and the second substrate. The liquid crystal composition includes a plurality of liquid crystal molecules and a polymerizable material, wherein the polymerizable material includes a polyether polyol acrylate monomer and a liquid crystal polymerization initiator. Afterward, an irradiation procedure and a thermal procedure are executed. | 09-18-2014 |
20150060734 | LIQUID CRYSTAL COMPOSITION - A liquid crystal composition including a first liquid crystal monomer, and a second liquid crystal monomer, wherein the ratio of the first liquid crystal monomer is 5 wt % to 10 wt % and the ratio of the second liquid crystal monomer is 90 wt % to 95 wt %, based on the total weight of the first liquid crystal monomer and the second liquid crystal monomer. The first liquid crystal monomer is selected from the group consisting of tetra-cyclic compounds represented by formula 1 to formula 6: | 03-05-2015 |
20150109542 | TOUCH PANEL - A touch panel is provided, which includes a poly(vinylidene fluoride) (PVDF) substrate and a touch electrode structure. The PVDF substrate has two opposite surfaces. The touch electrode structure is at least disposed on one of the surfaces. | 04-23-2015 |
20150116636 | TRANSPARENT DISPLAY DEVICE - A transparent display device includes a color filter substrate, a driving substrate and a polymer-dispersed liquid crystal (PDLC) layer. The color filter substrate includes a substrate, a light shielding structure and a plurality of color filter patterns. The light shielding structure is disposed on the substrate to define a plurality of sub-pixel regions and a blank sub-pixel region of the substrate. The color filter patterns respectively cover the sub-pixel regions of the substrate, but the blank sub-pixel region is not covered by the color filter patterns. The driving substrate corresponds to the color filter substrate. The PDLC layer is interposed between the color filter substrate and the driving substrate. | 04-30-2015 |
20150123031 | METHOD OF MANUFACTURING POLYMER DISPERSED LIQUID CRYSTAL - A method of manufacturing polymer dispersed liquid crystal includes: mixing liquid crystal, a first photopolymerizable material, a first photoinitiator, a second photopolymerizable material and a second photoinitiator to form a mixture, in which the first photoinitiator is capable to initiate polymerization of the first photopolymerizable material by irradiating a first ultraviolet light, and the second photoinitiator is capable to initiate polymerization of the second photopolymerizable material by irradiating a second ultraviolet light, and the first ultraviolet light has a wavelength different from that of the second ultraviolet light. The first photopolymerizable material is polymerized by irradiating the first ultraviolet light to form a plurality of first liquid crystal droplets. The second photopolymerizable material is polymerized by irradiating the second ultraviolet light to form a plurality of second liquid crystal droplets dispersed between the first liquid crystal droplets. | 05-07-2015 |
20150124199 | TRANSPARENT DISPLAY DEVICE - A transparent display device includes a display panel and an active transparent OLED backlight device. The display panel includes a first driving substrate, a color filter substrate and a polymer dispersed liquid crystal layer interposed therebetween. The first driving substrate has a first driving region and sub-pixel regions. The active transparent OLED backlight device includes a second driving substrate, an opposite substrate and OLEDs interposed therebetween. The second driving substrate has a second driving region and sub-pixel regions. The second driving region is aligned with the first driving region, and each of the sub-pixel regions of the second driving substrate is aligned with one of the sub-pixel regions of the first driving substrate. Each of the sub-pixel regions of the second driving substrate has a light-transmitting region and a light-emitting region. The OLEDs are respectively disposed on the light-emitting regions of the second driving substrate. | 05-07-2015 |
20150162585 | ORGANIC-INORGANIC COMPOSITE LAYER FOR LITHIUM BATTERY AND ELECTRODE MODULE - An organic-inorganic composite layer for a lithium battery includes an organic polymer and a plurality of composite inorganic particles. The weight ratio of the organic polymer to the composite inorganic particles is 10:90 to 95:5, wherein the composite inorganic particles have at least two structural configurations stacked in staggered configuration. | 06-11-2015 |
20150226988 | TRANSPARENT DISPLAY APPARATUS - A transparent display apparatus including a backlight module, a display panel, and a switching panel is provided. The backlight module includes a light source and a light guide plate (LGP). The display panel is located on a light emitting surface of the LGP. The switching panel and the backlight module are located at the same side of the display panel. The switching panel includes a first substrate, a second substrate opposite to the first substrate, a polymer-dispersed liquid crystal layer located between the first substrate and the second substrate, a first electrode layer located between the first substrate and the polymer-dispersed liquid crystal layer, and a second electrode layer located between the polymer-dispersed liquid crystal layer and the second substrate. The first electrode layer is divided into first electrode patterns that are separated from and electrically independent from one another. Another transparent display apparatus is also provided. | 08-13-2015 |
20150245470 | FLEXIBLE SUBSTRATE EMBEDDED WITH WIRES AND METHOD FOR FABRICATING THE SAME - A flexible substrate embedded with wires is provided. The flexible substrate embedded with wires includes a flexible substrate constituted by a polymer material, and a continuous wire pattern containing a plurality of pores embedded in the flexible substrate, wherein the polymer material fills the pores. A method for fabricating a flexible substrate embedded with wires is also provided. | 08-27-2015 |
20150355514 | TRANSPARENT DISPLAY DEVICE AND DISPLAYING METHOD THEREOF - A transparent display device includes a first active LCD panel, a second active LCD panel and a backlight module sandwiched between the first active LCD panel and the second active LCD panel. Both of the first active LCD panel and the second active LCD panel can provide various images and show different displaying states. Therefore, the transparent display device can utilize the images or the displaying states shown by the second active LCD panel to facilitate the image displaying function of the first active LCD panel to achieve the purpose of improving the image contrast and the variety effect. | 12-10-2015 |
Chun-Wei Tsai, Hualien County TW
Patent application number | Description | Published |
---|---|---|
20080213937 | METHOD OF FABRICATING OPTICAL DEVICE CAPS - A wafer having a plurality of through holes is provided, and a glass wafer is disposed on the wafer. A plate having a plurality of concave cavities is disposed on the glass wafer, wherein the concave cavities corresponding to the through holes of the wafer so that a part of the plate corresponding to the through holes is not in contact with the glass wafer. A voltage source is provided, and two electrodes thereof respectively have electrical connections to the wafer and the plate. The wafer and the glass wafer are bonded to each other by the anodic bonding method so that a plurality of optical device caps are formed. | 09-04-2008 |
20090061598 | WAFER-LEVEL PACKAGING CUTTING METHOD CAPABLE OF PROTECTING CONTACT PADS - A cutting method for wafer-level packaging capable of protecting the contact pad, in which several cavities and precutting lines are formed at the front surface of a cap wafer, and the depth of each precutting line is lesser than the thickness of the cap wafer, followed by the bonding of the cap wafer to the device wafer, which has several devices and several bonding pads disposed on the surface of the device wafer, followed by performing a wafer dicing process, along the precutting lines cutting through the cap wafer, and after removing a portion of the cap wafer that is not bonded to the device wafer, for exposing the bonding pads at the surface of the device wafer, and finally performing a dicing process for forming many packaged dies. | 03-05-2009 |
Chun-Wei Tseng, Kaohsiung TW
Patent application number | Description | Published |
---|---|---|
20140074309 | POWER USAGE CONTROL SYSTEM - A power usage control system includes a transmission medium for transmitting power. A management module is coupled to the transmission medium. A control module is coupled to the transmission medium and at least one controlled apparatus. The management module and the control module communicate with each other through the transmission medium. The management module monitors an operation status of the at least one controlled apparatus through the control module. The management module controls the at least one controlled apparatus through the control module. | 03-13-2014 |
Chun-Wei Tseng, Kaoshiung TW
Patent application number | Description | Published |
---|---|---|
20120246707 | METHOD FOR INDICATING ABNORMAL DATA-INPUTTING BEHAVIOR - A method for indicating abnormal data-inputting behavior includes inducting and connecting an identification end with a control system. The control system receives a procedure selecting command to allow input of registration data or a log-in data. The control system generates identification information based on the registration data when the procedure selecting command is the input of registration data. The identification information is stored in the identification end and includes the registration data, a template of keystroke, and an identification code. The control system generates a keystroke dynamic based on the long-in data when the procedure selecting command is the input of log-in data. The control system compares the keystroke dynamic of the log-in data with the template of keystroke of the identification information. The control system sends out a warning message when the keystroke dynamic of the log-in data does not match the template of keystroke of the identification information. | 09-27-2012 |
Chun-Wei Wang, Yongkang City TW
Patent application number | Description | Published |
---|---|---|
20090310852 | Method for Constructing Three-Dimensional Model and Apparatus Thereof - Disclosed are a method and an apparatus for constructing an accurate three-dimensional model. The apparatus includes a plurality of light sources, an image-capturing element and an image-processing unit. The present invention is used to integrate the two-dimensional images from different views of an object into a high accurate three-dimensional model. Compared with conventional apparatuses, the apparatus of the present invention is useful without safety problems, relatively easily manipulated, and capable of quick image reconstruction. | 12-17-2009 |
Chun-Wei Wang, Hsinchu TW
Patent application number | Description | Published |
---|---|---|
20090267090 | COLOR MIXING LIGHT EMITTING DIODE DEVICE - An exemplary color mixing light emitting diode (LED) device includes a substrate, LED dies, an encapsulating body, and a light mixing structure. The substrate has a main surface. The LED dies are arranged adjacent the main surface of the substrate. The light mixing structure is arranged adjacent an outer portion of the main surface of the substrate, around the LED dies. The encapsulating body encapsulates the LED dies and the light mixing structure. The light mixing structure is made of light transmissive material, and the light mixing structure has light scattering particles doped therein. | 10-29-2009 |
Chun-Wei Wang, Hukou TW
Patent application number | Description | Published |
---|---|---|
20090250709 | LED PACKAGE AND LIGHT SOURCE DEVICE USING SAME - An exemplary LED package includes a dielectric plate, a heat conductor, a first planar electrode and a second planar electrode, a LED chip, and metal wires. The dielectric plate comprises a receiving groove defined therein. The heat conductor is positioned in the dielectric plate opposite to the receiving groove, and the heat conductor comprises a holding portion exposed on bottom of the receiving groove. The first and second planar electrodes are respectively received in the dielectric plate extending to the receiving groove and are spaced from the heat conductor. The first and second electrodes are respectively electrically connected to the LED chip by the metal wires. The LED chip is mounted on the holding portion of the heat conductor. | 10-08-2009 |
20100001299 | LIGHT EMITTING DIODE ILLUMINATING APPARATUS WITH SAME-TYPE LIGHT EMITTING DIODES - A light emitting diode illuminating apparatus for emitting colorful light includes a substrate, a first lighting element, a second lighting element, a third lighting element. The first, second and third lighting elements are juxtaposed at the substrate. The first lighting element includes a first LED chip, and a first filling layer encapsulating it. The first filling layer includes red phosphor generally evenly doped therein. The second lighting element includes a second LED chip and a second filling layer encapsulating it. The third lighting element includes a third LED chip and a third filling layer encapsulating it. All of the first, the second and the third LED chips are the same kind of LED chip selected from the group consisting of GaN LED chips, AlGaN LED chips and InGaN LED chips. Light emitting from the filling layers are capable of mixing to produce light of a uniform color. | 01-07-2010 |
20110193110 | LIGHT EMITTING DIODE ILLUMINATING APPARATUS WITH SAME-TYPE LIGHT EMITTING DIODES - A light emitting diode illuminating apparatus includes a substrate, a first lighting element and a second lighting element. The first and second lighting elements are juxtaposed at the substrate. The first lighting element includes a first LED chip, and a first filling layer encapsulating the first LED chip. The first filling layer includes red phosphor generally evenly doped therein. The second lighting element includes a second LED chip and a second filling layer encapsulating it. The second filling layer includes two different phosphor materials respectively doped therein. The first LED chip and the second LED chip are the same kind of LED chip selected from the group consisting of GaN LED chips, AlGaN LED chips and InGaN LED chips. Light emitted from the first filling layer and the second filling layer is capable of mixing to produce light of a uniform color. | 08-11-2011 |
Chun-Wei Wang, Sanxia Town TW
Patent application number | Description | Published |
---|---|---|
20100315716 | Microstructure diffuser - A microstructure diffuser includes a light-entering surface, a light-emitting surface, and a plurality of microstructure portions having a first microstructure unit and a second microstructure unit. The first microstructure unit includes a first side surface, a second side surface, a top surface, a first pitch (P | 12-16-2010 |
Chun-Wei Wu, Tu-Cheng TW
Patent application number | Description | Published |
---|---|---|
20120235957 | STYLUS AND PORTABLE ELECTRONIC DEVICE USING SAME - A portable electronic device, including a housing defining an earphone connector, a touch screen, and a stylus having a stylus body, a tip and a pin connecting the stylus body with tip, and the pin and the tip are detachably secured in the earphone connector. | 09-20-2012 |
Chun-Wei Wu, Shindian TW
Patent application number | Description | Published |
---|---|---|
20130107475 | FLEXIBLE CIRCUIT BOARD STACK ASSEMBLY | 05-02-2013 |
Chun-Wei Yang, Kaohsiung City TW
Patent application number | Description | Published |
---|---|---|
20150054763 | DRIVING CIRCUIT HAVING NOISE IMMUNITY - A driving circuit including a display module, a retrieving module, a touch module, and an adjusting module is provided. The display module outputs a plurality of image control signals. The retrieving module is coupled with the display module, wherein the retrieving module retrieves the image control signals and sets a preset offset value according to a coupling level of the image control signals. The touch module outputs a plurality of driving signals. The adjusting module is coupled between the retrieving module and the touch module, wherein the adjusting module adjusts the driving signals according to the preset offset value. | 02-26-2015 |
Chun-Wei Yang, Hsien-Shi Township TW
Patent application number | Description | Published |
---|---|---|
20090191770 | CONDUCTING TERMINAL CONNECTOR AND MANUFACTURING METHOD THEREOF - There is disclosed a conducting terminal connector which comprises an insulating tube, a conducting terminal and a soldering sleeve. The conducting terminal has a first end received in the insulating tube and a second end opposite to said first end, and the second end is exposed outwardly for connecting an external conducting contact point so that the first end is bent to form a longitudinal elongation with an opening facing upward. The soldering sleeve is formed by a casting method so as to form a corrugated surface on the outer periphery thereof, and has a melting point in which a heat source is applied to an outer part of the insulating tube so that an inner part of the insulating tube is shrunken to lodge in the outer corrugated surface of the soldering sleeve thereby forming the conducting terminal connect. | 07-30-2009 |
Chun-Wei Yang, Taoyuan County TW
Patent application number | Description | Published |
---|---|---|
20140070533 | POWER GENERATION USING A HEAT TRANSFER DEVICE AND CLOSED LOOP WORKING FLUID - A fast heat transfer device is provided. The device dissipates heat and generates power at the same time. A liquid flow is used to absorb heat for forming a vapor gas flow; then, the gas flow drives a blade turbine and a power generator; and, finally, the gas flow is cooled down to become the original liquid flow for recycling. Thus, the present invention dissipates heat and generates power simultaneously with a minimized size and a reduced cost together with energy conservation. | 03-13-2014 |
Chun-Wei Yang, Chia-Yi City TW
Patent application number | Description | Published |
---|---|---|
20090286577 | Communication System Capable of Adjusting Power Consumed Thereby - A communication system capable of adjusting power consumed thereby is adapted for receiving connection information. The communication system includes first and second transceiving devices. The first transceiving device includes a transmitting end and a service end for receiving the connection information. The second transceiving device includes a receiving end capable of forming a communications link with the transmitting end. A power state of each of the first and second transceiving devices is switchable between a power-supplied mode and a power-saving mode. The power state alters status of the communications link. | 11-19-2009 |
Chun-Wei Yang, Hsinchu City TW
Patent application number | Description | Published |
---|---|---|
20140154997 | RF TESTING SYSTEM - An integrated circuit (IC) is provided. The IC includes an RF transmitter configured to generate an RF signal in response to a command signal from test equipment; an RF receiver configured to generate an evaluation signal according to the RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result, wherein the test equipment is external to the IC. | 06-05-2014 |
20150229415 | RF TESTING SYSTEM - An integrated circuit (IC) is provided. The IC includes an RF transmitter configured to generate an RF signal in response to a command signal from test equipment; an RF receiver configured to generate an evaluation signal according to the RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result, wherein the test equipment is external to the IC. | 08-13-2015 |
Chun-Wei Yang, Hang Zhou CN
Patent application number | Description | Published |
---|---|---|
20120240735 | TORQUE WRENCH - A torque wrench includes a driving head, a hollow handle, compression unit, an adjustment unit, an index unit and a display unit. The driving head and the handle are pivotably connected to each other. The compression unit has a resilient member and an end piece which contacts the driving head. The adjustment unit adjusts the length of the resilient member to set the torque of the wrench. The index unit has a first index and a second index, both of which are moved with the movement of the adjustment unit. The movement of the first index is detected by the display unit and transferred into digits to display the value of the torque. The second index is cooperated with the marks of the scale member to display the value of the torque. | 09-27-2012 |
20130239758 | OPEN WRENCH - An open wrench includes an elongate body with a head located on an end of the body. The head includes two jaws and a mounting hole is defined between the two jaws. One of the jaws has a curved recess, a curved guide slot and a notch defined in the inside thereof. The other jaw has a curved convex contact face protruding from the inside thereof. An engaging member is movably located in the curved guide slot and a resilient member biases the engaging member which performs as a ratchet wrench. Two covers are respectively connected to the top and the bottom of the head to cover up the engaging member and the resilient member. | 09-19-2013 |
Chun-Wei Yeh, Taichung Hsien TW
Patent application number | Description | Published |
---|---|---|
20140327131 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer formed on the body and having a plurality of openings for exposing the conductive pads; a plurality of conductive vias formed in the openings of the surface passivation layer and electrically connected to the conductive pads; a plurality of circuits formed on the surface passivation layer and electrically connected to the conductive vias, wherein the circuits have a plurality of electrical contacts; at least a pattern portion formed on the surface passivation layer and intersecting with the circuits; and a second passivation layer formed on the surface passivation layer, the circuits and the pattern portion and having a plurality of openings for exposing portions of the electrical contacts of the circuits, thereby strengthening the bonding between the circuits and the passivation layers. | 11-06-2014 |