Bhagavat
Milind Bhagavat, Medford, MA US
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20090294879 | Method for Capping a MEMS Wafer - A method for capping a MEMS wafer to form a hermetically sealed device. The method includes applying a glass bonding agent to the cap wafer and burning off organic material in the glass bonding agent. The cap wafer/glass bonding agent combination is then cleaned to reduce lead in the combination. The cleaning is preferably accomplished using an oxygen plasma. The MEMS device is coated with a WASA agent. The cap wafer is then bonded to the MEMS wafer by heating this combination in a capping gas atmosphere of hydrogen molecules in a gas such as nitrogen, argon or neon. This method of capping the MEMS wafer can reduce stiction in the MEMS device. | 12-03-2009 |
20100117221 | Capped Wafer Method and Apparatus - A capped wafer includes a device wafer and an opposing cap wafer with an annular glass frit disposed between the device wafer and the cap wafer. The glass frit and the opposing wafers define a sealed volume that encloses the capped devices, and the glass frit may support the wafer cap during removal of excess wafer cap material from the capped wafer. A method of fabricating a capped wafer includes fabricating an annular intermediate layer between a device wafer and a cap wafer. In an alternate embodiment, a plurality of unsingulated dice each contains bond pads along a single edge and are arranged on a device wafer in an alternating order so that the bond pads of a first die are adjacent to the bond pads of a second die. Removing excess cap wafer material involves making a first cut in the cap wafer near a first row of bond pads and a second cut near the adjacent row of bond pads, such that a strip of wafer cap material is suspended from portions of an underlying supporting member near the edge of the capped wafer, and then removing the wafer cap material suspended from the portions of the supporting glass frit using an adhesive tape. | 05-13-2010 |
20120112765 | MEMS In-Plane Resonators - MEMS in-plane resonators include a substrate wafer, at least one resonant mass supported by the substrate wafer and configured to resonate substantially in-plane, and at least one transducer coupled to the at least one resonant mass for at least one of driving and sensing in-plane movement of the at least one resonant mass, wherein at least part of one surface of the resonant mass is configured for exposure to an external environment and wherein the at least one transducer is isolated from the external environment. Such MEMS in-plane resonators may be fabricated using conventional surface micromachining techniques and high-volume wafer fabrication processes and may be configured for liquid applications (e.g., viscometry, densitometry, chemical/biological sensing), gas sensing (e.g., where a polymer film is added to the sensor surface, further degrading the damping performance), or other applications. | 05-10-2012 |
Milind Bhagavat, Fremont, CA US
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20120299868 | High Noise Immunity and High Spatial Resolution Mutual Capacitive Touch Panel - A mutual capacitive touch panel providing improved noise immunity and improved spatial resolution is described. The touch panel includes a drive line having a plurality of drive electrodes. The touch panel further includes a sense line arranged at an angle with respect to the drive line and the sense line having a plurality of sense electrodes, such that each of the plurality of sense electrodes overlies one of the plurality of drive electrodes. The touch panel is further configured such that a perimeter of each of the plurality of drive electrodes encompasses a perimeter of at least one of the plurality of sense electrodes. | 11-29-2012 |
Milind S. Bhagavat, Fremont, CA US
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20110101504 | Methods of Grinding Semiconductor Wafers Having Improved Nanotopology - Methods for holding a workpiece with a hydrostatic pad are disclosed herein. The pad includes hydrostatic pockets formed in a face of the body directly opposed to the wafer. The pockets are adapted for receiving fluid through the body and into the pockets to provide a barrier between the body face and the workpiece while still applying pressure to hold the workpiece during grinding. The hydrostatic pads allow the wafer to rotate relative to the pads about their common axis. The pockets are oriented to reduce hydrostatic bending moments that are produced in the wafer when the grinding wheels shift or tilt relative to the hydrostatic pads, helping prevent nanotopology degradation of surfaces of the wafer commonly caused by shift and tilt of the grinding wheels. | 05-05-2011 |
20120314367 | Methods and Systems for On-Chip Osmotic Airflow Cooling - An apparatus for cooling a semiconductor element is provided. The apparatus can include an electron emitter configured to emit electrons such that at least some of the emitted electrons become attached to air particulates and an air accelerator configured to generate an electric field that accelerates the air particulates toward the air accelerator to create an air flow over at least a portion of the semiconductor element. The air flow carries heat away from the at least a portion of the semiconductor element. | 12-13-2012 |
20140124940 | FLEXIBLE ROUTING FOR CHIP ON BOARD APPLICATIONS - Methods, systems, and apparatuses for semiconductor devices are provided herein. A semiconductor device includes an array of conductive pads for signals. One or more non-linear compliant springs may be present to route signals from the conductive pads to interconnect pads formed on the semiconductor device to attach bump interconnects. Each non-linear compliant spring may include one or more routing segments. The semiconductor device may be mounted to a circuit board by the bump interconnects. When the semiconductor device operates, heat may be generated by the semiconductor device, causing thermal expansion by the semiconductor device and the circuit board. The semiconductor device and circuit board may expand by different amounts due to differences in their thermal coefficients of expansion. The non-linear compliant springs provide for compliance between the conductive pads and bump interconnects to allow for the different rates of expansion. | 05-08-2014 |
20140145300 | INTEGRATION OF CHIPS AND SILICON-BASED TRENCH CAPACITORS USING LOW PARASITIC SILICON-LEVEL CONNECTIONS - Methods and apparatuses are described for integration of integrated circuit die and silicon-based trench capacitors using silicon-level connections to reduce connection lengths, parasitics and necessary capacitance magnitudes and volumes. A trench capacitor can be fabricated on silicon and mounted on or embedded in a chip or one or more sides of a through silicon interposer (TSI) for silicon-level connections to chip circuitry. Aspect ratio dependent, as opposed to trench diameter or trench depth dependent, trench capacitors formed by a dense array of high aspect ratio trenches with thin, high permittivity dielectric increase capacitance per unit area and volume, resulting in thin, high capacitance trench capacitors having thickness equal to or less than chip thickness. | 05-29-2014 |
Milind S. Bhagavat, Medford, MA US
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20100087123 | Method For Assessing Workpiece Nanotopology Using A Double Side Wafer Grinder - A method of processing a semiconductor wafer using a double side grinder of the type that holds the wafer in a plane with a pair of grinding wheels and a pair of hydrostatic pads. The method includes measuring a distance between the wafer and at least one sensor and determining wafer nanotopology using the measured distance. The determining includes using a processor to perform a finite element structural analysis of the wafer based on the measured distance. | 04-08-2010 |
Milind S. Bhagavat, Cupertino, CA US
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20140361395 | Biometric Sensor Chip Having Distributed Sensor and Control Circuitry - A sensor includes a sensor array formed on a first side of a substrate and at least one circuit operative to communicate with the sensor array formed on a second side of the substrate. At least one via extends through the substrate to electrically connect the sensor array to the at least one circuit. Placing the at least one circuit on the second side of the substrate allows the sensor array to occupy substantially all of the first side of the substrate. | 12-11-2014 |
Sitaram Bhagavat, Plaisboro, NJ US
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20100142808 | IDENTIFYING BANDING IN DIGITAL IMAGES - One or more implementations access a digital image and determine whether at least one portion of the digital image includes one or more bands having a difference in color. The determination is based on at least two candidate scales. One or more implementations access a digital image and assess at least a portion of the digital image for the existence of one or more bands having a difference in color. The assessing includes determining a fraction of pixels in the portion having a color value offset by an offset value from a color value of a particular pixel in the portion. | 06-10-2010 |
Sumeet Bhagavat, St. Charles, MO US
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20140357161 | CENTER FLEX SINGLE SIDE POLISHING HEAD - A polishing head assembly for single side polishing of silicon wafers includes a polishing head and a cap. The polishing head includes a top surface and a bottom surface and defines a longitudinal axis extending therethrough. The cap is positioned coaxially with the polishing head and includes an upper surface and a lower surface. The upper surface is spaced from the bottom surface of the polishing head to form a chamber that allows the cap to deflect toward the polishing head. | 12-04-2014 |
Sumeet S. Bhagavat, St. Peters, MO US
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20110237160 | Hydrostatic Pad Pressure Modulation in a Simultaneous Double Side Wafer Grinder - Systems and methods are disclosed for modulating the hydrostatic pressure in a double side wafer grinder having a pair of grinding wheels. The systems and methods use a processor to measure the amount of electrical current drawn by the grinding wheels. Pattern detection software is used to predict a grinding stage based on the measured electrical current. The hydrostatic pressure is changed by flow control valves at each stage to change the clamping pressure applied to the wafer and to thereby improve nanotopology in the processed wafer. | 09-29-2011 |
20130139800 | Methods For Controlling Surface Profiles Of Wafers Sliced In A Wire Saw - Methods are disclosed for controlling surface profiles of wafers cut in a wire saw machine. The systems and methods described herein are generally operable to alter the nanotopology of wafers sliced from an ingot by controlling the shape of the wafers. The shape of the wafers is altered by changing the temperature and/or flow rate of a temperature-controlling fluid circulated in fluid communication with bearings supporting wire guides of the saw. Different feedback systems can be used to determine the temperature of the fluid necessary to generate wafers having the desired shape and/or nanotopology. | 06-06-2013 |
20130139801 | Methods For Controlling Displacement Of Bearings In A Wire Saw - Methods are disclosed for controlling the displacement of bearings in a wire saw machine. The systems and methods described herein are generally operable to alter the nanotopology of wafers sliced from an ingot by controlling the shape of the wafers. The shape of the wafers is altered by controlling displacement of bearings in the wire saw by changing the temperature and/or flow rate of a temperature-controlling fluid circulated in fluid communication with bearings supporting wire guides of the saw. Different feedback systems can be used to determine the temperature of the fluid necessary to generate wafers having the desired shape and/or nanotopology. | 06-06-2013 |
20130144420 | Systems For Controlling Surface Profiles Of Wafers Sliced In A Wire Saw - Systems are disclosed for controlling the surface profiles of wafers cut in a wire saw machine. The systems and methods described herein are generally operable to alter the nanotopology of wafers sliced from an ingot by controlling the shape of the wafers. The shape of the wafers is altered by changing the temperature and/or flow rate of a temperature-controlling fluid circulated in fluid communication with bearings supporting wire guides of the saw. Different feedback systems can be used to determine the temperature of the fluid necessary to generate wafers having the desired shape and/or nanotopology. | 06-06-2013 |
20130144421 | Systems For Controlling Temperature Of Bearings In A Wire Saw - Systems and are disclosed for controlling the temperature of bearings in a wire saw machine. The systems described herein are generally operable to alter the nanotopology of wafers sliced from an ingot by controlling the shape of the wafers. The shape of the wafers is altered by controlling the temperature of bearings in the wire saw by changing the temperature and/or flow rate of a temperature-controlling fluid circulated in fluid communication with bearings supporting wire guides of the saw. Different feedback systems can be used to determine the temperature of the fluid necessary to generate wafers having the desired shape and/or nanotopology. | 06-06-2013 |
Sumeet S. Bhagavat, Creve Coeur, MO US
Patent application number | Description | Published |
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20110045740 | Methods and Systems For Adjusting Operation Of A Wafer Grinder Using Feedback from Warp Data - Processing a wafer using a double side grinder having a pair of grinding wheels. Warp data is obtained by a warp measurement device for measuring warp of a wafer as ground by the double side grinder. The warp data is received and a nanotopography of the wafer is predicted based on the received warp data. A grinding parameter is determined based on the predicted nanotopography of the wafer. Operation of the double side grinder is adjusted based on the determined grinding parameter. | 02-24-2011 |
Sumeet S. Bhagavat, St. Charles, MO US
Patent application number | Description | Published |
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20130174828 | Systems and Methods For Controlling Surface Profiles Of Wafers Sliced In A Wire Saw - Systems and methods are disclosed for controlling the surface profiles of wafers cut in a wire saw machine. The systems and methods described herein are generally operable to alter the nanotopology of wafers sliced from an ingot by controlling the shape of the wafers. The shape of the wafers is altered by changing the temperature and/or flow rate of a temperature-controlling fluid that comes in contact with the ingot. Different feedback systems can be used to determine the temperature of the fluid necessary to generate wafers having the desired shape and/or nanotopology. | 07-11-2013 |
20130174829 | Methods For Mounting An Ingot On A Wire Saw - Methods are disclosed for determining mounting locations of ingots on a wire saw machine. The methods include measuring a test surface of a test wafer previously sliced by the wire saw machine from a test ingot to calibrate the system. A magnitude and a direction of an irregularity of the measured test surface of the test wafer is then determined. The mounting location is then determined for another ingot to be mounted on the ingot holder based on at least one of the magnitude and direction of the irregularity of the measured test surface of the test wafer. | 07-11-2013 |
20140170781 | DOUBLE SIDE POLISHER WITH PLATEN PARALLELISM CONTROL - A platen for polishing a surface of a wafer has a reaction plate, a polishing plate, and a bladder. The reaction plate has a top and bottom surface, and defines a longitudinal axis. The polishing plate is positioned coaxially with the reaction plate. The polishing plate has a second top surface and a second bottom surface. The second top surface is adjacent to the bottom surface of the reaction plate. The bladder is coaxially located along a radially outer portion of either the top or bottom surface of the reaction plate. The bladder is connected with the polishing plate and able to expand to deform the polishing plate with respect to the bottom surface of the reaction plate. | 06-19-2014 |
20140273748 | SINGLE SIDE POLISHING USING SHAPE MATCHING - A method of polishing a wafer is disclosed that includes determining a removal profile. The wafer is measured to determine a starting wafer profile and then the wafer is polished. The wafer is again measured after being polished to determine a polished wafer profile. The starting wafer profile and the polished wafer profile are compared to each other to determine the removal profile by computing the amount and shape of material removed from the first wafer during polishing. | 09-18-2014 |