Patent application number | Description | Published |
20080242195 | CMP SYSTEM HAVING AN EDDY CURRENT SENSOR OF REDUCED HEIGHT - By providing an eddy current sensor element in a polishing tool at a reduced height level in combination with a corresponding optical endpoint detection system, standard polishing pads may be used, thereby enhancing the lifetime of the polishing pad and increasing tool utilization. | 10-02-2008 |
20080242196 | METHOD AND SYSTEM FOR CONTROLLING CHEMICAL MECHANICAL POLISHING BY TAKING ZONE SPECIFIC SUBSTRATE DATA INTO ACCOUNT - A system for chemical mechanical polishing (CMP) is disclosed which includes a polishing apparatus for polishing a surface of a substrate and a sensor for determining zone-specific substrate data respectively related to at least two zones of the substrate. A controller is provided for generating, in response to the zone-specific substrate data, at least one set-point value, e.g., a set-point window of values for at least one operating parameter of the polishing apparatus in a subsequent CMP process. The set-point value/set-point window of values may be displayed on a display device or automatically taken into account by the controller for controlling subsequent CMP processes. | 10-02-2008 |
20090061745 | POLISHING HEAD USING ZONE CONTROL - A polishing head for a chemical mechanical polishing apparatus is provided which includes at least two polishing head zones configured to provide different temperatures for transferring heat to at least two zones of a substrate corresponding to the at least two polishing head zones. The present disclosure addresses chemical mechanical polishing which allows a control of the polishing profile even if slurries are used, which show almost no dependency between polishing rate and down force. | 03-05-2009 |
20090170320 | CMP SYSTEM AND METHOD USING INDIVIDUALLY CONTROLLED TEMPERATURE ZONES - By creating a temperature profile across a polishing pad, a respective temperature profile may be obtained in a substrate to be polished, which may result in a respective varying removal rate across the substrate for a chemically reactive slurry material or for an electro-chemically activated polishing process. Hence, highly sensitive materials, such as material comprising low-k dielectrics, may be efficiently polished with a high degree of controllability. | 07-02-2009 |
20100112816 | METHOD OF REDUCING NON-UNIFORMITIES DURING CHEMICAL MECHANICAL POLISHING OF MICROSTRUCTURE DEVICES BY USING CMP PADS IN A GLAZED MODE - In sophisticated CMP recipes, the material removal may be accomplished on the basis of a chemically reactive slurry material and a reduced down force, wherein the surface topography of a finally obtained material layer may be enhanced by using, at least in a final phase, a glazed state of the polishing pad. | 05-06-2010 |
20110073920 | SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY CORNER ROUNDING BASED ON A SACRIFICIAL FILL MATERIAL - In a replacement gate approach, a top area of a gate opening may receive a superior cross-sectional shape on the basis of a material erosion process, wherein a sacrificial material may protect sensitive materials, such as a high-k dielectric material, in the gate opening. In one illustrative embodiment, the sacrificial material may be applied after depositing a work function adjusting species in the gate opening. | 03-31-2011 |
20110073956 | FORMING SEMICONDUCTOR RESISTORS IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES BY INCREASING ETCH RESISTIVITY OF THE RESISTORS - In a replacement gate approach, the polysilicon material may be efficiently removed during a wet chemical etch process, while the semiconductor material in the resistive structures may be substantially preserved. For this purpose, a species such as xenon may be incorporated into the semiconductor material of the resistive structure, thereby imparting a significantly increased etch resistivity to the semiconductor material. The xenon may be incorporated at any appropriate manufacturing stage. | 03-31-2011 |
20110076844 | SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY PERFORMING A POLISHING PROCESS BASED ON A SACRIFICIAL FILL MATERIAL - In a replacement gate approach, a top area of a gate opening may receive a superior cross-sectional shape after the deposition of a work function adjusting species on the basis of a polishing process, wherein a sacrificial material may protect the sensitive materials in the gate opening. | 03-31-2011 |
20110101460 | SEMICONDUCTOR FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES - In a replacement gate approach, the semiconductor material of the gate electrode structures may be efficiently removed during a wet chemical etch process, while this material may be substantially preserved in electronic fuses. Consequently, well-established semiconductor-based electronic fuses may be used instead of requiring sophisticated metal-based fuse structures. The etch selectivity of the semiconductor material may be modified on the basis of ion implantation or electron bombardment. | 05-05-2011 |
20110104880 | CORNER ROUNDING IN A REPLACEMENT GATE APPROACH BASED ON A SACRIFICIAL FILL MATERIAL APPLIED PRIOR TO WORK FUNCTION METAL DEPOSITION - In a replacement gate approach, a top area of a gate opening has a superior cross-sectional shape which is accomplished on the basis of a plasma assisted etch process or an ion sputter process. During the process, a sacrificial fill material protects sensitive materials, such as a high-k dielectric material and a corresponding cap material. Consequently, the subsequent deposition of a work function adjusting material layer may not result in a surface topography which may result in a non-reliable filling-in of the electrode metal. In some illustrative embodiments, the sacrificial fill material may also be used as a deposition mask for avoiding the deposition of the work function adjusting metal in certain gate openings in which a different type of work function adjusting species is required. | 05-05-2011 |
20110129980 | CAP REMOVAL IN A HIGH-K METAL GATE ELECTRODE STRUCTURE BY USING A SACRIFICIAL FILL MATERIAL - Dielectric cap layers of sophisticated high-k metal gate electrode structures may be efficiently removed on the basis of a sacrificial fill material, thereby reliably preserving integrity of a protective sidewall spacer structure, which in turn may result in superior uniformity of the threshold voltage of the transistors. The sacrificial fill material may be provided in the form of an organic material that may be reduced in thickness on the basis of a wet developing process, thereby enabling a high degree of process controllability. | 06-02-2011 |
20110156162 | SEMICONDUCTOR RESISTORS FORMED AT A LOWER HEIGHT LEVEL IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES - In sophisticated semiconductor devices comprising high-k metal gate electrode structures formed on the basis of a replacement gate approach, semiconductor-based resistors may be provided without contributing to undue process complexity in that the resistor region is recessed prior to depositing the semiconductor material of the gate electrode structure. Due to the difference in height level, a reliable protective dielectric material layer is preserved above the resistor structure upon exposing the semiconductor material of the gate electrode structure and removing the same on the basis of selective etch recipes. Consequently, well-established semiconductor materials, such as polysilicon, may be used for the resistive structures in complex semiconductor devices, substantially without affecting the overall process sequence for forming the sophisticated replacement gate electrode structures. | 06-30-2011 |
20110186929 | SOI SEMICONDUCTOR DEVICE COMPRISING SUBSTRATE DIODES HAVING A TOPOGRAPHY TOLERANT CONTACT STRUCTURE - In an SOI semiconductor device, substrate diodes may be formed on the basis of a superior design of the contact level and the metallization layer, thereby avoiding the presence of metal lines connecting to both diode electrodes in the critical substrate diode area. To this end, contact trenches may be provided so as to locally connect one type of diode electrodes within the contact level. Consequently, additional process steps for planarizing the surface topography upon forming the contact level may be avoided. | 08-04-2011 |
20110189825 | SOI SEMICONDUCTOR DEVICE WITH REDUCED TOPOGRAPHY ABOVE A SUBSTRATE WINDOW AREA - In sophisticated SOI devices, circuit elements, such as substrate diodes, may be formed in the crystalline substrate material on the basis of a substrate window, wherein the pronounced surface topography may be compensated for or at least reduced by performing additional planarization processes, such as the deposition of a planarization material, and a subsequent etch process when forming the contact level of the semiconductor device. | 08-04-2011 |
20110241117 | Semiconductor Device Comprising Metal Gate Structures Formed by a Replacement Gate Approach and eFuses Including a Silicide - In a replacement gate approach for forming high-k metal gate electrode structures, electronic fuses may be provided on the basis of a semiconductor material in combination with a metal silicide by using a recessed surface topography and/or a superior selectivity of the metal silicide material during the replacement gate process. For example, in some illustrative embodiments, electronic fuses may be provided in a recessed portion of an isolation region, thereby avoiding the removal of the semiconductor material when replacing the semiconductor material of the gate electrode structures with a metal-containing electrode material. Consequently, the concept of well-established semiconductor-based electronic fuses may be applied together with sophisticated replacement gate structures of transistors. | 10-06-2011 |
20110244670 | Replacement Gate Approach for High-K Metal Gate Stacks by Avoiding a Polishing Process for Exposing the Placeholder Material - In a replacement gate approach, the exposure of the placeholder material of the gate electrode structures may be accomplished on the basis of an etch process, thereby avoiding the introduction of process-related non-uniformities, which are typically associated with a complex polishing process for exposing the top surface of the placeholder material. In some illustrative embodiments, the placeholder material may be exposed by an etch process based on a sacrificial mask material. | 10-06-2011 |
20110269303 | Reduced Defectivity in Contacts of a Semiconductor Device Comprising Replacement Gate Electrode Structures by Using an Intermediate Cap Layer - Superior contact elements may be formed in semiconductor devices in which sophisticated replacement gate approaches may be applied. To this end, a dielectric cap layer is provided prior to patterning the interlayer dielectric material so that any previously created cracks may be reliably sealed prior to the deposition of the contact material, while the removal of any excess portion thereof may be performed without an undue interaction with the electrode metal of the gate electrode structures. Consequently, a significantly reduced defect rate may be achieved. | 11-03-2011 |
20120001323 | Semiconductor Device Including Ultra Low-K (ULK) Metallization Stacks with Reduced Chip-Package Interaction - In complex semiconductor devices, sophisticated ULK materials may be used in metal line layers in combination with a via layer of enhanced mechanical stability by increasing the amount of dielectric material of superior mechanical strength. Due to the superior mechanical stability of the via layers, reflow processes for directly connecting the semiconductor die and a package substrate may be performed on the basis of a lead-free material system without unduly increasing yield losses. | 01-05-2012 |
20120115326 | Method of Forming Metal Silicide Regions - The method described herein involves the formation of metal silicide regions. The method may involve forming a layer of refractory metal on a structure comprising silicon, forming a layer of silicon on the layer of refractory metal and, after forming the layer of silicon, performing at least one heat treatment process to form a metal silicide region in the structure. | 05-10-2012 |
20120146106 | SEMICONDUCTOR DEVICES HAVING THROUGH-CONTACTS AND RELATED FABRICATION METHODS - Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a layer of dielectric material overlying a doped region formed in a semiconductor substrate adjacent to a gate structure and forming a conductive contact in the layer of dielectric material. The conductive contact overlies and electrically connects to the doped region. The method continues by forming a second layer of dielectric material overlying the conductive contact, forming a voided region in the second layer overlying the conductive contact, forming a third layer of dielectric material overlying the voided region, and forming another voided region in the third layer overlying at least a portion of the voided region in the second layer. The method continues by forming a conductive material that fills both voided regions to contact the conductive contact. | 06-14-2012 |
20120153405 | Semiconductor Device Comprising a Contact Structure with Reduced Parasitic Capacitance - In sophisticated semiconductor devices, at least a portion of the interlayer dielectric material of the contact level may be provided in the form of a low-k dielectric material which may, in some illustrative embodiments, be accomplished on the basis of a replacement gate approach. Hence, superior electrical performance, for instance with respect to the parasitic capacitance, may be accomplished. | 06-21-2012 |
20120153480 | Metallization Systems of Semiconductor Devices Comprising a Copper/Silicon Compound as a Barrier Material - In sophisticated metallization systems of semiconductor devices, a sensitive core metal, such as copper, may be efficiently confined by a conductive barrier material comprising a copper/silicon compound, such as a copper silicide, which may provide superior electromigration behavior and higher electrical conductivity compared to conventionally used tantalum/tantalum nitride barrier systems. | 06-21-2012 |
20120161210 | Embedding Metal Silicide Contact Regions Reliably Into Highly Doped Drain and Source Regions by a Stop Implantation - When forming metal silicide regions, such as nickel silicide regions, in sophisticated transistors requiring a shallow drain and source dopant profile, superior controllability may be achieved by incorporating a silicide stop layer. To this end, in some illustrative embodiments, a carbon species may be incorporated on the basis of an implantation process in order to significantly modify the metal diffusion during the silicidation process. Consequently, an increased thickness of the metal silicide may be provided, while not unduly increasing the probability of creating contact failures. | 06-28-2012 |
20120161324 | Semiconductor Device Comprising Contact Elements with Silicided Sidewall Regions - When forming a metal silicide within contact openings in complex semiconductor devices, a silicidation of sidewall surface areas of the contact openings may be initiated by forming a silicon layer therein, thereby reducing unwanted diffusion of the refractory metal species into the laterally adjacent dielectric material. In this manner, superior reliability and electrical performance of the resulting contact elements may be achieved on the basis of a late silicide process. | 06-28-2012 |
20120181692 | HYBRID CONTACT STRUCTURE WITH LOW ASPECT RATIO CONTACTS IN A SEMICONDUCTOR DEVICE - In sophisticated semiconductor devices, superior contact resistivity may be accomplished for a given contact configuration by providing hybrid contact elements, at least a portion of which may be comprised of a highly conductive material, such as copper. To this end, a well-established contact material, such as tungsten, may be used as buffer material in order to preserve integrity of sensitive device areas upon depositing the highly conductive metal. | 07-19-2012 |
20120190195 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES HAVING LOCAL CONTACTS - Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure that includes a gate structure overlying a semiconductor substrate and a doped region formed in the semiconductor substrate adjacent to the gate structure involves the steps of forming a first layer of dielectric material overlying the gate structure and the doped region, isotropically etching the first layer of dielectric material, forming a second layer of dielectric material overlying the first layer of dielectric material after isotropically etching the first layer, and forming a conductive contact that is electrically connected to the doped region within the first layer and the second layer. | 07-26-2012 |
20120217582 | SOI Semiconductor Device Comprising a Substrate Diode with Reduced Metal Silicide Leakage - When forming substrate diodes in SOI devices, superior diode characteristics may be preserved by providing an additional spacer element in the substrate opening and/or by using a superior contact patterning regime on the basis of a sacrificial fill material. In both cases, integrity of a metal silicide in the substrate diode may be preserved, thereby avoiding undue deviations from the desired ideal diode characteristics. In some illustrative embodiments, the superior diode characteristics may be achieved without requiring any additional lithography step. | 08-30-2012 |
20120223437 | Semiconductor Device Comprising Metallization Layers of Reduced Interlayer Capacitance by Reducing the Amount of Etch Stop Materials - Upon forming a complex metallization system, the parasitic capacitance between metal lines of adjacent metallization layers may be reduced by providing a patterned etch stop material. In this manner, the patterning process for forming the via openings may be controlled in a highly reliable manner, while, on the other hand, the resulting overall dielectric constant of the metallization system may be reduced, thereby also significantly reducing the parasitic capacitance between stacked metal lines. | 09-06-2012 |
20120282765 | Method of Forming Metal Gates and Metal Contacts in a Common Fill Process - The method described herein involves a method of forming metal gates and metal contacts in a common fill process. The method may involve forming a gate structure comprising a sacrificial gate electrode material, forming at least one conductive contact opening in a layer of insulating material positioned adjacent the gate structure, removing the sacrificial gate electrode material to thereby define a gate electrode opening, and performing a common deposition process to fill the conductive contact opening and the gate electrode opening with a conductive fill material. | 11-08-2012 |
20120313176 | Buried Sublevel Metallizations for Improved Transistor Density - Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein electrical interconnects between circuit elements based on a buried sublevel metallization may provide improved transistor density. One illustrative method disclosed herein includes forming a contact dielectric layer above first and second transistor elements of a semiconductor device, and after forming the contact dielectric layer, forming a buried conductive element below an upper surface of the contact dielectric layer, the conductive element providing an electrical connection between the first and second transistor elements. | 12-13-2012 |
20120319285 | INTEGRATED CIRCUITS INCLUDING BARRIER POLISH STOP LAYERS AND METHODS FOR THE MANUFACTURE THEREOF - Embodiments of a method for fabricating integrated circuits are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes the steps of depositing an interlayer dielectric (“ILD”) layer over a semiconductor device, depositing a barrier polish stop layer over the ILD layer, and patterning at least the barrier polish stop layer and the ILD layer to create a plurality of etch features therein. Copper is plated over the barrier polish stop layer and into the plurality of etch features to produce a copper overburden overlying the barrier polish stop layer and a plurality of conductive interconnect features in the ILD layer and barrier polish stop layer. The integrated circuit is polished to remove the copper overburden and expose the barrier polish stop layer. | 12-20-2012 |
20130102147 | Methods of Forming Conductive Structures in Dielectric Layers on an Integrated Circuit Device - One method disclosed herein includes the steps of forming a ULK material layer, forming a hard mask layer above the ULK material layer, forming a patterned photoresist layer above the hard mask layer, performing at least one etching process to define an opening in at least the ULK material layer for a conductive structure to be positioned in at least the ULK material layer, forming a fill material such that it overfills the opening, performing a process operation to remove the patterned photoresist layer and to remove the fill material positioned outside of the opening, removing the fill material from within the opening and, after removing the fill material from within the opening, forming a conductive structure in the opening. | 04-25-2013 |
20130140645 | SEMICONDUCTOR FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES - In a replacement gate approach, the semiconductor material of the gate electrode structures may be efficiently removed during a wet chemical etch process, while this material may be substantially preserved in electronic fuses. Consequently, well-established semiconductor-based electronic fuses may be used instead of requiring sophisticated metal-based fuse structures. The etch selectivity of the semiconductor material may be modified on the basis of ion implantation or electron bombardment. | 06-06-2013 |
20140197544 | SEMICONDUCTOR DEVICE COMPRISING METALLIZATION LAYERS OF REDUCED INTERLAYER CAPACITANCE BY REDUCING THE AMOUNT OF ETCH STOP MATERIALS - Upon forming a complex metallization system, the parasitic capacitance between metal lines of adjacent metallization layers may be reduced by providing a patterned etch stop material. In this manner, the patterning process for forming the via openings may be controlled in a highly reliable manner, while, on the other hand, the resulting overall dielectric constant of the metallization system may be reduced, thereby also significantly reducing the parasitic capacitance between stacked metal lines. | 07-17-2014 |
20140264877 | METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES COMPRISING A COPPER/SILICON COMPOUND AS A BARRIER MATERIAL - A semiconductor device includes a first metallization layer positioned above a substrate of the semiconductor device, the metallization layer including a dielectric material and a copper-containing metal region embedded in the dielectric material. The semiconductor device also includes a conductive barrier layer positioned along substantially an entirety of an interface between the copper-containing metal region and the dielectric material, the conductive barrier layer including a copper/silicon compound that is in direct contact with the dielectric material along substantially the entirety of the interface. | 09-18-2014 |