Patent application number | Description | Published |
20100053575 | Thermal Control For EUV Lithography - A method of patterning an integrated circuit including generating a thermal profile of a reticle is provided. The thermal profile of the reticle may illustrate heat accumulation (e.g., a temperature) in a EUV reticle due an incident EUV radiation beam. The thermal profile may be determined using the pattern density of the reticle. The reticle is irradiated with a radiation beam having an extreme ultraviolet (EUV) wavelength. A thermal control profile may be generated using the thermal profile, which may define a parameter of the lithography process such as, a temperature gradient of a thermal control chuck. The thermal control profile may be downloaded to the EUV lithography tool (e.g., scanner or stepper) for use in a process. A separate thermal control profile may be provided for different reticles. | 03-04-2010 |
20100183961 | INTEGRATED CIRCUIT LAYOUT DESIGN - Provided is a method including layout design of an integrated circuit. A first pattern is provided. The first pattern includes an array of dummy line features and a plurality of spacer elements abutting the dummy line features. A second pattern is provided. The second pattern defines an active region of an integrated circuit device. An edge spacer element of the active region is determined. A dummy line feature of the array of dummy line features is biased (e.g., increased in width), the dummy line feature is adjacent an edge spacer element. | 07-22-2010 |
20100203734 | METHOD OF PITCH HALVING - The present disclosure provides a method of fabricating a semiconductor device that includes forming a mask layer over a substrate, forming a dummy layer having a first dummy feature and a second dummy feature over the mask layer, forming first and second spacer roofs to cover a top portion of the first and second dummy features, respectively, and forming first and second spacer sleeves to encircle side portions of the first and second dummy features, respectively, removing the first spacer roof and the first dummy feature while protecting the second dummy feature, removing a first end portion and a second end portion of the first spacer sleeve to form spacer fins, and patterning the mask layer using the spacer fins as a first mask element and the second dummy feature as a second mask element. | 08-12-2010 |
20110151359 | INTEGRATED CIRCUIT LAYOUT DESIGN - Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality, of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region. | 06-23-2011 |
20120021589 | METHOD OF FABRICATION OF A SEMICONDUCTOR DEVICE HAVING REDUCED PITCH - Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region. | 01-26-2012 |
20120244460 | MECHANISMS FOR PATTERNING FINE FEATURES - The embodiments described provide mechanisms for patterning features for advanced technology nodes with extreme ultraviolet lithography (EUVL) tools. One or more EUV pre-masks are generated by using a mask writer to form an EUV mask with an EUV scanner. The wafers are then patterned by using the EUV mask. The demagnification factor of the EUV scanner(s) used in preparing the EUV mask by exposing the EUV pre-mask(s) enable the wafers prepared by such mechanisms to meet the requirements for the advanced technology nodes. | 09-27-2012 |
Patent application number | Description | Published |
20090032891 | STRUCTURE OF MAGNETIC RANDOM ACCESS MEMORY AND FABRICATION METHOD THEREOF - A structure of magnetic random access memory includes a magnetic memory cell formed on a substrate. An insulating layer covers over the substrate and the magnetic memory cell. A write current line is in the insulating layer and above the magnetic memory cell. A magnetic cladding layer surrounds the periphery of the write current line. The magnetic cladding layer includes a first region surrounding the top of the write current line, and a second region surrounding the side edge of the write current line, and extending towards the magnetic memory cell and exceed by a distance. | 02-05-2009 |
20100109109 | MAGNETIC MEMORY ELEMENT UTILIZING SPIN TRANSFER SWITCHING - A magnetic memory element utilizing spin transfer switching includes a pinned layer, a tunneling barrier layer and a free layer structure. The tunneling barrier layer is disposed on the pinned layer. The free layer structure includes a composite free layer. The composite free layer includes a first free layer, an insert layer and a second free layer. The first free layer is disposed on the tunneling barrier layer and has a first spin polarization factor and a first saturation magnetization. The insert layer is disposed on the first free layer. The second free layer is disposed on the insert layer and has a second spin polarization factor smaller than the first spin polarization factor and a second saturation magnetization smaller than the first saturation magnetization. Magnetization vectors of the first free layer and the second free layer are arranged as parallel-coupled. | 05-06-2010 |
20110001203 | MAGNETIC MEMORY ELEMENT UTILIZING SPIN TRANSFER SWITCHING - A magnetic memory element includes a pinned layer, a tunneling barrier layer, a free layer and a stabilizing layer. The tunneling barrier layer is disposed on the pinned layer. The free layer is disposed on the tunneling barrier layer. The stabilizing layer is disposed on the free layer. | 01-06-2011 |
20110159316 | MAGNETORESISTIVE DEVICE WITH PERPENDICULAR MAGNETIZATION - A magnetoresistive device with perpendicular magnetization includes a magnetic reference layer, a first magnetic multi-layer film, a tunneling barrier layer, a second magnetic multi-layer film, and a magnetic free layer. The magnetic reference layer has a first magnetization direction, perpendicular to the magnetic reference layer. The first magnetic multi-layer film, having non-magnetic material layer, is disposed in contact on the magnetic reference layer. The tunneling barrier layer is disposed in contact on the first magnetic multi-layer film. The second magnetic multi-layer film, having non-magnetic material layer, is disposed in contact on the tunneling barrier layer. The magnetic free layer is disposed in contact on the second magnetic multi-layer film, having a second magnetization direction capable of being switched to be parallel or anti-parallel to the first magnetization direction. | 06-30-2011 |
20110241139 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory (MRAM) has a perpendicular magnetization direction. The MRAM includes a first magnetic layer, a second magnetic layer, a first polarization enhancement layer, a second polarization enhancement layer, a barrier layer, a spacer, and a free assisting layer. A pinned layer formed by the first magnetic layer and the first polarization enhancement layer has a first magnetization direction and a first perpendicular magnetic anisotropy. A free layer formed by the second magnetic layer and the second polarization enhancement layer has a second magnetization direction and a second perpendicular magnetic anisotropy. The barrier layer is disposed between the first polarization enhancement layer and the second polarization enhancement layer. The spacer is disposed on the second magnetic layer. The free assisting layer is disposed on the spacer and has an in-plane magnetic anisotropy. The spacer and the barrier layer are on opposite sides of the free layer. | 10-06-2011 |
20120068698 | STRUCTURE OF TMR AND FABRICATION METHOD OF INTEGRATED 3-AXIS MAGNETIC FIELD SENSOR AND SENSING CIRCUIT - A structure of TMR includes two magnetic tunneling junction (MTJ) devices with the same pattern and same magnetic film stack on a same conducting bottom electrode and a parallel connection of conducting top electrode. Each MTJ device includes a pinned layer on the bottom electrode, having a pinned magnetization; a non-magnetic tunneling on the pinned layer; and a free layer on the tunneling layer, having a free magnetization. These two MTJ devices have a collinear of easy-axis and their pinned magnetizations all are parallel to a same pinned direction which has an angle of 45 degree to easy-axis; their free magnetizations initially are parallel to the easy-axis but directions are mutual anti-parallel by applying a current generated ampere field. The magnetic field sensing direction is perpendicular to the easy-axis on the substrate. | 03-22-2012 |
20130161736 | TRENCH METAL OXIDE SEMICONDUCTOR TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF - A trench metal oxide semiconductor transistor device and a manufacturing method thereof are described. The trench metal oxide semiconductor transistor device includes a substrate of a first conductivity type, a drift region of the first conductivity type, a deep trench doped region of a second conductivity type, an epitaxial region of the second conductivity type, a trench gate, a gate insulating layer, a source region, a drain electrode and a source electrode. The drift region has at least one deep trench therein, and the deep trench doped region is disposed in the deep trench. The trench gate passes through the epitaxial region, and a distance between a bottom of the trench gate and a bottom of the deep trench doped region is 0.5˜3 um. | 06-27-2013 |
20140001489 | DOUBLE-RECESSED TRENCH SCHOTTKY BARRIER DEVICE | 01-02-2014 |
20140145207 | Schottky Barrier Diode and Fabricating Method Thereof - A Schottky barrier diode and fabricating method thereof are disclosed. A semiconductor substrate may have a first surface and a second surface positioned oppositely to be provided. Several trenches are formed on the first surface. Each trench has a sidewall with a first depth and a first bottom surface. An insulating material is formed on the first surface of the semiconductor substrate and on the sidewall and the first bottom surface of each trench, wherein the insulating material has a first thickness on the sidewall. The insulating material on the sidewall is patterned to define a second bottom surface having a second depth smaller than the first depth, and the removed portion of the insulating material on the sidewall has a second thickness smaller than the first thickness. Afterward, a contact metal layer is at least formed on the first surface between adjacent trenches. | 05-29-2014 |
20140159053 | SIC TRENCH GATE TRANSISTOR WITH SEGMENTED FIELD SHIELDING REGION AND METHOD OF FABRICATING THE SAME - A SiC trench gate transistor with segmented field shielding region is provided. A drain region of a first conductivity type is located in a substrate. A first drift layer of the first conductivity type is located on the substrate and a second drift layer of the first conductivity type is located on the first drift layer. A base region of a second conductivity type is located on the second drift layer. A gate trench is located between the adjacent base regions. A plurality of segmented field shielding regions of the second conductivity type is placed under a bottom of the gate trench and the space between segmented field shielding regions is the first drift region. A gate dielectric layer is located on a bottom and at a sidewall of the gate trench and a trench gate is formed in the gate trench. | 06-12-2014 |
20140167151 | STEPPED TRENCH MOSFET AND METHOD OF FABRICATING THE SAME - A step trench metal-oxide-semiconductor field-effect transistor comprises a drift layer, a first semiconductor region, a stepped gate and a floating region. The drift layer is of a first conductivity type. The first semiconductor region is of a second conductivity type and located on the drift layer, wherein the drift layer and the first semiconductor region have a stepped gate trench therein. The stepped gate trench at least comprises a first recess located in the first semiconductor region and extending into the drift layer and a second recess located below a bottom of the first recess, wherein a width of the second recess is smaller than a width of the first recess. A floating region is of the second conductivity type and located in the drift layer below the second recess. | 06-19-2014 |
20140175559 | INTEGRATED DEVICE HAVING MOSFET CELL ARRAY EMBEDDED WITH BARRIER SCHOTTKY DIODE - Provided is an integrated device having a MOSFET cell array embedded with a junction barrier Schottky (JBS) diode. The integrated device comprises a plurality of areas, each of which includes a plurality of MOS transistor cells and at least one JBS diode. Any two adjacent MOS transistor cells are separated by a separating line. A first MOS transistor cell and a second MOS transistor cell are adjacent in a first direction and separated by a first separating line, and the first transistor cell and a third MOS transistor cell are adjacent in a second direction and separated by a second separating line. The JBS diode is disposed at an intersection region between the first separating line and the second separating line. The JBS diode is connected in anti-parallel to the first, second and third MOS transistor cells. | 06-26-2014 |
20140176132 | MAGNETIC FIELD SENSORS AND SENSING CIRCUITS - A magnetic sensor for sensing an external magnetic field includes first and second electrodes and first and second magnetic tunneling junctions. The first and second electrodes are disposed over a substrate; and the first and second magnetic tunneling junctions are conductively disposed between the first and second electrodes and connected in parallel between the first and second electrodes. The first and second magnetic tunneling junctions are arranged along a first easy axis of the magnetic sensor. The first magnetic tunneling junction includes a first pinned magnetization and a first free magnetization, and the second magnetic tunneling junction includes a second pinned magnetization and a second free magnetization. The first free magnetization and the second free magnetization are arranged substantially in parallel to the first easy axis and in substantially opposite directions. | 06-26-2014 |
Patent application number | Description | Published |
20100165704 | Circuit and Method for a High Speed Memory Cell - A memory cell is disclosed, including a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node; and a storage capacitor coupled between the read word line and the storage node. Methods for operating the memory cell are also disclosed. | 07-01-2010 |
20120020177 | ELECTRICAL FUSE MEMORY - Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row. | 01-26-2012 |
20120086495 | VOLTAGE LEVEL SHIFTER - An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node. | 04-12-2012 |
20120257435 | NON-SALICIDE POLYSILICON FUSE - The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a non-salicided polysilicon fuse. The non-salicided polysilicon fuse and a programming transistor form a one-time programmable (OTP) memory cell, which can be programmed with a low programming voltage. | 10-11-2012 |
20130075856 | Integrated Circuit Structure and Method of Forming the Same - An embodiment is an integrated circuit (IC) structure. The structure comprises a deep n well in a substrate, a first pickup device in the deep n well, a first signal device in the deep n well, a dissipation device in the substrate, a second signal device in the substrate, a first electrical path between the first pickup device and the dissipation device, and a second electrical path between the first signal device and the second signal device. The dissipation device is outside of the deep n well, and the second signal device is outside of the deep n well. A highest point of the first electrical path is lower than a highest point of the second electrical path. | 03-28-2013 |
20130155799 | ELECTRICAL FUSE MEMORY - A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on. | 06-20-2013 |
20130256801 | INTEGRATED CIRCUIT STRUCTURE TO RESOLVE DEEP-WELL PLASMA CHARGING PROBLEM AND METHOD OF FORMING THE SAME - During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW. | 10-03-2013 |
Patent application number | Description | Published |
20080217923 | Hydraulic powered electric generator device - A hydraulic powered electric generator device includes a tubular member having a housing, a partition and a receptacle secured to the housing, a paddle wheel rotatably disposed in the housing for being rotated by the water flowing through the tubular member, an electric generator disposed in the receptacle for generating the electric energy and a follower coupled to the spindle of the electric generator, and one or more magnetic members are attached to the follower and attached to the paddle wheel for allowing the follower and the electric generator to be driven by the paddle wheel and for actuating the electric generator to effectively generate an electric energy. | 09-11-2008 |
20100019676 | Electric generator for bicycle - An electric generator for a bicycle includes a housing for attaching to a bicycle frame, a rotary member rotatably received in the housing for engaging with an axle of the bicycle, a reduction gearing received in the housing and engaged with the rotary member, a motor received in the housing and having a pinion attached to a spindle and engaged with the reduction gearing for being driven by the reduction gearing and the rotary member and for generating an electric energy, a battery electrically coupled to the motor for receiving and storing the electric energy generated by the motor and for supplying the electric energy to energize a light device, or other electric facilities. | 01-28-2010 |
20100073922 | Convertible light device - A light device includes a reflector disposed in a housing, a frame attached to an upper portion of the housing and having an axle extended into a notch of the frame, and having one or more projections extended from the axle, a carrier includes a protrusion rotatably secured to the frame with the axle and includes a number of depressions for engaging with the projection of the axle and for anchoring the carrier to the frame at selected angular positions, and the carrier includes a curved opening for rotatably attaching a spherical casing, a circuit board is disposed in the casing and includes a light member, the casing and the light member are rotatable relative to the housing and the frame and the carrier. | 03-25-2010 |
20100259211 | Recharge battery safely chargeable with solar energy - A recharge battery device includes a solar charge coupled to a alkaline recharge battery for supplying a solar energy to the alkaline recharge battery, an inner recharge battery coupled to the alkaline recharge battery, a safeguard and a voltage detector coupled to the alkaline recharge battery for actuating the safeguard to cut off the energy to the alkaline recharge battery when the alkaline recharge battery may not be suitably recharged or charged, or when the alkaline recharge battery is overflow or overcharged, or when too much energy is supplied to the alkaline recharge battery, and for preventing the alkaline recharge battery from being overcharged or damaged. | 10-14-2010 |
20110049979 | Portable electric energy supplying device - An electric energy supplying device includes a set-up circuit coupled to an electric energy source, a limited current circuit and a voltage regulator coupled to the set-up circuit, a battery coupled to the set-up circuit with a charge electrocircuit for being charged by the electric energy the charge electrocircuit, another set-up circuit is coupled to the battery for receiving the electric energy from the battery and includes an output device for coupling and supplying the DC electric energy to a failed or weak or not charged battery of a vehicle, and an inverter circuit is coupled to the battery and includes an output device for coupling and supplying the AC electric energy to charge various electric facilities. | 03-03-2011 |
20110140675 | Charging device for different batteries - A battery charging device includes one or more current control converting circuits connected to a voltage stabilization circuit for controlling the charging current through the rechargeable batteries of different voltages or currents or types, one or more protection converting circuits or overcharging protection circuits for protecting the batteries from being overcharged, one or more uninterrupted and reverse charging prevented circuits for protecting the batteries from being charged backwardly, and one or more charging state instruction circuits for indicating the charging status of the batteries and for allowing the different types of rechargeable batteries to be charged with a single charging device. | 06-16-2011 |
Patent application number | Description | Published |
20080282094 | Optical storage media and the corresponding cryptography for data encryption thereof - Based on the demand of developing a data encryption technique for the optical storage media, the present invention discloses a cryptography for data encryption based on a design of specific hardware conditions, so as to achieve the security requirements for the encrypted digital data stored in the optical storage media and the design requirements for the security issues on the optical storage media for software vendors in the current market. | 11-13-2008 |
20080320248 | Computer system architecture and operating method for the operating system thereof - In order to develop a mobile operating system for a computer, first the mobile operating system must be independent from the computer hardware device. Therefore, the present invention discloses a new computer system architecture which loads a Transient Resident Operating System (TROS) from an external device and provides a predefined hardware device driver to the operating system, and then the TROS can be stored into a portable memory storage device to be a Mobile Operating System (MOS). By applying the technique disclosed in the present invention, the TROS can work beyond the Intrinsic Operating System (IOS) of the computer without the mutual interference from each other, such that a computer environment with a Parasitic Operating System (POS) is created. | 12-25-2008 |
20090165025 | Computer system architecture and operating method for the operating system thereof - In order to develop a mobile operating system for a computer, first the mobile operating system must be independent from the computer hardware device. Therefore, the present invention discloses a new computer system architecture which loads a Transient Resident Operating System (TROS) from an external device and provides a predefined hardware device driver to the operating system, and then the TROS can be stored into a portable memory storage device to be a Mobile Operating System (MOS). By applying the technique disclosed in the present invention, the TROS can work beyond the Intrinsic Operating System (IOS) of the computer without the mutual interference from each other, such that a computer environment with a Parasitic Operating System (POS) is created. | 06-25-2009 |
20090240933 | Computer system architecture and operating method for the operating system thereof - In order to develop a mobile operating system for a computer, first the mobile operating system must be independent from the computer hardware device. Therefore, the present invention discloses a new computer system architecture which loads a Transient Resident Operating System (TROS) from an external device and provides a predefined hardware device driver to the operating system, and then the TROS can be stored into a portable memory storage device to be a Mobile Operating System (MOS). By applying the technique disclosed in the present invention, the TROS can work beyond the Intrinsic Operating System (IOS) of the computer without the mutual interference from each other, such that a computer environment with a Parasitic Operating System (POS) is created. | 09-24-2009 |
20110213989 | OPTICAL STORAGE MEDIA AND THE CORRESPONDING CRYPTOGRAPHY FOR DATA ENCRYPTION THEREOF - Based on the demand of developing a data encryption technique for the optical storage media, the present invention discloses a cryptography for data encryption based on a design of specific hardware conditions, so as to achieve the security requirements for the encrypted digital data stored in the optical storage media and the design requirements for the security issues on the optical storage media for software vendors in the current market. | 09-01-2011 |
Patent application number | Description | Published |
20100156791 | TEMPERATURE CONTROLLED MOUSE - A temperature controlled mouse includes a central controller, a driver control circuit, a temperature control circuit, and a signal transmitting circuit. The driver control circuit generates coordinate control signals and pointer clicking signals, and the signals are transmitted to a host computer coupled to the mouse via the signal transmitting circuit. The temperature control circuit detects the changes of the temperature from a user's hand and thereby generates temperature control signals. The central controller controls the operation status of the mouse according to the temperature control signals, wherein when the temperature detected is within a predetermined temperature range, the central controller wakes the mouse and allows the transmission of signals from the mouse to the host computer; otherwise the central controller stops the transmission of signals. The temperature controlled mouse prevents accidental activation due to negligent bump. Thereby the mouse may only wake from purposeful control and thereby conserves energy. | 06-24-2010 |
20100164388 | LUMINOUS SYSTEM AND METHOD WITH A CHANGEABLE COLOR LIGHT - A luminous system with a changeable color light applicable to an electronic device is provided. The system includes a light emitter for emitting a first light to outside of the electronic device, a color sensor for receiving a second light that is the reflection of the first light from an object and generating a RGB signal, and a central controller for receiving the RGB signal and generating a backlight color adjusting signal according to the RGB signal received. A backlight driver module of the device is further introduced to drive a backlight module to emit a third light according to the adjusting signal. The color of the third light is particularly the same as the second light. Thus the backlight color of the electronic device changes as what the color of the object is. The visual effect of the product can be alternative by providing this changeable color light. | 07-01-2010 |
20110012611 | TESTING METHOD FOR ELECTRONIC APPARATUS - An electronic apparatus includes a first power contact, a second power contact, and a control unit. The first power contact is electrically connected with an anode of a power supply source, and the second power contact is electrically connected with a cathode of the power supply source. The control unit electrically connects the first power contact and the second power contact for forming a signal transmission path and receiving the power generated by the power supply source. When the control unit is operated in a testing mode, the control unit operates in a working mode or a sleeping mode according to an instruction of a default instruction set for changing a current waveform signal transmitted over the signal transmission path, so as to achieve the purpose of providing a convenient and high-efficiency testing. | 01-20-2011 |
20110050577 | WIRELESS PERIPHERAL DEVICE AND PRODUCTION MATCHING SYSTEM THEREOF - Provided is a wireless peripheral device. Preferably the wireless peripheral device includes an operating main body and a receiver. The operating main body particularly has a controlling unit having built-in identification code. This identification code is particularly stored in a non-volatile memory of the controlling unit. The receiver, corresponding to the operating main body, pre-stores the matched identification code. The receiver acquires the power supplied from a computer system as connected therewith. Automatically, the operating main body and the receiver are wirelessly connected in accordance with the identification code. It is featured that the cost of the wireless peripheral device can be effectively reduced, and the related matching procedure can also be simplified before factory shipment. | 03-03-2011 |
Patent application number | Description | Published |
20110289541 | PORTABLE SET-TOP BOX - A portable set-top box includes a network connecting module, an AV receiving module, an information receiving module, a AV display module and a controlling module. The network connecting module is utilized for building up a network connection. The AV receiving module is utilized for receiving an AV signal. The information receiving module is utilized for receiving an information from Internet, local PCs, or machines, including sensor devices and peripherals. The AV display module is coupled to the AV receiving module and the information receiving module, and utilized for driving an external display device to display the information or the AV signal. In addition, the controlling module is coupled to the network connecting module and the information receiving module, and utilized for controlling that the information is transmitted via the network connection. | 11-24-2011 |
20120090001 | APPARATUS HAVING MULTIMEDIA INTERFACE AND NETWORK ACCESS MANAGEMENT INTEGRATED THEREIN - An apparatus includes a multimedia interface module and a network module. The multimedia interface module has a plurality of connection ports including at least an input port and at least an output port, and supports network data transmission. The network module, coupled to the multimedia interface module via a first network protocol, is for accessing a network, wherein the multimedia interface module is arranged for selectively coupling the network module to one of the connection ports. | 04-12-2012 |
20130142112 | METHOD OF SWITCHING DATA NETWORK FOR NETWORK APPARATUS, NETWORK APPARATUS, AND NETWORK SYSTEM - A network apparatus and a method of switching a data network for a network apparatus are provided. The network apparatus includes a plurality of User Identity Modules (UIMs), a transceiver module, and a switching unit. The UIMs are used to provide a plurality of network service plans, wherein the network apparatus operates in a first network service plan corresponding to a first UIM of the UIMs. The transceiver module is arranged to receive a plurality of network packets corresponding to the network service plans. The switching unit is arranged to obtain a plurality of corresponding network connection information from the network packets, performing an information-matching operation upon the plurality of corresponding network connection information to generate a matching result by referring to a profile database, and determining if the network apparatus is required to be switched to operate in a second network service plan according to the matching result. | 06-06-2013 |
Patent application number | Description | Published |
20090027942 | SEMICONDUCTOR MEMORY UNIT AND ARRAY - A memory unit comprising a gate electrode, a gate dielectric under said gate electrode, an active area and a metal-semiconductor compound layer is provided. The active area comprises a first source/drain region, a second source/drain region, a normal field channel region formed under said gate electrode, a fringing field channel region formed between said first source/drain region and said normal field channel region, a pocket implantation region formed under the fringing or normal field channel regions and an extension doping region formed between said second source/drain region and said normal field channel region. The metal-semiconductor compound layer is formed over said gate electrode, first source/drain region and second source/drain region. | 01-29-2009 |
20130026539 | REPLACEMENT SOURCE/DRAIN FINFET FABRICATION - A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor. | 01-31-2013 |
20130187207 | REPLACEMENT SOURCE/DRAIN FINFET FABRICATION - A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched to expose a first region of the fin. A portion of the first region is then doped with a dopant. | 07-25-2013 |
20140054679 | DOPING A NON-PLANAR SEMICONDUCTOR DEVICE - In doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. A first ion implant is performed in a region of the non-planar semiconductor body. The first ion implant has a first implant energy and a first implant angle. A second ion implant is performed in the same region of the non-planar semiconductor body. The second ion implant has a second implant energy and a second implant angle. The first implant energy may be different from the second implant energy. Additionally, the first implant angle may be different from the second implant angle. | 02-27-2014 |
20140097487 | PLASMA DOPING A NON-PLANAR SEMICONDUCTOR DEVICE - In plasma doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. The substrate having the non-planar semiconductor body may be placed into a chamber. A plasma may be formed in the chamber and the plasma may contain dopant ions. A first bias voltage may be generated to implant dopant ions into a region of the non-planar semiconductor body. A second bias voltage may be generated to implant dopant ions into the same region. In one example, the first bias voltage and the second bias voltage may be different. | 04-10-2014 |
20140175568 | REPLACEMENT SOURCE/DRAIN FINFET FABRICATION - A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor. | 06-26-2014 |
20150031181 | REPLACEMENT SOURCE/DRAIN FINFET FABRICATION - A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor. | 01-29-2015 |
Patent application number | Description | Published |
20100200064 | DYE-SENSITIZING SOLAR CELL AND FABRICATING METHOD THEREOF - A dye-sensitizing solar cell (DSSC) is provided. The DSSC includes a working electrode, a counter electrode disposed opposite to the working electrode, a first gap control layer disposed between the working electrode and the counter electrode, a packaging material, and an electrolyte. The working electrode has a first patterned conductive line. The counter electrode has a second patterned conductive line. The first gap control layer is located on at least an outer portion of one of the first and the second patterned conductive lines to surround at least the first and the second patterned conductive lines or is symmetrically located on one of the first and the second patterned conductive lines. The packaging material is disposed on the first gap control layer such that the working electrode, the counter electrode, the first gap control layer, and the packaging material form a gap. The electrolyte is disposed in the gap. | 08-12-2010 |
20120202308 | FABRICATING METHOD OF DYE-SENSITIZING SOLAR CELL - A fabricating method of a dye-sensitizing solar cell (DSSC) is provided. In the method, a working electrode and a counter electrode disposed opposite to each other is provided. The working electrode has a first patterned conductive line, and the counter electrode has a second patterned conductive line. A first gap control layer on at least an outer portion of one of the first and second patterned conductive lines is formed to surround the first and the second patterned conductive lines. Alternatively, the first gap control layer is symmetrically formed on one of the first and second patterned conductive lines. Then, a packaging material is formed on the first gap control layer. Next, the working electrode and the counter electrode are pressed to form a gap between the working electrode and the counter electrode. The packaging material is cured, and an electrolyte is filled into the gap. | 08-09-2012 |
20130000703 | COMPLEX DYE-SENSITIZED PHOTOVOLTAIC APPARATUS - An embodiment of the invention provides a complex dye-sensitized photovoltaic apparatus including a conductive substrate, a counter electrode, a partition member, a photoelectric conversion layer, a first electrolyte, and a charge storage device or an electrochromic solution. A space is provided between the counter electrode and the conductive substrate. The partition member is disposed in the space, dividing the space into a first chamber and a second chamber. The photoelectric conversion layer is disposed on the conductive substrate in the first chamber filled with the first electrolyte, wherein the photoelectric conversion layer includes a porous semiconductor film and a dye absorbed on the porous semiconductor film. The photoelectric conversion layer and the conductive substrate form a working electrode. The charge storage device or the electrochromic solution is disposed in the second chamber. | 01-03-2013 |
Patent application number | Description | Published |
20110263072 | FORMING CHALCOGENIDE SEMICONDUCTOR ABSORBERS - Sulfur-containing chalcogenide absorbers in thin film solar cell are manufactured by sequential sputtering or co-sputtering targets, one of which contains a sulfur compound, onto a substrate and then annealing the substrate. The anneal is performed in a non-sulfur containing environment and avoids the use of hazardous hydrogen sulfide gas. A sulfurized chalcogenide is formed having a sulfur concentration gradient. | 10-27-2011 |
20130037093 | SUPERSTRATE SOLAR CELL - A method of fabricating a solar cell includes forming a front contact layer over a substrate, and the front contact layer is optically transparent at specified wavelengths and electrically conductive. A first scribed area is scribed through the front contact layer to expose a portion of the substrate. A buffer layer doped with an n-type dopant is formed over the front contact layer and the first scribed area. An absorber layer doped with a p-type dopant is formed over the buffer layer. A back contact layer that is electrically conductive is formed over the absorber layer. | 02-14-2013 |
20130075247 | METHOD AND SYSTEM FOR FORMING CHALCOGENIDE SEMICONDUCTOR MATERIALS USING SPUTTERING AND EVAPORATION FUNCTIONS - A method and system for forming a chalcogenide or chalcopyrite-based semiconductor material provide for the simultaneous deposition of metal precursor materials from a target and Se radials from a Se radical generation system. The Se radical generation system includes an evaporator that produces an Se vapor and a plasma chamber that uses a plasma to generate a flux of Se radicals. Multiple such deposition operations may take place in sequence, each having the deposition temperature accurately controlled. The deposited material may include a compositional concentration gradient or may be a composite material, and may be used as an absorber layer in a solar cell. | 03-28-2013 |
20130118569 | METHOD FOR FORMING THIN FILM SOLAR CELL WITH BUFFER-FREE FABRICATION PROCESS - A thin film solar cell and process for forming the same. The solar cell includes a bottom electrode layer, a light absorbing semiconductor layer, and top electrode layer. The absorber layer includes a p-type interior region and an n-type exterior region formed around the perimeter of the layer from a modified native portion of the p-type interior region, thereby forming an active n-p junction that is an intrinsic part of the absorber layer. The top electrode layer is electrically connected to the bottom electrode layer via a scribe line formed in the absorber layer that defines sidewalls. The n-type exterior region of the absorber layer extends along both the horizontal top of the absorber layer, and onto the vertical sidewalls of the scribe line to increase the area of available n-p junction in the solar cell thereby improving solar conversion efficiency. | 05-16-2013 |
20130153015 | METHOD FOR FORMING SOLAR CELLS - A thin film solar cell and process for forming the same. The solar cell includes a bottom electrode layer, semiconductor light absorbing layer, top electrode layer, and a protective moisture barrier layer. In some embodiments, the barrier layer is formed of a water-insoluble material. The barrier layer helps protect the top electrode layer from exposure and damage caused by water and oxygen. | 06-20-2013 |
20130327393 | SUPERSTRATE SOLAR CELL - A method of fabricating a solar cell includes forming a front contact layer over a substrate, and the front contact layer is optically transparent at specified wavelengths and electrically conductive. A first scribed area is scribed through the front contact layer to expose a portion of the substrate. A buffer layer doped with an n-type dopant is formed over the front contact layer and the first scribed area. An absorber layer doped with a p-type dopant is formed over the buffer layer. A back contact layer that is electrically conductive is formed over the absorber layer. | 12-12-2013 |
20140109958 | METHOD OF IN-SITU FABRICATING INTRINSIC ZINC OXIDE LAYER AND THE PHOTOVOLTAIC DEVICE THEREOF - A method of fabricating a photovoltaic device includes forming an absorber layer for photon absorption over a substrate, forming a buffer layer above the absorber layer, wherein both the absorber layer and the buffer layer are semiconductors, and forming a layer of intrinsic zinc oxide above the buffer layer through a hydrothermal reaction in a solution of a zinc-containing salt and an alkaline chemical. | 04-24-2014 |
20140130856 | MOLYBDENUM SELENIDE SUBLAYERS WITH CONTROLLED THICKNESS IN SOLAR CELLS AND METHODS FOR FORMING THE SAME - A solar cell with a molybdenum back electrode layer and a molybdenum selenide ohmic contact layer over the molybdenum back electrode, is provided. The molybdenum selenide layer includes an accurately controlled thickness. A distinct interface exists between the molybdenum back electrode layer and the molybdenum silicide layer. The molybdenum silicide layer is produced by forming a molybdenum layer or a molybdenum nitride layer or a molybdenum oxide layer over an initially formed molybdenum layer such that an interface exists between the two layers. A selenization and sulfurization process is carried out to selectively convert the molybdenum-containing layer to molybdenum selenide but not the original molybdenum back electrode layer which remains as a molybdenum layer. | 05-15-2014 |
20140144769 | SPUTTERING APPARATUS AND METHOD - A sputtering apparatus comprises a chamber configured to contain at least one sputter target and at least one substrate to be coated. The chamber has at least one adjustable shielding member defining an adjustable aperture. The member is positioned between the at least one sputter target and the at least one substrate. The aperture is adjustable in at least one of the group consisting of area and shape. | 05-29-2014 |
20140206132 | METHOD FOR INDIUM SPUTTERING AND FOR FORMING CHALCOPYRITE-BASED SOLAR CELL ABSORBER LAYERS - A solar cell includes an absorber layer formed of a CIGAS, copper, indium, gallium, aluminum, and selenium. A method for forming the absorber layer provides for using an indium-aluminum target and depositing an aluminum-indium film as a metal precursor layer using sputter deposition. Additional metal precursor layers such as a | 07-24-2014 |
20140352751 | SOLAR CELL OR TANDEM SOLAR CELL AND METHOD OF FORMING SAME - A solar cell includes an absorber layer, a buffer layer on the absorber layer, a front contact layer where a glass substrate, a back contact layer on the glass substrate, the absorber layer on the back contact layer, the buffer layer, and the front contact layer are manufactured as a first module at a temperature exceeding 500 degrees Celsius. The solar further includes an extracted portion from the first module where the extracted portion includes the absorber layer, the buffer layer, and the front contact layer, and where the extracted portion is applied to a flexible substrate or other substrate. | 12-04-2014 |
20140360864 | APPARATUS AND METHODS FOR FORMING CHALCOPYRITE LAYERS ONTO A SUBSTRATE - A method generally comprises providing heat to a substrate in at least one buffer chamber and transferring the substrate to at least one deposition chamber that is coupled to the buffer chamber via an conveyor. The method also includes depositing a first set of a plurality of elements, using sputtering, and a second set of a plurality of elements, using evaporation, onto at least a portion of the substrate in the deposition chamber. | 12-11-2014 |
20140366935 | THIN FILM SOLAR CELL AND METHOD OF FORMING SAME - A solar cell device with improved performance and a method of fabricating the same is described. The solar cell includes a back contact layer formed on a substrate, an absorber layer formed on the back contact layer, a buffer layer formed on the absorber layer, and a front contact layer formed by depositing a transparent conductive oxide layer on the buffer layer and annealing the deposited TCO layer. | 12-18-2014 |
20140370623 | EVAPORATION APPARATUS AND METHOD - An evaporation apparatus comprises a chamber configured to contain at least one dispensing nozzle and at least one substrate to be coated. The chamber has at least one adjustable shielding member defining an adjustable aperture. The member is positioned between the at least one dispensing nozzle and the at least one substrate. The aperture is adjustable in at least one of the group consisting of area and shape. The at least one adjustable shielding member has a heater. | 12-18-2014 |
20150034160 | THIN FILM PHOTOVOLTAIC DEVICE AND METHOD OF MAKING SAME - A photovoltaic device includes a substrate; a back contact layer disposed on the substrate; an absorber layer for photo absorption disposed above the back contact layer; a buffer layer disposed above the absorber layer; a front contact layer disposed above the buffer layer; and a plasmonic nanostructured layer having a plurality of nano-particles, wherein the plasmonic nanostructured layer is between a topmost back contact layer surface and the absorber layer. | 02-05-2015 |
20150044814 | APPARATUS AND METHOD FOR FORMING CHALCOGENIDE SEMICONDUCTOR ABSORBER MATERIALS WITH SODIUM IMPURITIES - A method and system for forming chalcogenide semiconductor absorber materials with sodium impurities is provided. The system includes a sodium vaporizer in which a solid sodium source material is vaporized. The sodium vapor is added to reactant gases and/or annealing gases and directed to a furnace that includes a substrate with a metal precursor material. The precursor material reacts with reactant gases such as S-containing gases and Se-containing gases according to various process sequences. In one embodiment, a selenization operation is followed by an annealing operation and a sulfurization operation and the sodium vapor is caused to react with the metal precursor during at least one of the annealing and the sulfurization steps to produce a chalcogenide semiconductor absorber material that includes sodium dopant impurities. | 02-12-2015 |
20150059850 | PHOTOVOLTAIC DEVICE WITH BACK REFLECTOR - A device and method of improving efficiency of a thin film solar cell by providing a back reflector between a back electrode layer and an absorber layer. Back reflector reflects sunlight photons back into the absorber layer to generate additional electrical energy. The device is a photovoltaic device comprising a substrate, a back electrode layer, a back reflector, an absorber layer, a buffer layer, and a front contact layer. The back reflector is formed as a plurality of parallel lines. | 03-05-2015 |
20150079717 | APPARATUS AND METHODS FOR FABRICATING SOLAR CELLS - A method for fabricating a solar cell generally comprises delivering a solar cell substructure to a chamber. Electromagnetic radiation is generated using a wave generating device that is coupled to the chamber such that the wave generating device is positioned proximate to the solar cell substructure. The electromagnetic radiation is applied onto at least a portion of the solar cell substructure to facilitate the diffusion of at least one metal element through at least a portion of the solar cell substructure such that a semiconductor interface is formed between at least two different types of semiconductor materials of the solar cell substructure. | 03-19-2015 |
Patent application number | Description | Published |
20080254642 | METHOD OF FABRICATING GATE DIELECTRIC LAYER - A method for fabricating gate dielectric layer is provided. First, a sacrificial layer is formed on a substrate. Next, fluorine ions are implanted into the substrate. Then, the sacrificial layer is then removed. Finally, a dielectric layer is formed on the substrate. | 10-16-2008 |
20080318405 | METHOD OF FABRICATING GATE STRUCTURE - A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure. | 12-25-2008 |
20120193796 | POLYSILICON LAYER AND METHOD OF FORMING THE SAME - The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved. | 08-02-2012 |
20120264284 | MANUFACTURING METHOD FOR METAL GATE STRUCTURE - A manufacturing method for a metal gate structure includes providing a substrate having a gate trench formed thereon, forming a work function metal layer in the gate trench, and performing an annealing process to the work function metal layer. The annealing process is performed at a temperature between 400° C. and 500° C., and in a bout 20 seconds to about 180 seconds. | 10-18-2012 |
20120306028 | SEMICONDUCTOR PROCESS AND STRUCTURE THEREOF - A semiconductor process is provided, including: a substrate is provided, a buffer layer is formed, and a dielectric layer having a high dielectric constant is formed, wherein the methods of forming the buffer layer include: (1) an oxidation process is performed; and a baking process is performed; Alternatively, (2) an oxidation process is performed; a thermal nitridation process is performed; and a plasma nitridation process is performed; Or, (3) a decoupled plasma oxidation process is performed. Furthermore, a semiconductor structure fabricated by the last process is also provided. | 12-06-2012 |
20120309171 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer; removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and a disposable spacer on the sidewall of the gate structure; and filling the recesses with a material comprising silicon atoms for forming a faceted material layer. | 12-06-2012 |
20120329261 | MANUFACTURING METHOD FOR METAL GATE - A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function. | 12-27-2012 |
20130001707 | FABRICATING METHOD OF MOS TRANSISTOR, FIN FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF - A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided. | 01-03-2013 |
20130012012 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate having an oxide layer thereon is provided. A high temperature process higher than 1000° C. is performed to form a melting layer between the substrate and the oxide layer. A removing process is performed to remove the oxide layer and the melting layer. | 01-10-2013 |
20130072028 | PROCESS FOR FABRICATING SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING METAL OXIDE SEMICONDUCTOR DEVICE - A process for fabricating a semiconductor device is described. A silicon oxide layer is formed. A nitridation process including at least two steps is performed to nitridate the silicon oxide layer into a silicon oxynitride (SiON) layer. The nitridation process comprises a first nitridation step and a second nitridation step in sequence, wherein the first nitridation step and the second nitridation step are different in the setting of at least one parameter. | 03-21-2013 |
20130072030 | METHOD FOR PROCESSING HIGH-K DIELECTRIC LAYER - A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature. | 03-21-2013 |
20130078818 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and an oxide layer is formed on the substrate without the fin-shaped structure forming thereon. A thermal treatment process is performed to form a melting layer on at least a part of the sidewall of the fin-shaped structure. | 03-28-2013 |
20130093064 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor process includes the following steps. A substrate is provided. A dielectric layer having a high dielectric constant is formed on the substrate, wherein the steps of forming the dielectric layer include: (a) a metallic oxide layer is formed; (b) an annealing process is performed to the metallic oxide layer; and the steps (a) and (b) are performed repeatedly. Otherwise, the present invention further provides a semiconductor structure formed by said semiconductor process. | 04-18-2013 |
20130171837 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate having a recess is provided. A decoupled plasma nitridation process is performed to nitride the surface of the recess for forming a nitrogen containing liner on the surface of the recess. A nitrogen containing annealing process is then performed on the nitrogen containing liner. | 07-04-2013 |
20140159211 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a dielectric layer located on a substrate, wherein the dielectric layer includes nitrogen atoms, and the concentration of the nitrogen atoms in the dielectric layer is lower than 5% at a location wherein the distance between this location in the dielectric layer to the substrate is less than 20% of the thickness of the dielectric layer. Moreover, the present invention provides a semiconductor process including the following steps: a dielectric layer is formed on a substrate. Two annealing processes are performed in-situly on the dielectric layer, wherein the two annealing processes have different imported gases and different annealing temperatures. | 06-12-2014 |
20150021776 | POLYSILICON LAYER - A polysilicon layer including an amorphous polysilicon layer and a crystallized polysilicon layer is provided. The crystallized polysilicon layer is disposed on the amorphous polysilicon layer. Besides, the amorphous polysilicon layer has a first grain size, the crystallized polysilicon layer has a second grain size, and the first grain size is smaller than the second grain size. The amorphous polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the crystallized polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved. | 01-22-2015 |