Yoon, Icheon-Si
Ahn Sook Yoon, Icheon-Si KR
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20140042554 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is formed by depositing a nitride material having a lower etch rate than an oxide material over or between buried gates when forming a metal contact at an end portion of a cell region, to prevent a lower substrate from being etched during an etching process forming a metal contact hole. The semiconductor device includes at least one buried gate formed in a device isolation film of a semiconductor substrate, an etch stop film formed over and between the buried gates, and a metal contact formed perpendicular to the buried gate in the etch stop film. | 02-13-2014 |
Bohan Yoon, Icheon-Si KR
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20080242053 | INTEGRATED CIRCUIT SYSTEM WITH A DEBRIS TRAPPING SYSTEM - An integrated circuit system including: providing an integrated circuit wafer having an integrated circuit side and a backside; mounting a protective adhesive on the integrated circuit side of the integrated circuit wafer; removing material from the backside of the integrated circuit wafer; and dicing the integrated circuit wafer through the protective adhesive to form an integrated circuit die. | 10-02-2008 |
20090243070 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORT STRUCTURE UNDER WIRE-IN-FILM ADHESIVE - An integrated circuit package in package system including: providing a substrate; mounting a wire bonded die with an active side over the substrate; connecting the active side to the substrate with bond wires; mounting a structure over the wire bonded die having a wire-in-film adhesive between the structure and the wire bonded die and overhangs at ends of the structure between the wire-in-film adhesive and the substrate; mounting support structures at the overhangs between the wire-in-film adhesive and the substrate; and encapsulating the wire bonded die and the structure with an encapsulation. | 10-01-2009 |
Eui Sang Yoon, Icheon-Si KR
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20140156882 | MEMORY DEVICE, OPERATING METHOD THEREOF, AND DATA STORAGE DEVICE INCLUDING THE SAME - A memory device includes a data read/write block configured to store data in memory cells and read data from the memory cells; an input/output buffer block configured to buffer input data inputted through data pads and control signals inputted through control signal pads, and provide buffered input data and control signals to the data read/write block, and buffer read data read out through the data read/write block, and output buffered read data to an external device through the data pads, and a control logic configured to activate or deactivate the input/output buffer block based on an address which is inputted from the external device. | 06-05-2014 |
Hyo Gun Yoon, Icheon-Si KR
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20090122461 | CAPACITOR FOR A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a capacitor for a semiconductor device, comprising: a lower electrode formed over a predetermined lower structure on a semiconductor substrate; an aluminum oxynitride film formed over the lower electrode and having a low leakage current characteristic; a yttrium oxynitride film formed over the aluminum oxynitride film and having a higher dielectric constant than the aluminum oxynitride film; and an upper electrode formed over the yttrium oxynitride film, and a manufacturing method thereof. | 05-14-2009 |
Hyo Seob Yoon, Icheon-Si KR
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20090122461 | CAPACITOR FOR A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a capacitor for a semiconductor device, comprising: a lower electrode formed over a predetermined lower structure on a semiconductor substrate; an aluminum oxynitride film formed over the lower electrode and having a low leakage current characteristic; a yttrium oxynitride film formed over the aluminum oxynitride film and having a higher dielectric constant than the aluminum oxynitride film; and an upper electrode formed over the yttrium oxynitride film, and a manufacturing method thereof. | 05-14-2009 |
Hyuck-Soo Yoon, Icheon-Si KR
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20100165763 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory banks each having a plurality of memory cell arrays, a plurality of sense amplification units corresponding to the memory banks, configured to sense data corresponding to a selected memory cell to amplify the sensed data, and a common delay unit configured to delay a plurality of respective bank active signals activated in correspondence with the memory banks by a predetermined time to generate an operation control signal for controlling the sense amplification units. | 07-01-2010 |
20120155204 | SEMICONDUCTOR MEMORY APPARATUS HAVING A PRE-DISCHARGING FUNCTION, SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME, AND METHOD FOR DRIVING THE SAME - A semiconductor memory apparatus includes a bit line coupled to a plurality of memory cells, a discharge controller configured to generate a bit line discharge signal to pre-discharge the bit line before the memory cells are activated, and a bit line discharge block coupled to the bit line and configured to discharge the bit line in response to the bit line discharge signal. | 06-21-2012 |
Hyun Su Yoon, Icheon-Si KR
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20130279271 | PIPE REGISTER CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME - A pipe register circuit includes an address storage section configured to temporarily and sequentially store address signals input from an external in correspondence with a read command signal input together with the address signals, and an address output control section configured to generate an address output control signal for allowing the address signals stored in the address storage section to be output in correspondence with CAS latency, and output the address output control signal to the address storage section. | 10-24-2013 |
Jin-Wook Yoon, Icheon-Si KR
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20100135868 | SOFT X-RAY PHOTOIONIZATION CHARGER - A soft X-ray photoionization charger includes a housing having a chamber and an aperture formed on one side surface of the housing and joined to the chamber. The chamber forms a flow path of an aerosol containing particles. A photoionizer is fixed to the aperture of the housing. The photoionizer includes a head for irradiating soft X-rays into the chamber to neutralize the particles. A transparent window is mounted between the chamber and the head. The transparent window is made of a material permitting passage of the soft X-rays. The photoionization charger further includes a soft support ring arranged around the transparent window and tightly fitted to the aperture. | 06-03-2010 |
Jung Hyuk Yoon, Icheon-Si KR
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20110128805 | TEST CIRCUIT, NONVOLATILE SEMICONDUCTOR MEMORY APPRATUS USING THE SAME, AND TEST METHOD - A test circuit of a nonvolatile semiconductor memory apparatus includes a first switching unit, a second switching unit, and a third switching unit. The first switching unit is configured to selectively interrupt application of a pumping voltage for a sense amplifier to a sense amplifier input node. The second switching unit is configured to selectively decouple the sense amplifier input node and a sub input/output node. The sub input/output node is coupled with a data storage region. The third switching unit is configured to selectively connect a voltage applying pad and the sense amplifier input node. | 06-02-2011 |
20120195113 | PHASE CHANGE RANDOM ACCESS MEMORY APPARATUS - A phase change random access memory (PCRAM) apparatus includes: a memory cell array including a plurality of phase change memory cells; and a firing control unit configured to provide a firing voltage for firing the plurality of phase change memory cells to a global bit line in response to an enable signal based on a test mode signal. | 08-02-2012 |
20140063988 | SEMICONDUCTOR MEMORY DEVICE - Disclosed is a semiconductor memory device. A semiconductor memory device in accordance with an embodiment of the present invention includes a write driver configured to provide voltage necessary for a write operation when the write operation is performed, a switch block connected to the write driver and configured to control the path of the write voltage, and a cell block connected to the switch block, wherein a constant voltage is supplied to a node leading to a cell selection path within the cell block using the write driver as a voltage source. | 03-06-2014 |
20140063989 | SEMICONDUCTOR MEMORY DEVICE INCLUDING WRITE DRIVER AND METHOD OF CONTROLLING THE SAME - Disclosed is a method of controlling a semiconductor memory device including a write driver. A method of controlling a phase change memory device includes turning on switches connected to a global bit line and a local bit line, respectively, enabling a write driver connected to the switches, enabling a word line, and enabling a memory cell to be accessed by the word line, wherein control is performed so that electric charges supplied from the write driver through the switches are charged when the write driver is enabled. | 03-06-2014 |
20150058566 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages. | 02-26-2015 |
Sang Sic Yoon, Icheon-Si KR
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20120120744 | METHOD FOR SYNCHRONIZING SIGNALS AND PROCESSING DATA - A method for synchronizing signals includes the steps of receiving a preamble of a data strobe signal in response to a write preamble command, and synchronizing the data strobe signal with a clock signal through the preamble of the data strobe signal. | 05-17-2012 |
20130215692 | SEMICONDUCTOR MEMORY, MEMORY SYSTEM, AND METHOD OF CONTROLLING THE SAME - Various embodiments of a semiconductor system, semiconductor memory, and a method of controlling the same are disclosed. In one exemplary embodiment, the semiconductor memory may include a first circuit area configured to perform an operation corresponding to a general operation command and a second circuit area configured to provide the general operation command to the first circuit area. The second circuit area may be configured to determine whether the semiconductor memory selected to perform the operation based on unique identification information and target identification information allocated to the semiconductor memory. | 08-22-2013 |
20130227230 | SEMICONDUCTOR MEMORY, MEMORY SYSTEM, AND METHOD OF CONTROLLING THE SAME - Various embodiments of a semiconductor system, a semiconductor memory, and a method of controlling the same are disclosed. In one exemplary embodiment, the semiconductor memory may include a first circuit area configured to perform an operation corresponding to a general operation command and a second circuit area configured to provide the general operation command to the first circuit area. The second circuit area may be configured to determine whether the semiconductor memory is selected to perform the operation based on unique identification information and target identification information allocated to the semiconductor memory. | 08-29-2013 |
20130227240 | SEMICONDUCTOR MEMORY, MEMORY SYSTEM, AND METHOD OF CONTROLLING THE SAME - Various embodiments of a semiconductor system, semiconductor memory, and a method of controlling the same are disclosed. In one exemplary embodiment, the semiconductor memory may include a first circuit area configured to perform an operation corresponding to a general operation command and a second circuit area configured to provide the general operation command to the first circuit area. The second circuit area may be configured to determine whether the semiconductor memory selected to perform the operation based on unique identification information and target identification information allocated to the semiconductor memory. | 08-29-2013 |
Seok-Young Yoon, Icheon-Si KR
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20100055865 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a hardmask pattern over a substrate, forming a line type first photoresist pattern over the hardmask pattern, etching the hardmask pattern using the first photoresist pattern, removing the first photoresist pattern, forming a line type second photoresist pattern that cross the first photoresist pattern over the hardmask pattern, etching the hardmask pattern using the second photoresist pattern as an etch barrier, removing the second photoresist pattern, forming a trench by etching the substrate using the etched hardmask pattern as an etch barrier, and forming a device isolation region by filling the trench with an insulation layer. | 03-04-2010 |
Sung-Joon Yoon, Icheon-Si KR
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20140247648 | ELECTRONIC DEVICE - An electronic device includes a first electrode, a second electrode spaced apart from the first electrode, a resistance variable element interposed between the first electrode and the second electrode, and a conductor arranged at least one of a first side and a second side of the resistance variable element to apply an electric field to the resistance variable element while being spaced apart from the resistance variable element, the first side facing the second side. | 09-04-2014 |
20140269039 | ELECTRONIC DEVICE AND VARIABLE RESISTANCE ELEMENT - A variable resistance element includes: first and second magnetic layers having a lanthanide series element alloyed in a nickel-iron compound; and a tunnel barrier layer interposed between the first and second magnetic layers. | 09-18-2014 |
Sung Jun Yoon, Icheon-Si KR
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20120146230 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a carrier having a contact pad; forming a first resist layer, having a first resist opening, over the carrier and the contact pad, the first resist opening partially exposing the first contact pad; forming a second resist layer, having a second resist opening over the first resist opening, the second resist opening partially exposing the first resist layer; mounting an integrated circuit over the carrier; and forming an internal interconnect between the integrated circuit and the carrier, the internal interconnect filling the second resist opening with no space between the second resist layer in the second resist opening. | 06-14-2012 |
20130320566 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a stack substrate over the base substrate with an inter-substrate connector directly on the stack substrate and the base substrate, the inter-substrate connector having an inter-substrate connector pitch; mounting an integrated circuit over the stack substrate, the integrated circuit having an internal connector directly on the stack substrate; and attaching an external connector directly on the base substrate, the external connector having an external connector pitch greater than the inter-substrate connector pitch. | 12-05-2013 |
Yang-Han Yoon, Icheon-Si KR
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20100151668 | METHOD OF FABRICATING INSULATION LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method for fabricating an insulation layer includes forming an insulation layer over a nitride layer using a silicon source and a phosphorus source, wherein the insulation layer includes a first insulation layer contacting the nitride layer and a second insulation layer formed on the first insulation layer, wherein the first insulation layer is formed using a higher flow rate of the silicon source and a lower flow rate of the phosphorus source than used with the second insulation layer. | 06-17-2010 |
Young Hee Yoon, Icheon-Si KR
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20140048907 | POWER TSVS OF SEMICONDUCTOR DEVICE - A semiconductor device including power TSVs for stably supplying a power source is described. A semiconductor device includes a chip power pad placed in a first region of a chip, power through silicon vias (TSVs) connected to the chip power pad and placed in the second region of each of the chips, and metal lines configured to couple the chip power pad and the power TSVs. | 02-20-2014 |
Young Jun Yoon, Icheon-Si KR
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20140176168 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a receiver configured to receive a plurality of input signals through a plurality of pads; a signal processing unit configured to process the input signals received by the receiver and output the processed signals as a plurality of internal signals; a MUX unit configured to select the plurality of internal signals as a plurality of MUX output or select test input data and a plurality of latch signals as the plurality of MUX output signals in response to an input/output select signal; a latch unit configured to output the plurality of MUX output signals as the plurality of latch signals and a final output signal in response to a latch clock signal; and a clock selection unit configured to output any one of a test clock signal and an internal clock signal as the latch clock signal in response to a test mode signal. | 06-26-2014 |
20140347938 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes an input buffer configured to buffer data inputted through a data input/output pad; a data input control unit configured to transfer an output of the input buffer to a data input/output line in response to a write clock; a test loop control unit configured to output one of a signal of the data input/output line and test latch data in response to a test mode signal; a data output control unit configured to output an output of the test loop control unit in response to a read clock; an output inversion select unit configured to output an output signal of the data output control unit by inverting or non-inverting it; and an output buffer configured to buffer an output signal of the output inversion select unit and output a resultant signal to a node which is coupled with the data input/output pad and input buffer. | 11-27-2014 |
20150036438 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes an input buffer configured to buffer and output data inputted from a data input/output pad; a data input control unit configured to transfer data outputted from the input buffer; a data output control unit configured to transfer inputted data to an output buffer; the output buffer configured to buffer data outputted from the data output control unit, and output the buffered data to the data input/output pad; a test data input/output unit configured to latch test inputted data inputted and output test latch data or latch an output of the input buffer and output the test latch data; and a test loop control unit configured to transfer data or the test latch data to the data output control unit. | 02-05-2015 |