Patent application number | Description | Published |
20080242010 | At least penta-sided-channel type of finfet transistor - An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator. | 10-02-2008 |
20090020845 | SHALLOW TRENCH ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES INCLUDING DOPED OXIDE FILM LINERS AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate having a trench, a sidewall liner that covers inner walls of the trench, a doped oxide film liner on the sidewall liner in the trench, and a gap-fill insulating film that buries the trench on the doped oxide film liner. In order to form the doped oxide film liner, an oxide film liner is doped with a dopant under a plasma atmosphere. Related methods are also disclosed. | 01-22-2009 |
20100233864 | Methods of fabricating a semiconductor device - Methods of fabricating a semiconductor device are provided, the methods include forming a gate stack on a substrate, forming an insulation layer on the substrate to cover the gate stack, forming a spacer at both side walls of the gate stack by etching the insulation layer, and ion implanting impurities in the spacer or the insulation layer. | 09-16-2010 |
20120309145 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Methods of manufacturing semiconductor devices include providing a substrate including a NMOS region and a PMOS region, implanting fluorine ions into an upper surface of the substrate, forming a first gate electrode of the NMOS region and a second gate electrode of the PMOS region on the substrate, forming a source region and a drain region in portions of the substrate, which are adjacent to two lateral surfaces of the first gate electrode and the second gate electrode, respectively, and performing a high-pressure heat-treatment process on an upper surface of the substrate by using non-oxidizing gas. | 12-06-2012 |
Patent application number | Description | Published |
20090085125 | MOS transistor and CMOS transistor having strained channel epi layer and methods of fabricating the transistors - Provided are a metal oxide semiconductor (MOS) transistor and a complementary MOS (CMOS) transistor each having a strained channel epi layer, and methods of fabricating the transistors. The MOS transistor may include at least one active region defined by an isolation structure formed in a substrate. At least one channel trench may be formed in a part of the at least one active region. At least one strained channel epi layer may be in the at least one channel trench. At least one gate electrode may be aligned on the at least one strained channel epi layer. Sources/drains may be arranged in the at least one active region along both sides of the at least one strained channel epi layer. | 04-02-2009 |
20120070975 | Methods of Forming Gate Structure and Methods of Manufacturing Semiconductor Device Including the Same - A method of forming agate structure having an improved electric characteristic is disclosed. A gate insulating layer is formed on a substrate and a metal layer is formed on the gate insulating layer. Then, an amorphous silicon layer is formed on the metal layer by a physical vapor deposition (PVD) process. An impurity doped polysilicon layer is formed on the amorphous silicon layer. Formation of an oxide layer at an interface between the amorphous silicon layer and the metal layer may be prevented. | 03-22-2012 |
20120083111 | Methods of Manufacturing a Semiconductor Device - There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern. | 04-05-2012 |
20120309144 | METHODS OF FORMING MOSFET DEVICES USING NITROGEN-INJECTED OXIDE LAYERS TO FORM GATE INSULATING LAYERS HAVING DIFFERENT THICKNESSES - In some embodiments of the inventive subject matter, methods include forming an oxide layer on a semiconductor substrate, injecting nitrogen into the oxide layer to form a nitrogen injection layer and to change the oxide layer to an oxynitride layer, removing a part of the oxynitride layer to leave a portion of the oxynitride layer in a first area and expose the nitrogen injection layer in a second area and forming an insulating layer comprising a portion on the portion of the oxynitride layer in the first area and a portion on the nitrogen injection layer in the second area. The insulating layer may have a higher dielectric constant than the oxide layer. | 12-06-2012 |