Patent application number | Description | Published |
20080230830 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer. | 09-25-2008 |
20090108332 | Non-volatile memory device with charge trapping layer and method for fabricating the same - Disclosed herein are a non-volatile memory device and a method of manufacturing the same. The non-volatile memory device includes a substrate, a tunneling layer disposed on the substrate, a charge trapping layer disposed on the tunneling layer, a blocking layer disposed on the charge trapping layer, and a control gate electrode disposed on the blocking layer. The blocking layer in contact with the charge trapping layer includes an aluminum nitride layer. | 04-30-2009 |
20090108334 | Charge Trap Device and Method for Fabricating the Same - A charge trapping device includes a plurality of isolation layers, a plurality of charge trapping layers, a blocking layer, and a control gate electrode. The isolation layers define active regions, and the isolation layers and active regions extend as respective stripes along a first direction on a semiconductor substrate. The charge trapping layers are disposed on the active regions in island forms where the charge trapping layers are separated from each other in the first direction and disposed on the respective active regions between the isolation layers in a second direction perpendicular to the first direction. The blocking layer is disposed on the isolation layers and the charge trapping layers. The control gate electrode is disposed on the charge trapping layer. | 04-30-2009 |
20090114977 | NONVOLATILE MEMORY DEVICE HAVING CHARGE TRAPPING LAYER AND METHOD FOR FABRICATING THE SAME - Disclosed herein is a nonvolatile memory device having a charge trapping layer and a method of making the same. The nonvolatile memory device includes a substrate, a tunneling layer disposed on the substrate, a charge trapping layer disposed on the tunneling layer, a first blocking layer disposed on the charge trapping layer, a second blocking layer disposed on the first blocking layer, and a control gate electrode disposed on the second blocking layer. A first band gap between the first blocking layer and the charge trapping layer is larger than a second band gap between the second blocking layer and the charge trapping layer. | 05-07-2009 |
20090163014 | Method for Fabricating Non-Volatile Memory Device with Charge Trapping Layer - A method for fabricating a non-volatile memory device with a charge trapping layer wherein a tunneling layer, a charge trapping layer, a blocking layer, and a control gate electrode are formed on a semiconductor substrate. A temperature of the control gate electrode is increased by applying a magnetic field to the control gate electrode. The blocking layer is densified by allowing the increased temperature to be transferred to the blocking layer contacting the control gate electrode. | 06-25-2009 |
20110204430 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer. | 08-25-2011 |
20130069152 | 3D STRUCTURED MEMORY DEVICES AND METHODS FOR MANUFACTURING THEREOF - A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region. | 03-21-2013 |
20130193503 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity. | 08-01-2013 |
20130207182 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes vertical channel layers, a pipe channel layer coupling bottoms of the vertical channel layers, a pipe gate contacting a bottom surface and side surfaces of the pipe channel layer, and a dummy pipe gate formed of a non-conductive material and contacting a top surface of the pipe channel layer. | 08-15-2013 |
20130320424 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer. | 12-05-2013 |
20140015057 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a cell structure; n first pad structures formed on one side of the cell structure and each configured to have a step form in which 2n layers form one stage; and n second pad structures formed on the other side of the cell structure each configured to have a step form in which 2n layers form one stage, wherein n is a natural number of 1 or higher, and the first pad structures and the second pad structures have asymmetrical step forms having different heights. | 01-16-2014 |
20140061750 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a first substrate on which a cell region is defined. In the cell region, memory cells are stacked. A second substrate is located above the first substrate, and a peripheral region is defined on the second substrate. One or more conductive lines are located in the peripheral region. The one or more lines extend through the second substrate and couple to the cell region. | 03-06-2014 |
20140061776 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a trench formed in a substrate, a first stacked structure formed in the trench and including a plurality of first material layers and a plurality of second material layers stacked alternately on top of each other, and a transistor located on the substrate at a height corresponding to a top surface of the first stacked structure. | 03-06-2014 |
20140103417 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a pipe gate, word lines stacked on the pipe gate, first channel layers configured to pass through the word lines, and a second channel layer formed in the pipe gate to connect the first channel layers and having a higher impurity concentration than the first channel layers. | 04-17-2014 |
20140131783 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block. | 05-15-2014 |
20140138765 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first conductive layer, second conductive layers stacked on the first conductive layer; a second slit passing through the first and second conductive layers and connected with one side of the first slit, and a third slit passing through the first and second conductive layers and connected with the other side of the first slit. | 05-22-2014 |
20140191389 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first insulating layers formed alternately with each other in the contact region of the substrate, wherein an end of the pad structure is patterned stepwise, portions of the first conductive layers exposed at the end of the pad structure are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of first conductive layers. | 07-10-2014 |
20140291848 | SEMICONDUCTOR DEVICE - A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first regions including non-conductive material layers and a plurality of second regions including conductive material layers, wherein the first regions and the second regions are alternately arranged. | 10-02-2014 |
20140370675 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of conductive layers and a plurality of insulating layers formed alternately with each other, at least one channel layer passing through the plurality of conductive layers and the plurality of insulating layers, and at least one first charge blocking layer surrounding the at least one channel layer, wherein a plurality of first regions, interposed between the at least one channel layer and the plurality of conductive layers, and a plurality of second regions, interposed between the at least one channel layer and the plurality of insulating layers, are alternately defined on the at least one first charge blocking layer, and each of the plurality of first regions has a greater thickness than each of the plurality of second regions. | 12-18-2014 |
Patent application number | Description | Published |
20100258852 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed. | 10-14-2010 |
20100317166 | METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE - A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer. | 12-16-2010 |
20110058418 | 3D NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A 3D nonvolatile memory device includes: a plurality of channel structures including a plurality of channel layers and interlayer dielectric layers, which are alternately stacked, and extended in a first direction; a plurality of word lines extended in a second direction at least substantially perpendicular to the first direction; a plurality of row select lines connected to the plurality of channel layers, respectively, and extended in the second direction; and a plurality of column select lines connected to the plurality of channel structures, respectively, and extended in the first direction. | 03-10-2011 |
20110266611 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a plurality of interlayer dielectric layers and conductive layers for gate electrodes alternately stacked over a substrate, a channel trench passing through the interlayer dielectric layers and the conductive layers and exposing the substrate, a charge blocking layer and a charge trap or charge storage layer formed on sidewalls of the trench, a coupling prevention layer formed at the surface of the charge trap or charge storage layer, and a tunnel insulation layer formed over the coupling prevention layer. | 11-03-2011 |
20110291176 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a pair of columnar cell channels vertically extending from a substrate, a doped pipe channel arranged to couple lower ends of the pair of columnar cell channels, insulation layers over the substrate in which the doped pipe channel is buried, memory layers arranged to surround side surfaces of the columnar cell channels, and control gate electrodes arranged to surround the memory layers. | 12-01-2011 |
20110291177 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a pipe insulation layer having a pipe channel hole, a pipe gate disposed over the pipe insulation layer, a pair of cell strings each having a columnar cell channel, and a pipe channel coupling the columnar cell channels and surrounding inner sidewalls and a bottom of the pipe channel hole. | 12-01-2011 |
20120021574 | METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE - A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer. | 01-26-2012 |
20120092926 | THREE DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A three dimensional non-volatile memory structure according to an aspect of this disclosure includes a plurality of interlayer dielectric layers and a plurality of control gates alternately stacked over a substrate, a channel formed to penetrate the plurality of interlayer dielectric layers and the plurality of control gates, a tunnel insulating layer formed to surround the channel, a plurality of floating gates disposed between the plurality of interlayer dielectric layers and the tunnel insulating layer, wherein the plurality of floating gates each have a thickness greater than a corresponding one of the interlayer dielectric layers, and a charge blocking layer disposed between the plurality of control gates and the plurality of floating gates. | 04-19-2012 |
20120126308 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device includes a plurality of memory cells stacked along a channel protruded from a substrate, a first select transistor connected to one end of the plurality of memory cells, a first interlayer dielectric layer for being coupled between a source line and the first select transistor, and a second interlayer dielectric layer disposed between the first select transistor and the one end of the plurality of memory cells, and configured to include a first recess region. | 05-24-2012 |
20120146122 | 3-D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A three-dimensional (3-D) non-volatile memory device includes a plurality of word line structures extended in parallel and including a plurality of interlayer dielectric layers and a plurality of word lines that are alternately stacked over a substrate, a plurality of channels protruding from the substrate configured to penetrate the plurality of interlayer dielectric layers and the plurality of word lines, and an air gap formed between the plurality of word line structures. | 06-14-2012 |
20120146127 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a pipe gate having a pipe channel hole; a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked over the pipe gate; a pair of columnar cell channels passing through the interlayer insulation layers and the gate electrodes and coupling a pipe channel formed in the pile channel hole; a first blocking layer and a charge trapping and charge storage layer formed on sidewalk of the columnar cell channels; and a second blocking layer formed between the first blocking layer and the plurality of gate electrodes. | 06-14-2012 |
20120168850 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a channel protruding in a vertical direction from a substrate, a plurality of interlayer dielectric layers and gate electrode layers which are alternately stacked over the substrate along the channel, and a memory layer formed between the channel and a stacked structure of the interlayer dielectric layers and gate electrode layers. Two or more gate electrode layers of the plurality of gate electrode layers are coupled to an interconnection line to form a selection transistor. | 07-05-2012 |
20120170368 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a nonvolatile memory device and a method for fabricating the same, which can secure the structural stability of a three-dimensional nonvolatile memory device. The nonvolatile memory device includes one or more columnar channel plugs, a plurality of word lines and a plurality of dielectric layers stacked alternately to surround the columnar channel plug, a memory layer disposed between the word line and the columnar channel plug, a plurality of word line connection portions, each of the word line connection portions connecting ends of word lines of a common layer from among the plurality of word lines, and a plurality of word line extension portions extending from the word line connection portions. | 07-05-2012 |
20120211822 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed. | 08-23-2012 |
20120289020 | METHOD FOR FABRICATING VARIABLE RESISTANCE MEMORY DEVICE - A method for fabricating a variable resistance memory device includes forming a semiconductor pattern doped with impurities, forming a resistor over the semiconductor pattern, and forming a diode by performing microwave annealing to activate the impurities in the semiconductor pattern. | 11-15-2012 |
20120299117 | 3-DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A 3-dimensional (3-D) non-volatile memory device includes a first channel protruding from a substrate, a selection gate formed on sidewalls of the first channel and in an L shape, and a gate insulating layer interposed between the first channel and the selection gate and surrounding the first channel. A method of manufacturing a 3-D non-volatile memory device includes forming first channels protruding from a substrate, forming a first gate insulating layer surrounding the first channels, and forming first selection gates having an L shape on sidewalls of the first channels on which the first gate insulating layers are formed. | 11-29-2012 |
20130009239 | 3-D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A 3-D non-volatile memory device includes a pipe gate having a first trench formed therein, word lines stacked in multiple layers over the pipe gate, second trenches coupled to the first trench and formed to penetrate the word lines, a first channel layer formed within the first trench, and second channel layers formed within the second trenches, respectively, and coupled to the first channel layer, wherein the width or depth of the first trench is smaller than the diameter of each of the second trenches. | 01-10-2013 |
20130087846 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes word lines and interlayer insulating layers alternately stacked, a channel layer penetrating the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding the channel layer, and first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities. | 04-11-2013 |
20130105883 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME | 05-02-2013 |
20130130454 | METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE - A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer. | 05-23-2013 |
20130137228 | METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE - A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer. | 05-30-2013 |
20130153978 | 3D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer, and at least one second channel layer including a second pipe channel layer formed in the pipe gate and positioned over the first pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer. | 06-20-2013 |
20130161731 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A three-dimensional (3D) semiconductor device includes first interlayer dielectric layers and word lines that are alternately stacked on a substrate; select lines formed on the first interlayer dielectric layers and the word lines; etch stop patterns formed on the select lines to contact the select lines; channel holes formed to pass through the select lines, the first interlayer dielectric layers, and the word lines; channel layers formed on surfaces of the channel holes; insulating layers formed in the channel holes, the insulating layers having an upper surface that is lower than upper surfaces of the etch stop patterns; impurity-doped layers formed in channel holes on upper surface of the insulating layers; and a second interlayer dielectric layer formed over the etch stop patterns and the impurity-doped layers. | 06-27-2013 |
20130207178 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer. | 08-15-2013 |
20130240994 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, and a gate line, located over the substrate, which includes a first conductive layer and one or more second conductive pattern layers located in the first conductive layer. The second conductive pattern layer comprises a metal layer to thus reduce resistance of a gate line. | 09-19-2013 |
20140138687 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes first conductive layers and first interlayer insulating layers stacked alternately with each other, at least one second conductive layer and at least one second interlayer insulating layer formed on the first conductive layers and the first interlayer insulating layers and stacked alternately with each other, a first semiconductor layer passing through the first conductive layers and the first interlayer insulating layers and including polysilicon, and a second semiconductor layer coupled to the first semiconductor layer and passing through the at least one second conductive layer the at least one second interlayer insulating layer, wherein the second semiconductor layer includes silicon germanium. | 05-22-2014 |
20140242765 | 3-DIMENSIONAL NON-VOLATILE MEMORY DEVICE INCLUDING A SELECTION GATE HAVING AN L SHAPE - A 3-dimensional (3-D) non-volatile memory device includes a first channel protruding from a substrate, a selection gate formed on sidewalls of the first channel and in an L shape, and a gate insulating layer interposed between the first channel and the selection gate and surrounding the first channel. A method of manufacturing a 3-D non-volatile memory device includes forming first channels protruding from a substrate, forming a first gate insulating layer surrounding the first channels, and forming first selection gates having an L shape on sidewalls of the first channels on which the first gate insulating layers are formed. | 08-28-2014 |
20140346682 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of first conductive layers stacked on top of one another, a plurality of first slits passing through the first conductive layers, and a plurality of second slits passing through the first conductive layers and crossing end portions of the first slits to form cross-shaped edges. | 11-27-2014 |
20150017771 | 3D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer, and at least one second channel layer including a second pipe channel layer formed in the pipe gate and positioned over the first pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer. | 01-15-2015 |
20150050790 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes word lines and interlayer insulating layers alternately stacked, a channel layer penetrating the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding the channel layer, and first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities. | 02-19-2015 |
20150056769 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, and a gate line, located over the substrate, which includes a first conductive layer and one or more second conductive pattern layers located in the first conductive layer. The second conductive pattern layer comprises a metal layer to thus reduce resistance of a gate line. | 02-26-2015 |
20150093866 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a pipe insulation layer having a pipe channel hole, a pipe gate disposed over the pipe insulation layer, a pair of cell strings each having a columnar cell channel, and a pipe channel coupling the columnar cell channels and surrounding inner sidewalls and a bottom of the pipe channel hole. | 04-02-2015 |
20150111352 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer. | 04-23-2015 |
Patent application number | Description | Published |
20110310918 | LASER MODULE - Provided is a laser module. The laser module comprises: a substrate; an gain unit oscillating a laser light on the substrate; an external resonance reflecting unit total-reflecting the laser light at an external of the substrate adjacent to one side of the gain unit; and an inner resonance reflecting unit reflecting the laser light to the external resonance reflecting unit at the substrate between the modulating unit and gain unit and outputting the laser light to the modulating unit. | 12-22-2011 |
20120093178 | WAVELENGTH TUNABLE EXTERNAL CAVITY LASER GENERATING DEVICE - Provided is a wavelength tunable external cavity laser generating device. The wavelength tunable external cavity laser generating devices includes: an optical amplifier, a comb reflector, and an optical signal processor connected in series on a first substrate; and an external wavelength tunable reflector disposed on a second substrate adjacent to the first substrate and connected to the optical amplifier, wherein the comb reflector includes: a waveguide disposed on the first substrate; a first diffraction grating disposed at one end of the waveguide adjacent to the optical amplifier; and a second diffraction grating disposed at the other end of the waveguide adjacent to the optical signal processor, wherein the optical amplifier, the comb reflector, and the optical signal processor constitute a continuous waveguide. | 04-19-2012 |
20120106578 | WAVELENGTH-TUNABLE EXTERNAL CAVITY LASER GENERATING DEVICE - A wavelength-tunable external cavity laser generating device is provided. The wavelength-tunable external cavity laser generating device includes a reflection-type multi-mode interferometer, an optical amplifier disposed between the reflection-type multi-mode interferometer and an external wavelength-tunable reflector to amplify light, and an optical signal processor configured to process light from the reflection-type multi-mode interferometer. The reflection-type multi-mode interferometer includes a multi-mode waveguide, an input waveguide connecting the optical amplifier and one end of the multi-mode waveguide, and an output waveguide configured to connect the optical signal processor and the other end of the multi-mode waveguide. | 05-03-2012 |
20120307857 | SUPERLUMINESCENT DIODE, METHOD OF MANUFACTURING THE SAME, AND WAVELENGTH-TUNABLE EXTERNAL CAVITY LASER INCLUDING THE SAME - Provided are a high-speed superluminescent diode, a method of manufacturing the same, and a wavelength-tunable external cavity laser including the same. The superluminescent diode includes a substrate having an active region and an optical mode size conversion region, waveguides including an ridge waveguide in the active region and a deep ridge waveguide in the optical mode size conversion region connected to the active waveguide, an electrode disposed on the ridge waveguide; planarizing layers disposed on sides of the ridge waveguide and the deep ridge waveguide on the substrate, and a pad electrically connected to the electrode, the pad being disposed on the planarizing layers outside the active waveguide. | 12-06-2012 |
20130163621 | EXTERNAL CAVITY TUNABLE LASER MODULE - Disclosed is an external cavity tunable laser module including a substrate; a mirror surface that is formed on the substrate to reflect a laser incoming from the outside; a transmissive liquid crystal filter that is formed at a rear side of the mirror surface to select and tune a wavelength of the laser reflected through the mirror surface; and a light source chip that is formed at a rear side of the transmissive liquid crystal filter to reflect the laser that passes through the transmissive liquid crystal filter at a specific wavelength interval to form a plurality of channels and tune wavelengths of the channels. | 06-27-2013 |
20130163993 | DIRECTLY-COUPLED WAVELENGTH-TUNABLE EXTERNAL CAVITY LASER - Disclosed is a directly-coupled wavelength-tunable external cavity laser including a gain medium that generates an optical signal by an applied bias current; an optical waveguide structure that is coupled to the gain medium to form a minor surface and causes lasing in the mirror surface when the applied bias current has a threshold or higher; and a radio frequency transmission medium that adds a radio frequency signal to the applied bias current to adjust an operating speed of the optical signal. | 06-27-2013 |
20130243013 | TUNABLE LASER MODULE - The present disclosure relates to a tunable laser module including a light gain area unit for outputting an optical signal; an optical distributor for separating the optical signal output from the light gain area unit; two comb reflection units for reflecting a part of optical signals separated by the optical distributor and allow a part of the optical signals to penetrate; two phase units for changing phases of the optical signals penetrating the two comb reflection units; an optical coupler for combining the optical signals of which the phases are changed by the two phase units; and an optical amplifier for amplifying the optical signal combined by the optical coupler, wherein the light gain area unit oscillates a laser by totally reflecting the optical signals reflected by the two comb reflection units. | 09-19-2013 |
20140064306 | COMPACT EXTERNAL CAVITY TUNABLE LASER APPARATUS - The present disclosure relates to a compact external cavity tunable laser apparatus. The laser apparatus includes a substrate, an external cavity tunable reflecting unit that reflects laser light entering from the outside on the substrate and selects and varies a wavelength of the reflected laser light, an optical fiber that outputs the laser light on the substrate; and an highly integrated light source that integrates the laser light input from the external cavity tunable reflecting unit using inclined input and output waveguides, a curved waveguide, and a straight waveguide to output the integrated laser light to the optical fiber in order to match an optical axis formed with the external cavity tunable reflecting unit with an optical axis formed with an optical fiber. | 03-06-2014 |