Patent application number | Description | Published |
20130166981 | APPARATUS AND SECURITY SYSTEM FOR DATA LOSS PREVENTION, AND OPERATING METHOD OF DATA LOSS PREVENTION APPARATUS - Disclosed are a DLP security system and an operating method thereof. An operating method of a data loss prevention (DLP) apparatus, comprising: converting, into packets, Ethernet signals received from a fail over device that are transmitted and received between an external network and internal network; analyzing the packets to classify the packets into first packets required to be precisely judged and second packets not required to be precisely judged; distributing and allocating a judgment job about the first packet to at least one in-line instance according to a predetermined reference; and allocating the judgment job distributed to the in-line instance in which a fail occurs to the in-line instance which is normally operated when it is verified whether there is an in-line instance which is normally operated in the case where the fail occurs in the at least one in-line instance. | 06-27-2013 |
20130320351 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light emitting device is provided and includes a protective element including a first lower conductivity-type semiconductor layer and a second lower conductivity-type semiconductor layer. First and second lower electrodes are connected to the first lower conductivity-type semiconductor layer and the second lower conductivity-type semiconductor layer, respectively. A light emitting structure includes a first upper conductivity-type semiconductor layer, an active layer, and a second upper conductivity-type semiconductor layer sequentially formed on the protective element. First and second upper electrodes are connected to the first upper conductivity-type semiconductor layer and the second upper conductivity-type semiconductor layer, respectively. | 12-05-2013 |
20140045288 | METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - A method of manufacturing a semiconductor light emitting device includes preparing a light emitting structure including first and second conductivity type semiconductor layers and an active layer interposed therebetween, forming a plurality of seeds on at least one surface of the light emitting structure, and forming a plurality of dome-shaped protrusions by forming optical waveguide groups from the plurality of respective seeds and combining the optical waveguide groups. | 02-13-2014 |
20140070252 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a first conductivity-type semiconductor layer, an active layer and a second conductivity-type semiconductor layer sequentially stacked on a substrate. A first electrode is disposed on a portion of the first conductivity-type semiconductor layer. A current diffusion layer is disposed on the second conductivity-type semiconductor layer and includes an opening exposing a portion of the second conductivity-type semiconductor layer. A second electrode covers a portion of the current diffusion layer and the exposed portion of the second conductivity-type semiconductor layer, wherein the portion of the current diffusion layer is near the opening. | 03-13-2014 |
20140101751 | HARDWARE ENGINE FOR HIGH-CAPACITY PACKET PROCESSING OF NETWORK BASED DATA LOSS PREVENTION APPLIANCE - Provided is a network-based data loss prevention (DLP) system. The network-based DLP system includes a FPGA engine including a pattern matcher and a MCP engine including a session list filter. The a pattern matcher hash-processes a payload of an input packet in units of a certain size, compares a pre-stored pattern and the hash-processed packet, checks a matching rule ID and an upload channel ID corresponding to the pre-stored pattern when there is a match therebetween, adds tagging information to a header of the input packet, and outputs the packet. The session list filter receives the packet with the tagging information added thereto, and performs pre-registered processing on the pre-registered session, or passes the received packet. The processor uploads, forwards, or drops the received packet in correspondence with the matching rule ID. | 04-10-2014 |
20140367720 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor light emitting device and method of manufacturing the semiconductor light emitting device are provided. The semiconductor light emitting device includes a light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer. The device may also includes a first electrode connected to the first conductivity type semiconductor layer, and a second electrode connected to the second conductivity type semiconductor layer and having a pad region and a finger region extended from the pad region in one direction. The second electrode may include a transparent electrode part positioned on the second conductivity type semiconductor layer and including at least one opening therein, at least one reflective part spaced apart from the transparent electrode part within the opening and disposed in the pad region and the finger region, and a bonding part positioned on at least one portion of the reflective part and including a plurality of bonding finger parts spaced apart from each other in the finger region and a bonding pad part disposed in the pad region. | 12-18-2014 |
Patent application number | Description | Published |
20140299362 | STRETCHABLE ELECTRIC DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a stretchable electric circuit and a manufacturing method thereof The method for manufacturing the stretchable electric circuit includes forming a mold substrate, forming a stretchable substrate having a first flat surface and a first corrugated surface outside the first flat surface on the mold substrate, removing the mold substrate, forming a corrugated wire on the first corrugated surface, and forming an electric device connected to the corrugated wire on the first flat surface. | 10-09-2014 |
20150048375 | METHOD OF MANUFACTURING STRETCHABLE SUBSTRATE AND STRETCHABLE SUBSTRATE MANUFACTURED USING THE METHOD - Provided is a method of manufacturing a gradually stretchable substrate. The method includes forming convex regions and concave regions on a top surface of a stretchable substrate by compressing a mold onto the stretchable substrate and forming non-stretchable patterns by filling the concave regions of the stretchable substrate. The stretchable substrate includes a stretchable region defined by the non-stretchable patterns, the non-stretchable patterns have side surfaces in contact with the stretchable region, and the side surfaces of the non-stretchable patterns are formed of protrusions and a non-protrusion between the protrusions repetitively connected to one another. | 02-19-2015 |
20150147854 | METHOD OF FABRICATING ELECTRONIC CIRCUIT - Provided is a method of fabricating an electronic circuit. The method includes preparing a substrate, forming a polymer film on the substrate, patterning the polymer film to form a polymer pattern, and forming an electronic device on the polymer pattern. | 05-28-2015 |
20150159266 | METHOD OF MANUFACTURING FLEXIBLE SUBSTRATE ALLOWING ELECTRONIC DEVICE TO BE MOUNTED THERETO - Provided is a method of manufacturing a flexible substrate allowing an electronic device to be mounted thereto. The method of manufacturing a flexible substrate allowing an electronic device to be mountable thereto, includes preparing a substrate, applying a force to the substrate to stretch the substrate in horizontal direction, performing a surface treatment process on the substrate and forming a first region having a plurality of wavy surfaces, and forming an electrode on the first region. | 06-11-2015 |
20150348800 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate. | 12-03-2015 |
20150349136 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Methods for manufacturing semiconductor devices according to embodiments of the present invention may include providing a sacrificial substrate including a wiring region and a device region, sequentially forming a sacrificial layer and a buffer layer on the sacrificial substrate, forming a thin-film transistor on the buffer layer of the device region, forming a device protection element surrounding the thin-film transistor within the device region, forming a flexible substrate on the buffer layer, and exposing a surface of the buffer layer by separating the sacrificial substrate by removing the sacrificial layer. Since typical semiconductor process technologies may be directly used, the process compatibility may be improved, and semiconductor devices having high resolution and high performance may be manufactured. Furthermore, since the thin-film transistor is protected by the device protection element, the deformation of semiconductor devices under flexibility conditions may be prevented, thereby improving the reliability of the semiconductor devices. | 12-03-2015 |
Patent application number | Description | Published |
20100034031 | Semiconductor memory device - A semiconductor memory device includes a voltage level selection unit configured to output a plurality of voltage level selection signals according to a fuse program in response to a self-refresh command signal and a reference voltage generator configured to receive a reference voltage and output a target reference voltage having a different voltage level depending on a normal mode or a self-refresh mode in response to the voltage level selection signals. | 02-11-2010 |
20100106900 | Semiconductor memory device and method thereof - A semiconductor memory device and method thereof are provided. The example method may be directed to performing a memory operation in a semiconductor memory device, and may include receiving data and a data masking signal corresponding to at least a portion of the received data, the received data scheduled to be written into memory in response to a write command and the data masking signal configured to block the at least a portion of the received data from being written into the memory and configuring timing parameters differently for each of the received data and the data masking signal so as to execute the write command without writing the at least a portion of the received data into the memory. | 04-29-2010 |
20100142291 | Mobile system on chip (SoC) and mobile terminal using the mobile SoC, and method for refreshing a memory in the mobile SoC - A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a predetermined temperature range, the first memory controller controls the first memory so as not to perform a self refresh. When second temperature information received from the temperature sensor indicates that the detected temperature is in the predetermined temperature range, the first memory controller outputs a self refresh command to the first memory. | 06-10-2010 |
20100165773 | SEMICONDUCTOR MEMORY DEVICE FOR SELF REFRESH AND MEMORY SYSTEM HAVING THE SAME - A semiconductor memory device includes a memory core unit including a memory cell array including a plurality of memory cells and a sense amplifier to sense and amplify data of the plurality of memory cells, and a self refresh control unit to apply at least one first core voltage to the memory core unit and to control a self refresh operation to be performed at every first self refresh cycle, in a first self refresh mode, and to apply at least one second core voltage to the memory core unit and to control the self refresh operation to be performed at every second self refresh cycle, in a second self refresh mode. In the semiconductor memory, a level of the at least one first core voltage is higher than that of a corresponding one of the at least one second core voltage, and the first self refresh cycle is shorter than the second self refresh cycle. | 07-01-2010 |
20100172193 | Semiconductor memory device and method of reducing consumption of standby current therein - A semiconductor memory device comprises a memory array including a plurality of bit lines and a plurality of dummy bit lines, a bias application unit configured to supply bias voltages having a plurality of voltage levels to the plurality of dummy bit lines, a standby current measuring unit configured to measure a value of at least one of standby currents between at least one of the plurality of bit lines and at least one of the plurality of dummy bit lines. Each of the standby currents is generated by each of the bias voltages applied by the bias application unit. | 07-08-2010 |
20100246300 | SEMICONDUCTOR MEMORY DEVICES INCLUDING BURN-IN TEST CIRCUITS - A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit is configured to provide first and second precharge voltages to the first and second bitlines, respectively. The first precharge voltage is provided as a positive power supply voltage and the second precharge voltage is provided as a negative stress voltage during a burn-in test operation. Related methods of operation are also discussed. | 09-30-2010 |
20110188334 | FUSE CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse. | 08-04-2011 |
20120063251 | SEMICONDUCTOR DEVICE, METHOD OF ADJUSTING LOAD CAPACITANCE FOR THE SAME, AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to a plurality of control signals. | 03-15-2012 |
20150262620 | MEMORY MODULE AND MEMORY SYSTEM - A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal. | 09-17-2015 |
Patent application number | Description | Published |
20100157132 | DIGITAL IMAGE PROCESSING APPARATUS AND METHOD OF CONTROLLING THE SAME - A digital image processing apparatus and a method of controlling the same. The digital image processing apparatus includes a multi-direction button as a shutter release button which can move an auto focus (AF) region while a first shutter release signal is being applied. The multi-direction shutter release button is operable along the first direction which is an up and down direction, and is operable in the multiple directions which include back, front, right, and left directions. Specifically, the multi-direction shutter release button is operable to apply a first shutter release signal when moved down along the first direction to a first position, to allow for auto focusing operations in accordance with movement in any of the multiple directions, and is operable to apply a second shutter release signal when moved down along the first direction to a second position to control the digital image processing apparatus to operate a shutter to capture an image. | 06-24-2010 |
20100182851 | Refresh control circuit and semiconductor memory device and memory system including the same - A semiconductor memory device includes a refresh control circuit and a memory cell array. The refresh control circuit generates an internal auto refresh control signal based on a chip select signal and an external self refresh control signal. The memory cell array is refreshed in response to the internal auto refresh control signal. Because the semiconductor memory device internally generates the internal auto refresh control signal performing auto refresh operations, the semiconductor memory device may not be required to transmit to external devices for performing the auto refresh operations, and thus pins or pads for transmitting signals may be reduced and operation time may become faster. | 07-22-2010 |
20100182852 | Oscillation Circuit and Semiconductor Memory Device Including the Same - An oscillation circuit includes an internal voltage generator and an oscillator. The internal voltage generator receives an external voltage and generates an internal voltage based on the external voltage. The internal voltage varies in linearly with an operational temperature. The oscillator generates a variable oscillation signal based on the internal voltage. A period of the variable oscillation signal varies in linearly with the operational temperature. | 07-22-2010 |