Patent application number | Description | Published |
20080211786 | DISPLAY DEVICE - A display device, includes: a touch panel which outputs a predetermined enable signal corresponding to an external pressure; a display panel which includes a light detector responding to external light and generating a predetermined electrical signal representing the position of the light; and a panel driver which forms an image corresponding to the electrical signal on the display panel if the enable signal is input. | 09-04-2008 |
20080254779 | System and Method For Decorating Short Message From Origination Point - A method for converting a SMS sent through a mobile communication network into a SMS or MMS in a previously registered format includes the steps of: receiving a SMS from a certain sending subscriber, determining whether the corresponding sending subscriber is subscribed to a SMS converting service, then converting the SMS into a previously registered format in case the sending subscriber is subscribed to the SMS converting service, and then sending the converted message to a designated receiving terminal. | 10-16-2008 |
20090121701 | BANDGAP REFERENCE GENERATING CIRCUIT - A bandgap reference generating circuit includes an operational amplifier configured to generate a bandgap reference voltage; and a gain controller configured to control a gain of the operational amplifier with different values in a normal mode and a low power mode. | 05-14-2009 |
20090128208 | APPARATUS AND METHOD FOR DETECTING DUTY RATIO OF SIGNALS IN SEMICONDUCTOR DEVICE CIRCUIT - Apparatus for detecting duty ratio of signals in semiconductor device circuit includes a circuit for detecting a duty ratio of signals in a semiconductor device includes a comparing unit which compares a duty cycle of first and second input clock signals input differentially and generates a first output signal and a second output signal, a latching unit which stores the first and second output signals and generates a detected signal corresponding to the first and second output signals, and an adjusting unit which receives the first and the second output signals, and transmits the first and the second output signals to the latching unit based on a voltage level difference of the first and second output signals. | 05-21-2009 |
20090146684 | CIRCUIT FOR CONTROLLING DRIVER OF SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF CONTROLLING THE SAME - A circuit for controlling a driver of a semiconductor memory apparatus includes a driving unit having an impedance that is set according to a code value; a driving reinforcing control unit configured to output an adjustment code for a predetermined time; and a driving reinforcing unit configured to output a reinforcing code obtained by adjusting the code value using the adjustment code, wherein the reinforcing code reinforce a driving capability of the driving unit. | 06-11-2009 |
20090168944 | LOW PASS FILTER AND LOCK DETECTOR CIRCUIT - A low pass filter includes a driver unit configured to output a voltage proportional to an input pulse width, a charge/discharge unit configured to charge the output voltage of the driver unit, a comparator unit configured to compare an output voltage of the charge/discharge unit with a reference value to output a square wave signal, and a switching unit configured to switch the charge/discharge unit to an operation state, based on a bandwidth expansion signal. | 07-02-2009 |
20090175116 | CLOCK SYNCHRONIZATION CIRCUIT AND OPERATION METHOD THEREOF - A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal. | 07-09-2009 |
20090273385 | OUTPUT CIRCUIT OF SEMICONDUCTOR DEVICE - An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals. | 11-05-2009 |
20090284293 | DUTY CORRECTION CIRCUIT - A duty correction circuit includes a duty ratio sensor for controlling a duty ratio sensing speed by a sensing speed control signal and outputting a correction signal by sensing a duty ratio of a clock, and a duty ratio corrector for controlling the duty ratio of the clock in response to the correction signal. | 11-19-2009 |
20090302891 | OUTPUT DRIVER - There is provided an output driver, which includes a pre-driver configured to generate a main driving control signal in response to a data signal, a main driver configured to drive an output terminal in response to the main driving control signal, an auxiliary driving control signal generator configured to generate an auxiliary driving control signal having an activation interval corresponding to the data signal and an interval control signal, and an auxiliary driver configured to drive the output terminal in response to the auxiliary driving control signal. | 12-10-2009 |
20090303827 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a clock supply portion for providing an external clock to the interior of the memory device, a clock transfer portion for transferring the clock from the clock supply portion to each of elements in the memory device and data output portions for outputting data in synchronism the clock from the clock transfer portion, wherein the clock from the clock supply portion to the clock transfer portion swings at a current mode logic (CML) level. | 12-10-2009 |
20090323444 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes a second clock transmission path configured to convert the source clock in a clock swinging at a CMOS level in response to the enable signal, and to output the converted clock through the clock transmission line and a data output unit configured to output data in response to output clocks of the first and second clock transmission lines. | 12-31-2009 |
20100007372 | SEMICONDUCTOR DEVICE - A semiconductor, which includes a first phase detecting unit configured to detect a phase of a second clock on the basis of a phase of a first clock, and generate a first detection signal corresponding to a result of the detection, a second phase detecting unit configured to detect a phase of a delayed clock, which is generated by delaying the second clock by a predetermined time, on the basis of the phase of the first clock, and generate a second detection signal corresponding to a result of the detection, and a logic level determining unit configured to determine a logic level of a feedback output signal according to the first detection signal, the second detection signal and the feedback output signal. | 01-14-2010 |
20100054059 | SEMICONDUCTOR MEMORY DEVICE - A circuit which can reduce time taken by a clock alignment training operation in a semiconductor memory device is provided. The semiconductor memory device, which includes: a clock inputting unit configured to receive a system clock and a data clock; a clock dividing unit configured to divide a frequency of the data clock to generate a data division clock, wherein the clock dividing unit determines a phase of the data division clock in response to an inversion division control signal; a phase dividing unit configured to generate a plurality of multiple phase data division clocks having respective predetermined phase differences in response to the data division clock; a data serializing unit configured to serialize predetermined parallel pattern data in correspondence with the multiple phase data division clocks; and a signal transmitting unit configured to transmit an output signal of the data serializing unit to the outside. | 03-04-2010 |
20100091598 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a first data selection section inputted with the first data and second data and output one of the first data and the second data as first selection data in response to an address signal, a second data selection section inputted with the second data and the first selection data and output one of the second data and the first selection data as second selection data depending upon an input and output mode, and a data output section configured to be inputted with the first and second selection data and output first and second output data. | 04-15-2010 |
20100141323 | DELAY LINE - A delay line has a high response speed by minimizing the amount of loading on an input node and an output node while delaying an input signal over a wide variation range. The delay line includes a forward delay unit configured to determine the length of a forward delay path passing an input signal in response to a delay control code, a reverse delay unit configured to receive an output signal of the forward delay unit, and to output a delayed input signal through a reverse delay path that is as long as the length of the forward delay path determined by the delay control code, and a transfer unit configured to transfer the output signal of the forward delay unit from a turn point determined by the delay control code to the reverse delay unit. | 06-10-2010 |
20100142244 | MEMORY MODULE AND DATA INPUT/OUTPUT SYSTEM - A memory module is configured to include a first rank installed with a first memory chip and a second rank installed with a second memory chip. When the first and second memory chips are in a first data output mode, the first memory chip is configured to externally output lower order data of a plurality of data via lower data output pins. Also, when the first and second memory chips are in the first data output mode, the second memory chip is configured to externally output data that has the same order as the lower order data output by the first memory chip via upper data output pins. | 06-10-2010 |
20100164572 | SEMICONDUCTOR DEVICE - A semiconductor device includes a latency signal generating circuit for generating a latency signal corresponding CAS latency by measuring a delay amount reflected at a delay locked loop and reflecting the measured delay amount at a read command signal, and a delay locked loop for controlling an internal clock signal applied to the latency signal generating circuit corresponding to the read command and the latency signal. The semiconductor device includes an internal clock signal generating block configured to generate an internal clock signal, a latency generating block configured to generate a latency signal by synchronizing a read command signal with the internal clock signal at a time corresponding to a CAS latency value and a measured delay value, and an input controlling block configured to activate the reference clock signal using an external clock signal in response to the read command signal and the latency signal. | 07-01-2010 |
20100308860 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of data driving units, each configured to drive a corresponding data output pad by a power supply voltage supplied through a power supply voltage input pin and a ground voltage supplied through a ground voltage input pin, in response to a corresponding bit of a data code, a pattern sensing unit configured to sense a bit pattern of the data code and generate a pattern sensing signal, and a phantom driving unit configured to form a current path between the power supply voltage input pin and the ground voltage input pin and to drive the current path by a driving force determined in response to the pattern sensing signal. | 12-09-2010 |
20110001537 | DELAY LINE - A delay line includes a delay amount adjusting unit configured to adjust a delay amount of an input signal in response to a first delay control code, and a delay unit configured to determine a number of first delay blocks having a delay amount with a first variation width and a number of second delay blocks having a delay amount with a second variation width in response to a second delay control code, wherein the delay amount with the first variation width and the delay amount with the second variation width are determined by the delay amount adjusting unit and the first and second variation widths correspond to a level change of a power supply. | 01-06-2011 |
20110156791 | OUTPUT CIRCUIT OF SEMICONDUCTOR DEVICE - An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals. | 06-30-2011 |
20110187427 | LATENCY CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A latency control circuit includes a delay unit configured to delay an input signal for a delay corresponding to a phase difference between an external clock and an internal clock and generate a delayed input signal, a delay information generation unit configured to generate a delay information based on a latency information and a delay amount of the input signal caused by a chip including the latency control circuit, a shift unit configured to shift the delayed input signal for a time period corresponding to the delay information in synchronism with the internal clock and an asynchronous control unit configured to selectively control the shift unit to output the delayed input signal without performing a shift operation. | 08-04-2011 |
20110242922 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a first data selection section inputted with the first data and second data and output one of the first data and the second data as first selection data in response to an address signal, a second data selection section inputted with the second data and the first selection data and output one of the second data and the first selection data as second selection data depending upon an input and output mode, and a data output section configured to be inputted with the first and second selection data and output first and second output data. | 10-06-2011 |
20120218831 | INTEGRATED CIRCUIT FOR STORING INFORMATION - An integrated circuit includes a variable resistance unit including at least one transistor that receives a control signal and changes a resistance through the transistor in response to the control signal in a programming operation mode and an information detection unit configured to detect programming information in response to an output voltage of the variable resistance unit in a normal operation mode. | 08-30-2012 |