Patent application number | Description | Published |
20100055823 | Methods of manufacturing CMOS image sensors - Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) and methods of manufacturing the same are provided, the sensors include an epitaxial layer on a substrate in which a first, second, third and fourth region are defined. A photodiode may be formed at an upper portion of the epitaxial layer in the first region. A plurality of gate structures may be formed on the epitaxial layer in the second, third and fourth regions. A first blocking layer may be formed on the gate structures and the epitaxial layer in the first and second regions. A first impurity layer may be formed at an upper portion of the epitaxial layer adjacent to the gate structures in the second region, and a second impurity layer at upper portions of the epitaxial layer adjacent to the gate structures in the third and fourth regions. A color filter layer may be formed over the photodiode. A microlens may be formed on the color filter layer. | 03-04-2010 |
20110163363 | COMS image sensors and methods of manufacturing the same - Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) and methods of manufacturing the same are provided, the sensors include an epitaxial layer on a substrate in which a first, second, third and fourth region are defined. A photodiode may be formed at an upper portion of the epitaxial layer in the first region. A plurality of gate structures may be formed on the epitaxial layer in the second, third and fourth regions. A first blocking layer may be formed on the gate structures and the epitaxial layer in the first and second regions. A first impurity layer may be formed at an upper portion of the epitaxial layer adjacent to the gate structures in the second region, and a second impurity layer at upper portions of the epitaxial layer adjacent to the gate structures in the third and fourth regions. A color filter layer may be formed over the photodiode. A microlens may be formed on the color filter layer. | 07-07-2011 |
20120164783 | CMOS IMAGE SENSOR HAVING A CROSSTALK PREVENTION STRUCTURE AND METHOD OF MANUFACTUREING THE SAME - In a method of manufacturing a CMOS image sensor, a P type epitaxial layer is formed on an N type substrate. A deep P | 06-28-2012 |
Patent application number | Description | Published |
20110157299 | APPARATUS AND METHOD OF VIDEO CONFERENCE TO DISTINGUISH SPEAKER FROM PARTICIPANTS - Disclosed are a system and a method that generates image data that represent a speaker to be distinguished, and enables a mobile terminal to provide a video conference service using the image data that distinguishes the speaker. A video conference apparatus may include a speaker distinguishing unit to distinguish, as a speaker, a participant who is speaking from a plurality of participants in the video conference and an image data generating unit to generate image data that represents the distinguished participant differently from other participants. | 06-30-2011 |
20120331323 | DEVICES AND METHODS FOR SAVING ENERGY THROUGH CONTROL OF SLEEP MODE - A system for saving energy through control of a sleep mode, and a method of operating the system are provided. The energy-saving system may enable a proxy device to maintain a minimum basic setup necessary for a communication when a host device enters a sleep mode, and may omit an operation performed based on the basic setup when the host device switches to a communication mode, thereby enabling a smooth switch between the sleep mode and the communication mode. | 12-27-2012 |
20130028160 | COMMUNICATION METHOD AND DEVICE FOR ENHANCING ENERGY EFFICIENCY - Provided is a method and device for increasing energy efficiency by adaptively performing clipping with respect to an input signal. The method may adaptively determine a clipping ratio (CR) based on a modulation method of the communication device and perform clipping based on the determined CR. | 01-31-2013 |
20130244716 | METHOD FOR DETERMINING TRANSMISSION POWER IN MIMO SYSTEM BASED ON COOPERATIVE TRANSMISSION - A method for determining a transmission power in a multi-input multi-output (MIMO) system based on a cooperative transmission is provided. The method includes setting a power constraint condition of a transmitter and target quality information of a receiver. The method further includes determining the transmission power to be allocated to the transmitter to transmit the data to the receiver based on the power constraint condition and the target quality information. | 09-19-2013 |
20130286911 | METHOD AND APPARATUS FOR USER SCHEDULING IN MULTI-USER MULTIPLE INPUT MULTIPLE OUTPUT (MIMO) COMMUNICATION SYSTEM - A method and apparatus for user scheduling in a multi-user multiple input multiple output (MIMO) communication system are provided. The method includes identifying a user group comprising user terminals. The method further includes comparing power consumptions based on the user group. The method further includes scheduling the user terminals based on the comparing. | 10-31-2013 |
20140011508 | METHOD AND APPARATUS FOR DETERMINING NUMBER OF ANTENNAS IN MULTIPLE INPUT MULTIPLE OUTPUT (MIMO) COMMUNICATION SYSTEM - A method of determining a number of antennas, includes calculating a power used by a transmitting device. The method further includes calculating a channel capacity of the transmitting device. The method further includes determining a number of antennas of the transmitting device to be used based on the power and the channel capacity. | 01-09-2014 |
20140184456 | ANTENNA AND COMMUNICATION SYSTEM INCLUDING THE ANTENNA - An antenna and a communication system with the antenna are provided. The antenna may include a first layer including a plurality of folded stubs, a second layer including a pattern of the folded stubs, and a third layer connected to ground is disposed between the first layer and the second layer. | 07-03-2014 |
20140185509 | CENTRAL CONTROL APPARATUS AND METHOD FOR ENERGY EFFICIENCY OF A BASE STATION IN A MOBILE COMMUNICATION SYSTEM - A central control apparatus and method thereof include a traffic demand receiving unit, a traffic demand calculating unit, a base station efficiency calculating unit, and a base station management unit. The traffic demand receiving unit is configured to receive a required traffic demand and a current location of each of terminals. The traffic demand calculating unit is configured to calculate traffic of each of base stations to which a terminal is unassigned. The base station efficiency calculating unit is configured to calculate an energy efficiency of each of the base stations. The base station management unit configured to verify a base station with an optimum energy efficiency, to activate the base station with the optimum energy efficiency, and to assign the terminals of a corresponding region to the base station with the optimum energy efficiency. | 07-03-2014 |
20140335804 | TRANSMITTER FOR SUPPORTING MULTIMODE AND MULTIBAND USING MULTIPLE RADIO FREQUENCY (RF) DIGITAL-TO-ANALOG CONVERTERS (DAC) AND CONTROL METHOD OF THE TRANSMITTER - A transmitter configured to support a multimode and a multiband, using radio frequency (RF) digital-to-analog converters (DACs), includes a first RF DAC configured to transmit a first signal in a first frequency band, and a second RF DAC configured to transmit a second signal in a second frequency band different from the first frequency band. The transmitter further includes an impedance controller configured to adjust impedance of one of the first RF DAC and the second RF DAC operating in an impedance matching mode to adjust a frequency range of another one of the first RF DAC and the second RF DAC operating in a data transmission mode. | 11-13-2014 |
20140348254 | METHOD AND APPARATUS FOR REDUCING PEAK-TO-AVERAGE POWER RATIO (PAPR) OF ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING (OFDM) SIGNAL AND TRANSMITTER - Methods and apparatus for reducing a peak-to-average power ratio (PAPR) of an orthogonal frequency division multiplexing (OFDM) signal in an MIMO-OFDM communication system is provided, in which the method for reducing the PAPR of the OFDM signal may identify interference generated in an MIMO communication system, and adjust a clipping ratio (CR) for an effect of a clipping distortion to be less than an effect of interference. | 11-27-2014 |
20150070225 | METHOD AND DEVICE FOR DETERMINING TRANSMISSION POWER IN MULTI-ANTENNA COMMUNICATION SYSTEM - A method and a device for determining transmission power in a multi-antenna communication system are provided. The method for determining transmission power includes calculating the power consumption of a transmission device, calculating the capacity of the transmission device, and determining transmission power for maximizing the energy efficiency of the transmission device by using the power consumption and the capacity thereof. | 03-12-2015 |
Patent application number | Description | Published |
20100088552 | Method for Obstruction and Capacity Information Unification Monitoring in Unification Management System Environment and System for Thereof - Provided are a method and system for integrated monitoring of fault and performance information in an integrated management system environment including an integrated management server that interworks with a managed server having a built-in agent for the sake of integrated management of a variety of management information. The method includes the steps of: collecting, at the agent, in real time, fault information data of the managed server using queues; periodically collecting, at the agent, performance information data of the managed server using a function-specific remote function module (REM); converting, at the agent, the fault and performance information data collected from the managed server into a format that the integrated management server can recognize and transferring it; receiving, at the integrated management server, the fault information data from the agent, and generating and transferring an event message to a corresponding administrator terminal; and receiving, at the integrated management server, the performance information data from the agent and storing it in a previously prepared database (DB). Therefore, even when a user docs not directly access a managed server, fault and performance information data is transferred in real time to the corresponding administrator so that loss due to faults can be minimized. | 04-08-2010 |
20100145950 | Realtime Unification Management Information Data Conversion and Monitoring Apparatus and Method for Thereof - Provided are an apparatus and method for converting and monitoring management information data in an integrated manner and in real time. More particularly, the present invention relates to an apparatus and method for converting and monitoring management information data in an integrated manner and in real time which are capable of reducing the number of processes and stably operating an IT infrastructure through integrated management by flexibly collecting and converting management information data having a variety of formats and transmitting it to a destination integrated management solution when existing point-specific management solutions are managed in an integrated manner using an integrated management solution. | 06-10-2010 |
Patent application number | Description | Published |
20120064584 | BUFFER COMPOSITION FOR CATALYZING THE PREPARATION OF CALCITRIOL OR CALCIFEDIOL AND METHOD FOR PREPARING CALCITRIOL OR CALCIFEDIOL USING SAME - The present invention relates to a buffer composition for promoting production of calcitriol or calcifediol, and a method for producing calcitriol or calcifediol using the same. More particularly, the present invention relates to a buffer composition for promoting production of calcitriol or calcifediol comprising a metallic compound, an organic solvent, cyclodextrin, tris(hydroxymethyl)aminomethane, sodium succinate, sodium chloride, magnesium chloride, and water, and a method for producing calcitriol or calcifediol using the same. In the method for producing calcitiriol or calcifediol, the production yield of calcitriol or calcifediol is high, and the bioconversion is carried out in an enzyme reaction system instead of in a microorganism culture system. Thus, it is not required to maintain a sterile state. Also, the separation/purification following the completion of a biocatalytic reaction can be carried out in a cleaner state than the microorganism culture method. Accordingly, there is an advantage in that a cost required for separation is low and the quality is improved. Furthermore, the buffer composition for promoting production of calcitriol or calcifediol can provide a high productivity of calcitriol or calcifediol. | 03-15-2012 |
20120232261 | METHOD FOR MANUFACTURING LOW MOLECULAR WEIGHT HYALURONIC ACID - The present invention relates to a method for preparing low molecular weight hyaluronic acid from high molecular weight hyaluronic acid which is produced by | 09-13-2012 |
20140206040 | STREPTOCOCCUS DYSGALACTIAE ID9103 AND METHOD FOR PRODUCTION OF HYALURONIC ACID USING THE SAME - Provided is a | 07-24-2014 |
Patent application number | Description | Published |
20090231914 | Memory devices and methods - Disclosed are a memory device and a memory data reading method. The memory device may include a multi-bit cell array, a threshold voltage detecting unit configured to detect first threshold voltage intervals including threshold voltages of multi-bit cells of the multi-bit cell array from among a plurality of threshold voltage intervals, a determination unit configured to determine data of a first bit layer based on the detected first threshold voltage intervals, and an error detection unit configured to detect an error bit of the data of the first bit layer. In this instance, the determination unit may determine data of a second bit layer using a second threshold voltage interval having a value of the first bit layer different from the detected error bit and being nearest to a threshold voltage of a multi-bit cell corresponding to the detected error bit. | 09-17-2009 |
20100110786 | Nonvolatile memory device, memory system including the same, and memory test system - Provided are a nonvolatile memory device and a memory test system. The nonvolatile memory device includes a temperature compensator to calculate a trim value for regulating a characteristic of the nonvolatile memory device that varies with temperature in response to a test signal. The memory test system includes a plurality of nonvolatile memories and a tester. Each of the nonvolatile memories includes a temperature compensator. The tester tests the plurality of nonvolatile memories. The temperature compensator calculates a trim value for regulating a characteristic of the nonvolatile memory device that varies with temperature in response to a test signal of the tester. | 05-06-2010 |
20100246260 | NONVOLATILE MEMORY DEVICE, SYSTEM, AND PROGRAMMING METHOD - A method of programming a nonvolatile memory device comprises selectively programming memory cells from a first state to a second state based on lower bit data, selectively programming the memory cells from the second state to an intermediate state corresponding to the lower bit data, and selectively programming the memory cells from the intermediate state to a third or fourth state based on upper bit data. | 09-30-2010 |
20120081957 | FLASH MEMORY DEVICE AND WORDLINE VOLTAGE GENERATING METHOD THEREOF - A word line voltage generating method of a flash memory which includes generating a program voltage using a positive voltage generator; generating a plurality of negative program verification voltages corresponding to a plurality of negative data states using a negative voltage generator; and generating at least one or more program verification voltages corresponding to at least one or more states using the positive voltage generator. Generating a plurality of negative program verification voltages includes generating a first negative verification voltage; discharging an output of the negative voltage generator to become higher than the first negative verification voltage; and performing a negative charge pumping operation until an output of the negative voltage generator reaches a second negative verification voltage level. | 04-05-2012 |
20130088923 | NONVOLATILE MEMORY DEVICE, SYSTEM, AND PROGRAMMING METHOD - A method of programming a nonvolatile memory device comprises selectively programming memory cells from a first state to a second state based on lower bit data, selectively programming the memory cells from the second state to an intermediate state corresponding to the lower bit data, and selectively programming the memory cells from the intermediate state to a third or fourth state based on upper bit data. | 04-11-2013 |
Patent application number | Description | Published |
20110163364 | IMAGE SENSOR, FABRICATING METHOD THEREOF, AND DEVICE COMPRISING THE IMAGE SENSOR - Image sensor, fabricating method thereof, and device comprising the image sensor are provided, which comprises a substrate in which a photoelectric transformation device is formed, an interconnection structure formed on the substrate and including multiple intermetal dielectric layers and multiple metal interconnections placed in the multiple intermetal dielectric layers, the interconnection structure defining a cavity aligned corresponding to the photoelectric transformation device, a moisture absorption barrier layer conformally formed on a top of the interconnection structure and in the cavity; and a light guide unit formed on the moisture absorption barrier layer and including light transmittance material filling the cavity, wherein the moisture absorption barrier layer is formed with a uniform thickness on both sides and a bottom of the cavity and on a top surface of the multiple intermetal dielectric layer. | 07-07-2011 |
20150041944 | IMAGE SENSOR, FABRICATING METHOD THEREOF, AND DEVICE COMPRISING THE IMAGE SENSOR - Image sensor, fabricating method thereof, and device comprising the image sensor are provided, which comprises a substrate in which a photoelectric transformation device is formed, an interconnection structure formed on the substrate and including multiple intermetal dielectric layers and multiple metal interconnections placed in the multiple intermetal dielectric layers, the interconnection structure defining a cavity aligned corresponding to the photoelectric transformation device, a moisture absorption barrier layer conformally formed on a top of the interconnection structure and in the cavity; and a light guide unit formed on the moisture absorption barrier layer and including light transmittance material filling the cavity, wherein the moisture absorption barrier layer is formed with a uniform thickness on both sides and a bottom of the cavity and on a top surface of the multiple intermetal dielectric layer. | 02-12-2015 |
Patent application number | Description | Published |
20090040420 | Backlight unit and image display apparatus including the backlight unit - In a backlight unit and an image display apparatus including the backlight unit, the backlight unit includes a base substrate and a transparent substrate arranged to face each other; a cathode electrode and a first gate electrode alternately arranged on an upper surface of the base substrate; an emitter arranged on an edge of the cathode electrode facing the first gate electrode; an insulation layer arranged on the cathode electrode and the first gate electrode; a second gate electrode arranged on an upper surface of the insulation layer; and a fluorescent layer arranged on a lower surface of the transparent substrate. An aperture is arranged in the insulation layer and second gate electrode, the aperture being in an area corresponding to the emitter. | 02-12-2009 |
20090040423 | Backlight unit and image display apparatus employing the same - A backlight unit that can perform local dimming, and has a structure for preventing light leakage and a cooling structure, and an image display apparatus employing the backlight unit. The backlight unit includes a light emitting arrangement adapted to radiate light and a plurality of light. shielding guides adapted to divide the light emitting arrangement into a plurality of unit blocks, the unit blocks being adapted to provide local dimming, the light shielding guides being further adapted to prevent light from traveling from one of said unit blocks to another of said unit blocks. | 02-12-2009 |
20090167150 | Field emission surface light source apparatus and method of fabricating the same - Provided are a field emission surface light source apparatus and a method of fabricating the field emission surface light source apparatus. The field emission surface light source apparatus includes a base substrate and a transparent substrate facing each other, a plurality of gate electrodes formed on an upper surface of the base substrate, an insulating layer formed on the upper surface of the base substrate to cover the gate electrodes, a plurality of emitters formed on an upper surface of the insulating layer, and a fluorescent layer formed on a lower surface of the transparent substrate. The fluorescent layer faces the emitters. | 07-02-2009 |
20100193731 | COMPOSITE ANODE ACTIVE MATERIAL, ANODE INCLUDING THE COMPOSITE ANODE ACTIVE MATERIAL, LITHIUM BATTERY INCLUDING THE ANODE, AND METHOD OF PREPARING THE COMPOSITE ANODE ACTIVE MATERIAL - A composite anode active material including metal core particles and carbon nanotubes that are covalently bound to the metal core particles, an anode including the composite anode active material, a lithium battery employing the anode, and a method of preparing the composite anode active material. | 08-05-2010 |
20110121338 | FLUORO GROUP-CONTAINING COMPOUND, FLUORO GROUP-CONTAINING POLYMER, ORGANIC LIGHT EMITTING DEVICE INCLUDING THE POLYMER, AND METHOD OF MANUFACTURING THE DEVICE - A fluoro group-containing compound, a fluoro group-containing polymer, an organic light emitting device including the polymer, and a method of manufacturing the organic light emitting device are provided. | 05-26-2011 |
20130146849 | POLYMER AND ORGANIC LIGHT-EMITTING DIODE INCLUDING THE SAME - A polymer having a repeating unit represented by Formula 1, wherein R | 06-13-2013 |
20140070147 | COMPOSITE ANODE ACTIVE MATERIAL, ANODE INCLUDING THE COMPOSITE ANODE ACTIVE MATERIAL, LITHIUM BATTERY INCLUDING THE ANODE, AND METHOD OF PREPARING THE COMPOSITE ANODE ACTIVE MATERIAL - A composite anode active material including metal core particles and carbon nanotubes that are covalently bound to the metal core particles, an anode including the composite anode active material, a lithium battery employing the anode, and a method of preparing the composite anode active material. | 03-13-2014 |
Patent application number | Description | Published |
20090058868 | IMAGE DISPLAY DEVICE AND METHOD OF CHANGING EDID INFORMATION THEREOF - An image display device and method of changing extended display identification data (EDID) information includes a first storage unit which stores extended display identification data (EDID) information to be provided to the source providing device, a second storage unit which stores at least one version of the EDID information which is different from the EDID information stored in the first storage unit, and a control unit which replaces the EDID information stored in the first storage unit with the different version of the EDID information stored in the second storage unit if an EDID information change request signal is input. Accordingly, compatibility of the EDID information between the source providing device and the image display device can be maintained. | 03-05-2009 |
20090080134 | ELECTRONIC DEVICE AND METHOD FOR REMOVING STATIC ELECTRICITY - An electronic device and a method for removing a static electricity thereof are provided. The method for removing a static electricity includes performing a switching operation to transmit a signal output from an interface, which is communicably connected to an external device, to a signal processor or cut off the signal from being transmitted to the signal processor, and based on this switching operation, performing a switching operation to supply a bias power to the signal processor or cut off a supply of power to the signal processor. Accordingly, a static electricity signal is grounded using a switch based on an operation state of the electronic device such that a static electricity shock and static electricity noise can be prevented from affecting the electronic device. | 03-26-2009 |
20090091665 | DISPLAY APPARATUS AND METHOD OF CHANGING EDID INFORMATION THEREOF - A display apparatus connected to a video/audio output device includes at least two connecting portions to connect with the video/audio output device, a first storage unit to store extended display identification data (EDID) information to be provided to the video/audio output device, a second storage unit to store EDID information corresponding to the two connecting portions respectively, and a controller to change the EDID information stored in the first storage unit into one information of a currently connected connecting portion among the EDID information stored in the second storage unit when the connecting portion connected with the video/audio output device is changed. | 04-09-2009 |
20100052420 | METHOD FOR SELECTING AN ELECTRIC POWER SUPPLY, A CIRCUIT AND AN APPARATUS THEREOF - A method for selecting an electric power supply and a circuit thereof are provided. The method includes detecting whether there is an output signal from a high electric power source, connecting a low electric power source with input of a transformer if there is no output signal from the high electric power source, disconnecting output of the transformer with a general circuit if there is no output signal from the high electric power source, transforming a voltage received from the low electric power source, and outputting the transformed voltage to a control unit. By disconnecting the output of the transformer with the general circuit, the low power source may reduce waste of an electric power. | 03-04-2010 |
20120013604 | DISPLAY APPARATUS AND METHOD FOR SETTING SENSE OF DEPTH THEREOF - A display apparatus is provided. The display apparatus includes a display and an image extractor that extracts a reference object included in an input image, an image converter that calculates a distance from a position on a screen at which the input image is displayed to a virtual position of the reference object when the reference object is expressed as a 3D image. The display apparatus automatically sets a depth corresponding to the distance, and a controller controls the display unit to display the input image as a 3D image according to the set depth. | 01-19-2012 |
20120038655 | IMAGE DISPLAY DEVICE AND METHOD OF CHANGING EDID INFORMATION THEREOF - An image display device and method of changing extended display identification data (EDID) information includes a first storage unit which stores extended display identification data (EDID) information to be provided to the source providing device, a second storage unit which stores at least one version of the EDID information which is different from the EDID information stored in the first storage unit, and a control unit which replaces the EDID information stored in the first storage unit with the different version of the EDID information stored in the second storage unit if an EDID information change request signal is input. Accordingly, compatibility of the EDID information between the source providing device and the image display device can be maintained. | 02-16-2012 |
20130113890 | 3D LOCATION SENSING SYSTEM AND METHOD - A 3-dimensional (3D) location sensing system and method. The 3D location sensing system includes: an emitter which emits light including a plurality of markers onto an object; two or more photographing units which sense the light reflected from the object to respectively sense one or more markers; and a controller which calculates a 3D location coordinate of the object based on information about the one or more markers sensed by the two or more photographing units. | 05-09-2013 |
20130162908 | DISPLAY APPARATUS AND SIGNAL PROCESSING MODULE FOR RECEIVING BROADCASTING AND DEVICE AND METHOD FOR RECEIVING BROADCASTING - A display apparatus for receiving broadcasting includes a display unit configured to display an image thereon, a cover which partially covers the display unit, at least one signal connector which is configured to connect to a portable signal processing module that is located outside the cover and processes a signal to be displayed by the display unit, and receives the signal processed by the signal processing module, and a timing controller (T-con) configured to control a display timing of the signal received by the at least one signal connector. | 06-27-2013 |
20130169625 | IMAGE PROCESSING APPARATUS, UPGRADE APPARATUS, DISPLAY SYSTEM INCLUDING THE SAME, AND CONTROL METHOD THEREOF - An image processing apparatus, upgrade apparatus, display system and control method are provided. The image processing apparatus includes a signal input unit; a first image processing unit which processes an input signal input by the signal input unit to output a first output signal; an upgrade apparatus connection unit connected to an upgrade apparatus which includes a second image processing unit; and a first controller which controls at least one of the input signal processed by the first image processing unit and the first output signal to be transmitted to the upgrade apparatus and processed by the second image processing unit if the upgrade apparatus is connected to the upgrade apparatus connection unit. | 07-04-2013 |
20130169652 | IMAGE PROCESSING APPARATUS, UPGRADE APPARATUS, DISPLAY SYSTEM INCLUDING THE SAME, AND CONTROL METHOD THEREOF - An image processing apparatus, upgrade apparatus, display system and control method are provided. The image processing apparatus includes a signal input unit; a first image processing unit which processes an input signal input by the signal input unit to output a first output signal; an upgrade apparatus connection unit connected to an upgrade apparatus which includes a second image processing unit; and a first controller which controls at least one of the input signal processed by the first image processing unit and the first output signal to be transmitted to the upgrade apparatus and processed by the second image processing unit if the upgrade apparatus is connected to the upgrade apparatus connection unit | 07-04-2013 |
20130194302 | DISPLAY SYSTEM INCLUDING A DISPLAY APPARATUS AND AN UPGRADING APPARATUS, AND CONTROL METHOD - A display system including a display apparatus and an upgrading apparatus are provided along with a control method. A display apparatus includes an image processor which processes an image signal, a display which displays the processed image thereon, a connector to which an upgrading apparatus comprising at least one upgrading function is connected and a controller which communicates with the upgrading apparatus and controls the display to display thereon a user interface (UI) screen displaying at least one upgrading function list generated by the upgrading apparatus in response to a user selection. | 08-01-2013 |
20130194322 | DISPLAY APPARATUS AND DISPLAY METHOD THEREOF - A display apparatus is provided. The display apparatus includes a display unit that includes a plurality of pixels and is configured to display at least one image frame by illuminating the plurality of pixels on a pixel basis; a motion measuring unit that measures a motion per pixel of the at least one image frame by comparing a plurality of image frames to be displayed on the display unit; and a controller that adjusts a light emission intensity and a light emission time per pixel of the display unit according to a magnitude of the measured motion. | 08-01-2013 |
20130222400 | IMAGE PROCESSING APPARATUS, UPGRADE APPARATUS, DISPLAY SYSTEM INCLUDING THE SAME, AND CONTROL METHOD THEREOF - An image processing apparatus, upgrade apparatus, display system and control method are provided. The image processing apparatus includes a signal input unit; a first image processing unit which processes an input signal input by the signal input unit to output a first output signal; an upgrade apparatus connection unit connected to an upgrade apparatus which includes a second image processing unit; and a first controller which controls at least one of the input signal processed by the first image processing unit and the first output signal to be transmitted to the upgrade apparatus and processed by the second image processing unit if the upgrade apparatus is connected to the upgrade apparatus connection unit. | 08-29-2013 |
20150028838 | ELECTRONIC APPARATUS AND POWER CONTROLLING METHOD - An electronic apparatus and a method of controlling power thereto are disclosed. The electronic apparatus including: a signal receiver configured to receive an input signal; a power supply configured to supply power to elements of the electronic apparatus; a controller configured to controls power supplied to the power supply; and a driving circuit configured to output an ON signal to the power supply in order to supply power to the elements of the electronic apparatus in response to the signal receiver receiving a preset frequency signal while the controller is turned off. Thus, the electronic apparatus is automatically turned on and off by an input signal of a predetermined frequency without a user's manipulation of an additional power switch, and thus, a user's convenience may be improved. | 01-29-2015 |
Patent application number | Description | Published |
20090205570 | Gas supply unit and chemical vapor deposition apparatus - A gas supply unit and a chemical vapor deposition apparatus are disclosed. A gas supply unit for supplying a reactive gas for a chemical vapor deposition process can include a hot wire part configured to pyrolyze the reactive gas, an ejection part configured to eject the reactive gas towards the hot wire part, and a suction part disposed adjacent to the hot wire part and configured to suck in and exhaust a by-product of the reactive gas. With certain embodiments of the invention, the by-products resulting from the chemical vapor deposition process may be exhausted immediately, so that a thin film may be formed over an object with higher quality, and the cleaning cycles for the inside of the chamber may be extended, for greater productivity. | 08-20-2009 |
20100037947 | Thin film type solar cell and method for manufacturing the same - A thin film type solar cell and a method for manufacturing the same is disclosed, the thin film type solar cell comprising a first electrode in a predetermined pattern on a substrate; a first semiconductor layer on the first electrode; a second electrode in a predetermined pattern on the first semiconductor layer; a second semiconductor layer on the second electrode; and a third electrode in a predetermined pattern on the second semiconductor layer, the first and third electrodes being electrically connected with each other, wherein a first solar cell is composed of a combination of the first electrode, the first semiconductor layer, and the second electrode; a second solar cell is composed of a combination of the second electrode, the second semiconductor layer, and the third electrode; and the first and second solar cells are connected in parallel, whereby it is possible to realize improved efficiency of the entire thin film type solar cell without performing a process for a current matching between the first and second solar cells. | 02-18-2010 |
Patent application number | Description | Published |
20120043819 | POWER STORAGE SYSTEM, METHOD OF CONTROLLING THE SAME, AND COMPUTER READABLE RECORDING MEDIUM STORING A PROGRAM FOR EXECUTING THE METHOD - A power storage system for supplying power to a load by coupling a power generation system, a battery, and a grid, the power storage system includes a battery management system (BMS) for controlling charging and discharging of the battery and a power supply circuit for supplying power to the BMS, wherein the power supply circuit is configured to supply external power to the BMS as an operating power of the BMS in a first state in which the external power is applied, and the power supply circuit is configured to supply power of the battery to the BMS as the operating power of the BMS in a second state in which the external power is not applied. | 02-23-2012 |
20120261997 | POWER CONTROL SYSTEM AND CONTROLLING METHOD THEREOF - A power control system includes a rechargeable battery, the rechargeable battery including a first battery unit and including a second battery unit connected to a first terminal of the first battery unit at a first node, a switching unit, the switching unit including a first switch connected to a second terminal of the first battery unit and including a second switch connected to the first node, and a control unit, the control unit being configured to generate and transmit switch control signals respectively corresponding to the first switch and the second switch, and being configured to control a voltage of the rechargeable battery such that the voltage is maintained in a threshold range of a predetermined rated voltage. | 10-18-2012 |
20130141051 | ENERGY STORAGE SYSTEM AND METHOD FOR CONTROLLING THE SAME - An energy storage system configured to be coupled to at least one of a power generation system, a grid, or a load, the energy storage system including a battery system including at least one rack, the at least one rack including a rack controller, and a system controller configured to control a charging operation and a discharging operation of at least one battery on the at least one rack in accordance with a temperature of the at least one battery. | 06-06-2013 |
Patent application number | Description | Published |
20120135545 | LASER APPARATUS AND METHOD FOR MANUFACTURING A SOLAR CELL MODULE USING THE SAME - A method for manufacturing a solar cell module includes forming a first electrode on a first surface of a substrate; forming a semiconductor layer on the first electrode; forming a second electrode on the semiconductor layer; inverting the substrate with the first electrode, semiconductor layer and second electrode formed thereon, and then, positioning the inverted substrate on a plurality of supports; patterning the second electrode and the semiconductor layer while the inverted substrate is on the supports by irradiating a laser on a second surface of the substrate to form a plurality of solar cells, wherein the second surface of the substrate is opposite the first surface of the substrate; identifying defective solar cells by using the supports; and repairing the defective solar cells by using the supports. | 05-31-2012 |
20130037086 | PHOTOVOLTAIC DEVICE - A photovoltaic device and a manufacturing method thereof are provided. The photovoltaic device includes: a substrate; a first conductive layer formed on the substrate; P layers and N layers alternately formed along a first direction on the first conductive layer; and I layers covering the P layers and the N layers on the first conductive layer, wherein the P layers and the N layers are separated from each other by a first interval, the I layers are formed between the P layers and the N layers that are separated by the first interval, and the P layers, the I layers, and the N layers formed along the first direction form unit cells. | 02-14-2013 |
20130045564 | Method of manufacturing a photovoltaic device - A photovoltaic device and a manufacturing method thereof are provided. The photovoltaic device includes: a substrate; a first conductive layer formed on the substrate; P layers and N layers alternately formed along a first direction on the first conductive layer; and I layers covering the P layers and the N layers on the first conductive layer, wherein the P layers and the N layers are separated from each other by a first interval, the I layers are formed between the P layers and the N layers that are separated by the first interval, and the P layers, the I layers, and the N layers formed along the first direction form unit cells. | 02-21-2013 |
20140137931 | SOLAR CELL AND METHOD OF MANUFACTURING THE SAME - A solar cell having improved electric energy generation efficiency and a method of manufacturing the solar cell. The solar cell includes a substrate, a rear electrode layer on the substrate and comprising a first rear electrode and a second rear electrode spaced from each other, a window electrode layer on the rear electrode layer and comprising a first window electrode electrically coupled to the second rear electrode at a contact region on the second rear electrode, a light-absorbing layer between the rear electrode layer and the window electrode layer, and an insulating layer on a first portion of the second rear electrode, wherein the first portion is between an edge of the second rear electrode facing the first rear electrode and the contact region. | 05-22-2014 |
20140193941 | METHOD FOR MANUFACTURING SOLAR CELL - A method for manufacturing a solar cell includes forming a first electrode on a substrate, removing a portion of the first electrode to form a first electrode opening, forming a light absorbing layer on the first electrode and in the first electrode opening, and applying a laser beam to the substrate to create an interface reaction between the first electrode and at least the light absorbing layer, thereby removing a portion of the light absorbing layer to form a light absorbing layer opening. | 07-10-2014 |
20140352752 | SOLAR CELL AND METHOD OF MANUFACTURING THE SAME - A solar cell including a substrate and a plurality of electrically connected unit cells on the substrate. A unit cell of the unit cells includes a first electrode, a light absorbing layer, and a second electrode, sequentially stacked. Adjacent unit cells of the unit cells are separated by an isolation region. The isolation region is between the light absorbing layers of the adjacent unit cells and between the second electrodes of the adjacent unit cells. A cross-section of the isolation region has step-shaped patterns in a direction perpendicular to the substrate, and the step-shaped patterns oppose one another. A method of manufacturing the solar cell includes sequentially stacking a first electrode, a light absorbing layer, and a second electrode on a substrate, and forming an isolation region in the light absorbing layer and the second electrode. The forming of the isolation region includes heat-forming a portion of the isolation region followed by mechanical-forming another portion of the isolation region. | 12-04-2014 |
Patent application number | Description | Published |
20110063274 | BACKLIGHT ASSEMBLY AND DISPLAY APPARATUS HAVING THE SAME - In a backlight assembly and a display apparatus having the backlight assembly, a plurality of lamps are housed in a housing having grounded sidewalls, where each of the lamps has at least one bend and series circuits are formed by respective sets of two or more of the bent lamps; where each series connected set of lamps is driven by an AC driving voltage of sufficient magnitude to light the series connected set of lamps, the AC driving voltage being produced by an AC step-up transformer circuit and where each series connected set has its series circuit formed by a lamp-to-lamp connection made through a grounded sidewall of the container. High and low voltage portions of each series connected set of lamps are positioned to reduce electrostatic discharge as between high voltage portions of the series and a nearby grounded sidewall of the container. | 03-17-2011 |
20110249033 | METHOD OF DRIVING BACKLIGHT ASSEMBLY AND DISPLAY APPARATUS HAVING THE SAME - A backlight assembly outputs scan signals having a scanning frequency synchronized with a frame frequency to sequentially drive light emitting blocks providing a light to a display panel. A dimming step of each light emitting block corresponds to one of a plurality of dimming steps in response to local dimming data. A dimming clock having a value obtained by dividing a value obtained by multiplying the scanning frequency and the number is dimming steps by a duty ratio of each scan signal is generated. The dimming step of each light emitting block is counted using the dimming clock, and the counted values are combined with the scan signals to generate dimming signals having a dimming duty ratio corresponding to the dimming step of the light emitting blocks. | 10-13-2011 |
20120229039 | BACKLIGHT UNIT HAVING LIGHT EMITTING DIODE - A backlight unit has a Light Emitting Diode (LED). The backlight unit includes a base member, and a light source unit provided on the base member and including p light source blocks, where p is a natural number equal to or greater than 2. The light source blocks are sequentially arranged to emit light, and each of the light source blocks includes at least one LED package. The LED package includes an LED configured to generate light in response to a driving voltage applied from the outside. A main lead is connected to the LED and configured to apply the driving voltage to the LED. At least one sub lead is separated from the main lead and configured to provide the driving voltage to an adjacent light source block. | 09-13-2012 |
20130038211 | DISPLAY DEVICE AND LED BAR CONNECTION METHOD THEREOF - Disclosed is a display device which includes a display panel, an LED bar configured to output a light to the display panel, and a source printed circuit board including a driver circuit driving the display panel and an LED driver circuit driving the LED bar, wherein the LED bar and the LED driver circuit are connected via a socket disposed at the source printed circuit board. | 02-14-2013 |
Patent application number | Description | Published |
20080219547 | METHOD OF ANALYZING A WAFER SAMPLE - In a method of analyzing a wafer sample, a first defect of a photoresist pattern on the wafer sample having shot regions exposed with related exposure conditions is detected. A first portion of the pattern includes the shot regions exposed with an exposure condition corresponding to a reference exposure condition and a tolerance error range of the reference exposure condition. The first defect repeatedly existing in at least two of the shot regions in a second portion of the pattern is set up as a second defect of the pattern. A first reference image displaying the second defect is obtained. The first defect of the shot regions in the first portion corresponding to the second defect is set up as a third defect corresponding to weak points of the pattern. The exposure conditions of the shot region having no weak points are set up as an exposure margin of an exposure process. | 09-11-2008 |
20100091220 | BACKLIGHT UNIT, METHOD OF OPERATING THE SAME AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE SAME - A backlight unit includes; a light source, an inverter which provides the light source with an input voltage, and a printed circuit board (“PCB”) connected to the light source, wherein the PCB includes a protection circuit which detects an open-lamp-protection voltage which varies according to a change of the input voltage and changes a reference voltage according to the change of the input voltage, wherein the protection circuit turns off the inverter when the detected open-lamp-protection voltage is higher than the changed reference voltage. | 04-15-2010 |
20110101874 | METHOD OF DRIVING LIGHT SOURCE AND DISPLAY APPARATUS FOR PERFORMING THE METHOD - A method of driving a light source apparatus includes inverting a direct current voltage to generate a first alternating current voltage, transforming the first alternating current voltage into a second alternating current voltage having a voltage level that is greater than a voltage level of the first alternating current voltage, compensating a driving alternating current voltage based on the second alternating current voltage to generate a compensated driving alternating current voltage such that a substantially equal current flows through each light emitting string of a plurality of light emitting string included in the light source apparatus, and rectifying the compensated driving alternating current voltage to apply a driving voltage to the light emitting strings. | 05-05-2011 |
20110204812 | TRANSFORMER AND LIQUID CRYSTAL DISPLAY APPARATUS HAVING THE SAME - A transformer and a liquid crystal display apparatus having the transformer are provided. The transformer includes a bobbin having at least one first winding section, at least one second winding section, and at least one core insertion groove formed therein. The transformer also includes at least one coil wound around the first winding section and the second winding section with at least one core inserted into the core insertion groove. | 08-25-2011 |
20120038691 | METHOD OF DRIVING A LIGHT SOURCE AND DISPLAY APPARATUS FOR PERFORMING THE METHOD - A method of driving a light source, which comprises a first light-emitting module including first to k-th light source blocks and disposed at a first edge of a light guide plate, and a second light-emitting module including first to m-th light source blocks and disposed at a second edge of the light guide plate, wherein k and m are natural numbers, includes generating a plurality of duty control signals corresponding to the first to k-th top light source blocks and the first to m-th bottom light source blocks based on an image signal, and selectively generating first to k-th top driving signals and first to m-th bottom driving signals using the plurality of duty control signals based on a three-dimensional image enable signal, where the first to k-th top driving signals drive the first light-emitting module, and the first to m-th bottom driving signals drive the second light-emitting module | 02-16-2012 |
20120146543 | CONNECTOR FOR LIGHT SOURCE MODULE AND BACKLIGHT ASSEMBLY HAVING THE SAME - A connector for a light source module includes a body portion and a terminal portion. The body portion includes a first opening portion and a second opening portion. The first opening portion receives a portion of the light source module. The second opening portion receives a portion of a light source driver which drives the light source module. The terminal portion includes a first terminal and a second terminal. The first terminal is in the first opening portion of the body portion. The second terminal is connected to the first terminal. The second terminal is in the second opening portion of the body portion. | 06-14-2012 |
20130113841 | BACKLIGHT UNIT AND DISPLAY DEVICE INCLUDING THE SAME - A backlight unit includes: a light source unit including at least one light emitting diode (“LED”) string; a driving current controller which is connected to a cathode terminal of the at least one LED string and controls a driving current which flows through the at least one LED string; a feedback unit which generates a feedback signal based on a dimming input signal and a voltage of the cathode terminal of the at least one LED string; and a direct current to direct current (“DC-DC”) converter which generates a driving voltage in response to the feedback signal and provides the driving voltage to the light source unit. | 05-09-2013 |
20140139785 | TWO-WAY DISPLAY DEVICE AND METHOD OF DRIVING THE SAME - A two-way display device includes a transparent display panel, a roll film unit disposed opposite to the transparent display panel and a backlight unit disposed between the roll film unit and the transparent display panel. | 05-22-2014 |
Patent application number | Description | Published |
20090042385 | METHOD OF MANUFACTURING METAL LINE - A method of manufacturing a metal line according to embodiments includes forming an interlayer dielectric layer over a semiconductor substrate. A dielectric layer is formed over the interlayer dielectric layer. A trench may be formed by etching the dielectric layer and the interlayer dielectric layer. A metal material may be disposed over the interlayer dielectric layer including the trench. A first planarization process may be performed on the metal material using the dielectric layer as an etch stop layer. A wet etch process may be performed on the semiconductor substrate subjected the first planarization process. A second planarization process may be performed on interlayer dielectric layer subjected to the wet etch process. | 02-12-2009 |
20090057828 | METAL-INSULATOR-METAL CAPACITOR AND METHOD FOR MANUFACTURING THE SAME - A metal-insulator-metal (MIM) capacitor having fast frequency characteristics and a method for manufacturing the same are disclosed. The disclosed MIM capacitor may include a first intermetal insulating film, a lower metal layer formed over the first intermetal insulating film, a second intermetal insulating film formed around the lower metal layer, and a third intermetal insulating film formed over the lower metal layer. A first-capacitor lower metal layer, a first-capacitor insulating film, a first-capacitor upper metal layer, and a first capping layer may be sequentially formed over a portion of the third intermetal insulating film. A first interlayer insulating film, a fourth intermetal insulating film, and a second interlayer insulating film may be sequentially formed over the third intermetal insulating film including the first capping layer. A second-capacitor lower metal layer may extend through the second interlayer insulating film and the first capping layer such that the second-capacitor lower metal layer is connected to the first-capacitor upper metal layer. A first passivation film may be formed over the second-capacitor lower metal layer. A second-capacitor upper metal layer may be formed over a portion of the first passivation film and extending through the first passivation film in a region where the second-capacitor lower metal layer is arranged such that the second-capacitor upper metal layer is connected to the second-capacitor lower metal layer. Second to fourth passivation films may be sequentially formed over the first passivation film including the second-capacitor upper metal layer. | 03-05-2009 |
20090152678 | CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A capacitor includes a first lower metal layer and an insulating layer on a lower interlayer dielectric layer of a semiconductor substrate; a first upper metal layer aligned on the insulating layer to partially expose it; a first capping layer and an upper interlayer dielectric layer on the insulating layer including the first upper metal layer; a second lower metal layer connected to the first upper metal layer through the upper interlayer dielectric layer and the first capping layer; a second capping layer aligned on the upper interlayer dielectric layer including the second lower metal layer and formed with a hole for partially exposing the second lower metal layer; a pad aligned on the second capping layer and connected to the second lower metal layer; a protective layer on the second capping layer; and a second upper metal layer aligned on the second capping layer. | 06-18-2009 |
20100032792 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes forming an N-well and a P-well formed in a semiconductor substrate. An isolation layer may be formed in the semiconductor substrate. At least one dummy active pattern may be formed in a boundary area between the N-well and the P-well. A salicide blocking layer may be over the upper surface of the at least one dummy active pattern. A non-salicide region may be formed over the upper surface of the at least one dummy active pattern by carrying out a salicide process over the semiconductor substrate provided with the salicide blocking layer. | 02-11-2010 |
Patent application number | Description | Published |
20120211720 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane. | 08-23-2012 |
20120315737 | METHODS OF FORMING VARIABLE RESISTIVE MEMORY DEVICES - A method of forming a variable resistive memory device includes forming a conductive pattern that alternates with a first insulation pattern along a first direction on a substrate that is parallel with a surface of the substrate, forming a preliminary sacrificial pattern on the conductive pattern that contacts a sidewall of the first insulation pattern, etching the conductive pattern using the preliminary sacrificial pattern as an etch masks to form a preliminary bottom electrode pattern, patterning the preliminary sacrificial pattern and the preliminary bottom electrode pattern to form a sacrificial pattern and a bottom electrode pattern that each include at least two portions which are separated from each other along a second direction intersecting the first direction, and replacing the sacrificial pattern with a variable resistive pattern. | 12-13-2012 |
20130105757 | PHASE CHANGE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME | 05-02-2013 |
20140113429 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane. | 04-24-2014 |
20140308797 | METHODS OF FORMING VARIABLE RESISTIVE MEMORY DEVICES - A method of forming a variable resistive memory device includes forming a conductive pattern that alternates with a first insulation pattern along a first direction on a substrate that is parallel with a surface of the substrate, forming a preliminary sacrificial pattern on the conductive pattern that contacts a sidewall of the first insulation pattern, etching the conductive pattern using the preliminary sacrificial pattern as an etch masks to form a preliminary bottom electrode pattern, patterning the preliminary sacrificial pattern and the preliminary bottom electrode pattern to form a sacrificial pattern and a bottom electrode pattern that each include at least two portions which are separated from each other along a second direction intersecting the first direction, and replacing the sacrificial pattern with a variable resistive pattern. | 10-16-2014 |
20150028399 | Semiconductor Devices and Methods of Manufacturing the Same - Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time. | 01-29-2015 |
Patent application number | Description | Published |
20120081274 | THIN FILM TRANSISTOR ARRAY PANEL, LIQUID CRYSTAL DISPLAY, AND METHOD TO REPAIR THE SAME - The present invention relates to a thin film transistor array panel, a liquid crystal display, and a method capable of reducing an effect on neighboring pixels in a process of repairing a pixel defect. The thin film transistor array panel may include: a thin film transistor connected to a gate line and a data line to define a pixel area; a pixel electrode formed in the pixel area and connected to the thin film transistor; and a storage electrode including a first portion overlapping the data line between two adjacent gate lines. The storage electrode may also include a second portion connected to the first portion and enclosing an edge of the pixel area except for a region where the first portion is formed. The storage electrode may be branched between pixel electrodes respectively formed in two adjacent pixel areas. | 04-05-2012 |
20120206437 | DISPLAY APPARATUS - A display apparatus includes a substrate, gate lines disposed on the substrate, data lines extending across the gate lines, and pixels connected to the gate lines and the data lines. The pixels arranged in a matrix of rows and columns. The pixels disposed in the same columns are alternately connected to data lines disposed to the left or right sides of the column. The pixels may be disposed in different display areas of the substrate. Adjacent pixels in the same columns but in different display areas may be connected to the same data line. | 08-16-2012 |
20130033417 | SCAN DRIVER, DISPLAY DEVICE HAVING THE SAME AND METHOD OF DRIVING A DISPLAY DEVICE - A scan driver drives a display device having a plurality of gate lines transferring scan signals, and a plurality of source lines transferring data signals. The scan driver includes a shift register and a multiple signal applying unit. The shift register includes a plurality of cascade-connected stages, each stage having an output terminal electrically connected to a respective one of the plurality of gate lines. The multiple signal applying unit applies a sub scan signal and a main scan signal. The sub scan signal and the main scan signal sequentially activate each of the plurality of gate lines. Therefore, the scan lines receive the scan signal twice, so that the liquid crystal capacitors electrically connected to the gate lines receive the data voltage twice. As a result, even though the time for charging the liquid crystal capacitors may be reduced, the liquid crystal capacitors may be fully charged to enhance display quality. | 02-07-2013 |
20130113772 | DISPLAY PANEL - A display panel includes a gate driver connected to a gate line, where the gate driver includes a plurality of stages, where each of the stages includes at least one dual gate thin film transistor having a first control terminal and a second control terminal, and where each of the stages receives a clock signal, a first low voltage, a second low voltage, at least one transmission signal of previous stages, at least two transmission signals of subsequent stages and an output control signal from one of the stages to output a gate voltage including a gate-on voltage and a gate-off voltage. | 05-09-2013 |
20130147698 | DISPLAY APPARATUS - A display apparatus includes a first sub-pixel and a second sub-pixel. The first sub-pixel and the second sub-pixel are electrically and respectively connected to a first gate line and a second gate line adjacent to each other and are electrically connected to a data line. The display apparatus further includes a connection line disposed between sub-pixel electrodes of the first and second sub-pixels. The connection line has two ends connected to the data line and serves as an additional or alternative path for transmitting a data signal that is transmitted by the data line. | 06-13-2013 |
20130215350 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF REPAIRING BAD PIXELS THEREIN - A liquid crystal display device and a method of repairing bad pixels thereof, in which the bad pixels can be efficiently and easily repaired, includes a first insulating substrate, a gate wiring and a storage wiring arranged substantially parallel to each other in a first direction on the first insulating substrate, a data wiring intersecting the gate and storage wirings in an insulated manner and arranged substantially in a second direction, and a pixel electrode formed on a pixel area defined by the gate and data wirings. The storage wiring includes a horizontal portion arranged substantially in the first direction and at least a part of which does not overlap the pixel electrode, and a vertical portion branching off substantially in the second direction from the horizontal portion and overlapping the data wiring. | 08-22-2013 |
20130335667 | THIN FILM TRANSISTOR ARRAY PANEL, LIQUID CRYSTAL DISPLAY, AND METHOD TO REPAIR THE SAME - The present invention relates to a thin film transistor array panel, a liquid crystal display, and a method capable of reducing an effect on neighboring pixels in a process of repairing a pixel defect. The thin film transistor array panel may include: a thin film transistor connected to a gate line and a data line to define a pixel area; a pixel electrode formed in the pixel area and connected to the thin film transistor; and a storage electrode including a first portion overlapping the data line between two adjacent gate lines. The storage electrode may also include a second portion connected to the first portion and enclosing an edge of the pixel area except for a region where the first portion is formed. The storage electrode may be branched between pixel electrodes respectively formed in two adjacent pixel areas. | 12-19-2013 |
20140139418 | LIQUID CRYSTAL DISPLAY - A liquid crystal display (LCD) includes a substrate; first and second pixel rows formed on the substrate and including a plurality of pixels; a first gate line extending in a row direction on the substrate and connected with the first pixel row; a second gate line extending in the row direction on the substrate, connected with the first pixel row; a third gate line extending in the row direction on the substrate, connected with the second pixel row, and adjacent to the second gate line; a fourth gate line extending in the row direction on the substrate, connected with the second pixel row; a plurality of data lines extending in a column direction on the substrate, wherein each of the data lines are disposed every two of the pixels; a first gate driver connected with the first and fourth gate lines and applying gate signals to the first and fourth gate lines; and a second gate driver connected with the second and third gate lines and applying gate signals to the second and third gate lines. | 05-22-2014 |
Patent application number | Description | Published |
20110178091 | ARYLPIPERAZINE-CONTAINING PYRROLE 3-CARBOXAMIDE DERIVATIVES FOR TREATING DEPRESSIVE DISORDERS - The present invention relates to novel arylpiperazine-containing pyrrole 3-carboxamide derivatives of formula (I) or a pharmaceutically acceptable salt thereof which is useful for preventing or treating depressive disorders. The present invention also provides a method for preparing the arylpiperazine-containing pyrrole 3-carboxamide derivatives or the pharmaceutically acceptable salt thereof, a pharmaceutical composition containing same, and a method for preventing or treating depressive disorders. | 07-21-2011 |
20120101051 | NOVEL C-ARYL GLUCOSIDE SGLT2 INHIBITORS AND PHARMACEUTICAL COMPOSITIONS COMPRISING SAME - A novel C-aryl glucoside compound, or a pharmaceutically acceptable salt or a prodrug thereof having an inhibitory activity against sodium-dependent glucose cotransporter 2 (SGLT2) being present in the intestine and kidney; and a pharmaceutical composition comprising the same as an active ingredient, which is useful for preventing or treating metabolic disorders, particularly, diabetes, are provided. | 04-26-2012 |
20120115881 | NOVEL ARYLPIPERAZINE-CONTAINING IMIDAZOLE 4-CARBOXAMIDE DERIVATIVES AND PHARMACEUTICAL COMPOSITION COMPRISING SAME - A novel arylpiperazine-containing imidazole 4-carboxamide derivative or a pharmaceutically acceptable salt thereof, and a pharmaceutical composition comprising the same as an active ingredient for preventing or treating a depressive disorder are provided. | 05-10-2012 |
20120232090 | ARYLPIPERAZINE-CONTAINING PURINE DERIVATIVES AND USES THEREOF - A novel arylpiperazine-containing purine derivatives and a pharmaceutical composition comprising the same as an active ingredient, which are useful for preventing or treating depressive disorders, are provided. | 09-13-2012 |
20130090298 | Thiazole Derivatives as SGLT2 Inhibitors and Pharmaceutical Composition Comprising Same - The present invention relates to a novel compound with thiazole ring having an inhibitory activity against sodium-dependent glucose cotransporter 2 (SGLT2) being present in the intestine and kidney, and a pharmaceutical composition comprising the same as an active ingredient, which is useful for preventing or treating metabolic disorders, particularly diabetes. | 04-11-2013 |
Patent application number | Description | Published |
20080205113 | Inter-transmission multi memory chip, system including the same and associated method - A multi memory chip stacked on a multi core CPU includes a plurality of memories, each memory corresponding to a CPU core from among the CPU cores and being configured to directly transmit data between the other memories of the multi memory chip. | 08-28-2008 |
20090039492 | STACKED MEMORY DEVICE - A semiconductor memory device includes a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip. Each one of the stacked plurality of interposer chips includes a central portion having bond pads seating the corresponding memory device and a peripheral portion having a plurality of through silicon vias (TSVs). The respective pluralities of TSVs for adjacent interposer chips in the stacked plurality of interposer chips are connected via vertical connection elements to form multiple internal signal paths communicating write data from and read data to the buffer chip from respective memory chips. | 02-12-2009 |
20090052218 | SEMICONDUCTOR PACKAGE HAVING MEMORY DEVICES STACKED ON LOGIC DEVICE - A semiconductor package includes a base substrate, a logic device with a serializer/deserializer (SerDes), a plurality of odd memory devices disposed on a lower surface of the logic device and operatively stack-connected with the SerDes, and a plurality of even memory devices disposed on an upper surface of the logic device and operatively stack-connected with the SerDes, such that the plurality of odd memory devices and the plurality of even memory devices are connected in parallel by the SerDes. | 02-26-2009 |
20090091962 | MULTI-CHIP MEMORY DEVICE WITH STACKED MEMORY CHIPS, METHOD OF STACKING MEMORY CHIPS, AND METHOD OF CONTROLLING OPERATION OF MULTI-CHIP PACKAGE MEMORY - A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each bank of each memory chip in the stacked plurality of memory chips is commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips. | 04-09-2009 |
20090168571 | DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF DETERMINING REFRESH CYCLE THEREOF - Provided are a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle of the dynamic random access memory device. The method includes: selecting one or more monitoring bits during first through n-th self refresh cycles, where “n” is a natural number equal to or greater than one; detecting whether the monitoring bits have errors during (n+1)-th through m-th self refresh cycles, where “m” is a natural number equal to or greater than n+1; and adjusting an (m+1)-th self refresh cycle according to whether the monitoring bits have errors. | 07-02-2009 |
20110044084 | MULTI-CHIP MEMORY DEVICE WITH STACKED MEMORY CHIPS, METHOD OF STACKING MEMORY CHIPS, AND METHOD OF CONTROLLING OPERATION OF MULTI-CHIP PACKAGE MEMORY - A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each bank of each memory chip in the stacked plurality of memory chips is commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips. | 02-24-2011 |
20110057310 | SEMICONDUCTOR PACKAGE HAVING MEMORY DEVICES STACKED ON LOGIC DEVICE - A semiconductor package includes a base substrate, a logic device with a serializer/deserializer (SerDes), a plurality of odd memory devices disposed on a lower surface of the logic device and operatively stack-connected with the SerDes, and a plurality of even memory devices disposed on an upper surface of the logic device and operatively stack-connected with the SerDes, such that the plurality of odd memory devices and the plurality of even memory devices are connected in parallel by the SerDes. | 03-10-2011 |
20110122716 | DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF DETERMINING REFRESH CYCLE THEREOF - Provided are a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle of the dynamic random access memory device. The method includes: selecting one or more monitoring bits during first through n-th self refresh cycles, where “n” is a natural number equal to or greater than one; detecting whether the monitoring bits have errors during (n+1)-th through m-th self refresh cycles, where “m” is a natural number equal to or greater than n+1; and adjusting an (m+1)-th self refresh cycle according to whether the monitoring bits have errors. | 05-26-2011 |
Patent application number | Description | Published |
20100051082 | THIN FILM SOLAR CELL MODULE AND METHOD OF MANUFACTURING THE SAME - A thin film solar cell module includes a front substrate; a plurality of thin film solar cells disposed on the front substrate; a rear substrate disposed on the thin film solar cells; a plurality of inter-connection terminals electrically connected to the thin film solar cells, respectively, and exposed to an exterior surface of at least one of the front and rear substrates; and a connector electrically connecting the inter-connection terminals in a series or parallel configuration. | 03-04-2010 |
20120122262 | THIN FILM SOLAR CELL MODULE AND METHOD OF MANUFACTURING THE SAME - A thin film solar cell module includes a front substrate; a plurality of thin film solar cells disposed on the front substrate; a rear substrate disposed on the thin film solar cells; a plurality of inter-connection terminals electrically connected to the thin film solar cells, respectively, and exposed to an exterior surface of at least one of the front and rear substrates; and a connector electrically connecting the inter-connection terminals in a series or parallel configuration. | 05-17-2012 |
20140069479 | Photoelectric Device Module and Manufacturing Method Thereof - A solar cell module according to the present invention includes photoelectric converting cells, interconnect wiring, and a bus bar, wherein the interconnect wiring is attached by a conductive adhesive layer, and the bus bar is attached by an insulating adhesive layer. A method for manufacturing the solar cell module includes attaching the interconnect wiring and the bus bar by the conductive adhesive layer and the insulating adhesive layer, and according to the method, a solar cell module with excellent characteristics can be manufactured through a simple and inexpensive method. | 03-13-2014 |
20150059833 | PHOTOELECTRIC PANEL ASSEMBLY - A photoelectric panel assembly includes a photoelectric panel, a support rail coupled to a rear surface of the photoelectric panel, the support rail including a base portion parallel to and spaced apart from the photoelectric panel, flange portions parallel to and adhered to the photoelectric panel, slope portions between the base portion and respective ones of the flange portions, and rounded portions between the base portion and the slope portions and between the slope portions and the flange portions. | 03-05-2015 |
Patent application number | Description | Published |
20090131684 | Photoacid generator, chemically amplified resist composition including the same, and associated methods - A photoacid generator represented by Formula 1 or Formula 2: | 05-21-2009 |
20100093172 | METHOD OF FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE - A method of forming fine patterns of a semiconductor device includes forming a plurality of first mask patterns on a substrate such that the plurality of first mask patterns are separated from one another by a space located therebetween, in a direction parallel to a main surface of the substrate, forming a plurality of capping films formed of a first material having a first solubility in a solvent on sidewalls and a top surface of the plurality of first mask patterns. The method further includes forming a second mask layer formed of a second material having a second solubility in the solvent, which is less than the first solubility, so as to fill the space located between the plurality of first mask patterns, and forming a plurality of second mask patterns corresponding to residual portions of the second mask layer which remain in the space located between the plurality of first mask patterns, after removing the plurality of capping films and a portion of the second mask layer using the solvent. | 04-15-2010 |
20110027993 | METHODS OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming fine patterns of a semiconductor device is provided. The method includes forming plural preliminary first mask patterns, which are spaced apart from each other by a first distance in a direction parallel to a surface of a substrate, on the substrate; forming an acid solution layer on the substrate to cover the plural preliminary first mask patterns; forming plural first mask patterns which are spaced apart from each other by a second distance larger than the first distance, of which upper and side portions are surrounded by acid diffusion regions having first solubility; exposing the first acid diffusion regions by removing the acid solution layer; forming a second mask layer having second solubility lower than the first solubility in spaces between the acid diffusion regions; and forming plural second mask patterns located between the plural first mask patterns, respectively, by removing the acid diffusion regions by the dissolvent. | 02-03-2011 |
20110053362 | METHOD OF FORMING A MASK PATTERN, METHOD OF FORMING A MINUTE PATTERN, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - A method of forming a mask pattern, a method of forming a minute pattern, and a method of manufacturing a semiconductor device using the same, the method of forming the mask pattern including forming first mask patterns on a substrate; forming first preliminary capping layers on the first mask patterns; irradiating energy to the first preliminary capping patterns to form second preliminary capping layers ionically bonded with the first mask patterns; applying an acid to the second preliminary capping layers to form capping layers; forming a second mask layer between the capping layers, the second mask layer having a solubility lower than that of the capping layers; and removing the capping layers to form second mask patterns. | 03-03-2011 |
20110244689 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first mask pattern on a substrate by using a material including a polymer having a protection group de-protectable by an acid, the first mask pattern having a plurality of holes; forming a capping layer on an exposed surface of the first mask pattern, the capping layer including an acid source; diffusing the acid source into the first mask pattern so that the protection group becomes de-protectable from the polymer in the first mask pattern; forming a second mask layer on the capping layer, the second mask layer separate from the first mask pattern and filling the plurality of holes in the first mask pattern; and forming a plurality of second mask patterns in the plurality of holes by removing the capping layer and the first mask pattern. | 10-06-2011 |
20110275020 | Methods Of Forming Photoresist Patterns - Methods of forming photoresist patterns may include forming a photoresist layer on a substrate, exposing the photoresist layer using an exposure mask, forming a preliminary pattern by developing the exposed photoresist layer and treating a surface of the preliminary pattern using a treatment agent that includes a coating polymer. | 11-10-2011 |
20120028434 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING ACID DIFFUSION - A method of manufacturing a semiconductor device includes forming a resist pattern on a first region on a substrate, bringing a descum solution including an acid source into contact with the resist pattern and with a second region of the substrate, decomposing resist residues remaining on the second region of the substrate by using acid obtained from the acid source in the descum solution and removing the decomposed resist residues and the descum solution from the substrate. | 02-02-2012 |
20130034965 | METHODS OF FORMING FINE PATTERNS USING DRY ETCH-BACK PROCESSES - In a method of fabricating patterns in an integrated circuit device, first mask patterns, sacrificial patterns, and second mask patterns are formed on a target layer such that the sacrificial patterns are provided between sidewalls of adjacent ones of the first and second mask patterns. The sacrificial patterns between the sidewalls of the adjacent ones of the first and second mask patterns are selectively removed using a dry etch-back process, and the target layer is patterned using the first and second mask patterns as a mask. | 02-07-2013 |
20130040448 | METHODS OF FORMING METAL OR METAL NITRIDE PATTERNS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - In a method of forming a metal or metal nitride pattern, a metal or metal nitride layer is formed on a substrate, and a photoresist pattern is formed on the metal or metal nitride layer. An over-coating composition is coated on the metal or metal nitride layer and on the photoresist pattern to form a capping layer on the photoresist pattern. The over-coating composition includes a polymer having amine groups as a side chain or a branch and a solvent. A remaining portion of the over-coating composition is removed by washing with a hydrophilic solution. The metal or metal nitride layer is partially removed using the capping layer and the photoresist pattern as an etching mask. | 02-14-2013 |
20140124834 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is disclosed comprising the steps of: providing a substrate having a first region, a second region and a plurality of gate electrodes which are formed on the first and second regions of the substrate; forming a mask film to expose the first region of the substrate while covering the second region of the substrate, such that the mask film has a negative lateral profile at a boundary between the first and second regions of the substrate; forming sigma trenches in the first region of the substrate by etching the first region of the substrate using the mask film and the gate electrodes as a mask; and forming an epitaxial layer in each of the sigma trenches. | 05-08-2014 |
Patent application number | Description | Published |
20110086262 | RECHARGEABLE BATTERY - A rechargeable battery is disclosed. The rechargeable battery comprises: a central electrode portion comprising a positive electrode, a negative electrode and a separator; a first electrode portion extending from a first end of the central electrode portion; a second electrode portion extending from a second end of the central electrode portion opposite the first end; a central case enclosing the central electrode portion; a first electrode case enclosing the first electrode portion, wherein the first electrode case is coupled to the central case such that an overlapping part of the first electrode case encloses a part of the central electrode portion at the first end, and the central case encloses the overlapping part of the first electrode case; and a second electrode case enclosing the second electrode portion, wherein the second electrode case is coupled to the central case such that an overlapping part of the second electrode case encloses a part of the central electrode portion at the second end, and the central case encloses the overlapping part of the second electrode case. | 04-14-2011 |
20110123857 | RECHARGEABLE BATTERY - A rechargeable battery includes an electrode assembly having a plurality of first electrodes each including a first coated region coated with a first active material and a first uncoated region having a first alignment opening and a second alignment opening, a plurality of second electrodes each including a second coated region coated with a second active material and a second uncoated region having a third alignment opening and a fourth alignment opening, a separator between each first coated region and each second coated region; and a case housing the electrode assembly, wherein the first alignment openings are substantially aligned with each other, the second alignment openings are substantially aligned with each other, the third alignment openings are substantially aligned with each other, and the fourth alignment openings are substantially aligned with each other. | 05-26-2011 |
20110151307 | RECHARGEABLE BATTERY - A rechargeable battery comprises: an electrode assembly comprising a plurality of positive electrode plates, a plurality of negative electrode plates, and a plurality of separators; and a case enclosing the electrode assembly; wherein each separator in the plurality of separators comprises a central portion facing at least one of the positive and negative electrode plates, and an extended portion that extends past the positive and negative electrode plates, and wherein each of the extended portion comprises an adhered portion that is adhered to adjacent extended portions. | 06-23-2011 |
Patent application number | Description | Published |
20120149144 | METHOD FOR MANUFACTURING SOLAR CELL - A method for manufacturing a solar cell is presented. The method includes: forming an amorphous silicon layer on a first surface of a light absorbing layer; doping the amorphous silicon layer with a dopant; forming a dopant layer by diffusing the dopant into the amorphous silicon layer with a laser; forming a semiconductor layer by removing the dopant that remains outside the dopant layer; etching the surface of the semiconductor layer by using an etchant; forming a first electrode on the semiconductor layer; and forming a second electrode on a second surface of the light absorbing layer. | 06-14-2012 |
20120247548 | SOLAR CELL AND METHOD OF FABRICATING THE SAME - A method of fabricating a solar cell includes forming an emitter layer of a second conductive type on a front surface and a back surface of a substrate of a first conductive type opposite to the second conductive type, forming an anti-reflection layer on the front surface of the substrate, partially removing the anti-reflection layer and the emitter layer to form an isolation groove dividing the emitter layer into a plurality of regions, removing a portion of the emitter layer formed on the back surface of the substrate, and forming a passivation layer covering the isolation groove and the back surface of the substrate. | 10-04-2012 |
20120295391 | METHOD OF MANUFACTURING A SOLAR CELL - A method of manufacturing a solar cell includes preparing a base substrate having a first conductive type; diffusing an impurity having a second conductive type (opposite the first conductive type) into the base substrate to form an emitter layer having a first impurity concentration on the base substrate and a by-product layer on the emitter layer; irradiating a laser beam onto the emitter layer corresponding to a first region of the base substrate to form a front contact portion having a second impurity concentration higher than the first impurity concentration; irradiating the laser beam onto the by-product layer to remove the by-product layer corresponding to the first region; removing the by-product layer from an area outside of the first region; forming an anti-reflection layer on the base substrate; forming a front electrode on the anti-reflection layer corresponding to the first region; and forming a back electrode on the base substrate. | 11-22-2012 |
20130125971 | PHOTOVOLTAIC DEVICE AND METHOD OF MANUFACTURING THE SAME - Method of manufacturing a photovoltaic device and a photovoltaic device manufactured by using the method. The method includes forming a first conductive-type semiconductor layer using a first impurity on a semiconductor substrate, performing doping on a region of the first conductive-type semiconductor layer using a laser such that the region of the first conductive-type semiconductor layer has a higher concentration of the first impurity than a remaining portion of the first conductive-type semiconductor layer, performing edge isolation to form a groove portion at an edge portion of a rear surface of the semiconductor substrate, forming an antireflection layer on a front surface of the semiconductor substrate, forming a first metal electrode on the front surface of the semiconductor substrate, and forming a second metal electrode and a second conductive-type semiconductor layer including a second impurity that is different from the first impurity, on the rear surface of the semiconductor substrate. | 05-23-2013 |
20140130854 | PHOTOELECTRIC DEVICE AND THE MANUFACTURING METHOD THEREOF - A photoelectric device includes: a semiconductor substrate including monocrystalline silicon and has first and second surfaces that are opposite to each other; a doping unit formed on the first surface of the semiconductor substrate; and an insulating layer that is formed between the doping unit and the second surface of the semiconductor substrate, wherein the doping unit includes: a first semiconductor layer including a first dopant doped in the monocrystalline silicon; and a second semiconductor layer including a second dopant doped in the monocrystalline silicon. | 05-15-2014 |
20150020882 | SEALING MEMBER AND SOLAR CELL INCLUDING THE SAME - A sealing member according to an exemplary embodiment of the present invention includes a first plate having a predetermined width with a plate shape, and a second plate with a plate shape connected to both ends of the first plate, wherein the first plate and the second plate have the same plate shape and form a closed line. | 01-22-2015 |