Patent application number | Description | Published |
20090129392 | MULTIPLE QUEUE PAIR ACCESS WITH A SINGLE DOORBELL - A method for controlling access by processes running on a host device to a communication network includes assigning to each of the processes a respective doorbell address on a network interface adapter that couples the host device to the network and allocating instances of a communication service on the network, to be provided via the adapter, to the processes. Upon receiving a request submitted by a given one of the processes to its respective doorbell address to access one of the allocated service instances, the adapter conveys the data over the network using the specified instance of the service, subject to verifying, based on the doorbell address to which the request was submitted, that the specified instance was allocated to the given process. | 05-21-2009 |
20090201926 | FIBRE CHANNEL PROCESSING BY A HOST CHANNEL ADAPTER - A method for data storage includes mapping a queue pair (QP) of a channel adapter to a specified Fibre Channel (FC) exchange for communication with a storage device. Upon receiving at the channel adapter from a host computer a storage command directed to the storage device, the storage command is executed by transmitting data packets over a switched network from the channel adapter to the storage device using the specified exchange and performing a remote direct memory access (RDMA) operation on the channel adapter using the mapped QP. | 08-13-2009 |
20100138840 | SYSTEM AND METHOD FOR ACCELERATING INPUT/OUTPUT ACCESS OPERATION ON A VIRTUAL MACHINE - A system and method for accelerating input/output (IO) access operation on a virtual machine, The method comprises providing a smart IO device that includes an unrestricted command queue (CQ) and a plurality of restricted CQs and allowing a guest domain to directly configure and control IO resources through a respective restricted CQ, the IO resources allocated to the guest domain. In preferred embodiments, the allocation of IO resources to each guest domain is performed by a privileged virtual switching element. In some embodiments, the smart IO device is a HCA and the privileged virtual switching element is a Hypervisor. | 06-03-2010 |
20100189206 | Precise Clock Synchronization - A method for clock synchronization includes computing an offset value between a local clock time of a real-time clock circuit and a reference clock time, and loading the offset value into a register that is associated with the real-time clock circuit. The local clock time is then summed with the value in the register so as to give an adjusted value of the local clock time that is synchronized with the reference clock. | 07-29-2010 |
20100274876 | NETWORK INTERFACE DEVICE WITH MEMORY MANAGEMENT CAPABILITIES - An input/output (I/O) device includes a host interface for connection to a host device having a memory and a network interface, which is configured to receive, over a network, data packets associated with I/O operations directed to specified virtual addresses in the memory. Packet processing hardware is configured to translate the virtual addresses into physical addresses and to perform the I/O operations using the physical addresses, and upon an occurrence of a page fault in translating one of the virtual addresses, to transmit a response packet over the network to a source of the data packets so as to cause the source to refrain from transmitting further data packets while the page fault is serviced. | 10-28-2010 |
20110010557 | CONTROL MESSAGE SIGNATURE FOR DEVICE CONTROL - A method of controlling a peripheral device includes generating, in a host processor, a control message for transmission to the peripheral device, and calculating a signature for the control message. The control message and the signature are written to an address in a system memory of the host processor, and the peripheral device is notified of the address, so as to cause the device to read the control message and the signature from the system memory. | 01-13-2011 |
20110029847 | PROCESSING OF DATA INTEGRITY FIELD - A network communication device includes a host interface, which is coupled to communicate with a host processor, having a memory, so as to receive a work request to convey one or more data blocks over a network. The work request specifies a memory region of a given data size, and at least one data integrity field (DIF), having a given field size, is associated with the data blocks. Network interface circuitry is configured to execute an input/output (I/O) data transfer operation responsively to the work request so as to transfer to or from the memory a quantity of data that differs from the data size of the memory region by a multiple of the field size, while adding the at least one DIF to the transferred data or removing the at least one DIF from the transferred data. | 02-03-2011 |
20110058571 | DATA SWITCH WITH SHARED PORT BUFFERS - A communication apparatus includes a plurality of switch ports, each switch port including one or more port buffers for buffering data that traverses the switch port. A switch fabric is coupled to transfer the data between the switch ports. A switch control unit is configured to reassign at least one port buffer of a given switch port to buffer a part of the data that does not enter or exit the apparatus via the given switch port, and to cause the switch fabric to forward the part of the data to a destination switch port via the at least one reassigned port buffer. | 03-10-2011 |
20110083064 | PROCESSING OF BLOCK AND TRANSACTION SIGNATURES - A network communication device includes a host interface, which is coupled to communicate with a host processor, having a host memory, so as to receive a work request to execute a transaction in which a plurality of data blocks are to be transferred over a packet network. Processing circuitry is configured to process multiple data packets so as to execute the transaction, each data packet in the transaction containing a portion of the data blocks, and the multiple data packets including at least first and last packets, which respectively contain the first and last data blocks of the transaction. The processing circuitry is configured to compute a transaction signature over the data blocks while processing the data packets so that at least the first data block passes out of the network communication device through one of the interfaces before computation of the transaction signature is completed. | 04-07-2011 |
20110096668 | HIGH-PERFORMANCE ADAPTIVE ROUTING - A method for communication includes routing a first packet, which belongs to a given packet flow, over a first routing path through a communication network. A second packet, which follows the first packet in the given packet flow, is routed using a time-bounded Adaptive Routing (AR) mode, by evaluating a time gap between the first and second packets, routing the second packet over the first routing path if the time gap does not exceed a predefined threshold, and, if the time gap exceeds the predefined threshold, selecting a second routing path through the communication network that is potentially different from the first routing path, and routing the second packet over the second routing path. | 04-28-2011 |
20110116512 | Dynamically-Connected Transport Service - A method of communication includes receiving, in a network interface device, first and second requests from an initiator process running on an initiator host to transmit, respectively, first and second data to first and second target processes running on one or more target nodes, via a packet network. A single dynamically-connected initiator context is allocated for serving both the first and second requests. A first connect packet referencing the dynamically-connected (DC) initiator context is directed to the first target process so as to open a first dynamic connection with the first target process, followed by transmission of the first data over the first dynamic connection. The first dynamic connection is closed after the transmission of the first data, and a second connect packet is transmitted so as to open a second dynamic connection with the second target process, followed by transmission of the second data. | 05-19-2011 |
20120071011 | ADAPTER FOR HIGH-SPEED ETHERNET - An adapter includes a mechanical frame, which is configured to be inserted into a SFP-type receptacle and contains a socket for receiving a plug of a twisted-pair-type cable. First electrical terminals, held by the mechanical frame, are configured to mate with a connector in the receptacle. Second electrical terminals, held within the socket, are configured to mate with electrical connections of the plug. Circuitry connects the first and second electrical terminals so as to enable interoperation of the plug with the receptacle. | 03-22-2012 |
20120082164 | Cell-Based Link-Level Retry Scheme - A method for communication includes receiving a packet at a first node for transmission over a link to a second node. The data in the packet is divided into a sequence of cells of a predetermined data size. The cells have respective sequence numbers. The cells are transmitted in sequence over the link, while storing the transmitted cells in a buffer at the first node. The first node receives acknowledgments indicating the respective sequence numbers of the transmitted cells that were received at the second node. Upon receiving an indication at the first node that a transmitted cell having a given sequence number was not properly received at the second node, the stored cells are retransmitted from the buffer starting from the cell with the given sequence number. | 04-05-2012 |
20120174102 | SYSTEM AND METHOD FOR ACCELERATING INPUT/OUTPUT ACCESS OPERATION ON A VIRTUAL MACHINE - A system and method for accelerating input/output (IO) access operation on a virtual machine, The method comprises providing a smart IO device that includes an unrestricted command queue (CQ) and a plurality of restricted CQs and allowing a guest domain to directly configure and control IO resources through a respective restricted CQ, the IO resources allocated to the guest domain. In preferred embodiments, the allocation of IO resources to each guest domain is performed by a privileged virtual switching element. In some embodiments, the smart IO device is a HCA and the privileged virtual switching element is a Hypervisor. | 07-05-2012 |
20120246535 | PROCESSING OF BLOCK AND TRANSACTION SIGNATURES - A network communication device includes a host interface, which is coupled to communicate with a host processor, having a host memory, so as to receive a work request to execute a transaction in which a plurality of data blocks are to be transferred over a packet network. Processing circuitry is configured to process multiple data packets so as to execute the transaction, each data packet in the transaction containing a portion of the data blocks, and the multiple data packets including at least first and last packets, which respectively contain the first and last data blocks of the transaction. The processing circuitry is configured to compute a transaction signature over the data blocks while processing the data packets so that at least the first data block passes out of the network communication device through one of the interfaces before computation of the transaction signature is completed. | 09-27-2012 |
20120314706 | PACKET SWITCHING BASED ON GLOBAL IDENTIFIER - A communication method in a network operating in accordance with a standard that allocates a given number of bits m for layer-2 addressing of nodes in the network. The method includes accepting at a layer-2 switch in the network an assignment to one or more nodes in the network of respective layer-2 extended addresses, each including n=m+k bits, k>0. A given data packet is received at the switch for forwarding. The given data packet includes a layer-2 destination address and a layer-3 destination address in accordance with the standard. The layer-3 destination address includes t bits, t≧k. The given data packet is forwarded from the switch to one of the nodes by reading from the given data packet and combining the layer-2 destination address and k bits from the layer-3 destination address so as to reconstruct the n bits of the extended layer-2 address of the one of the nodes. | 12-13-2012 |
20130042236 | VIRTUALIZATION OF INTERRUPTS - A method for computing includes running a plurality of virtual machines on a computer having one or more cores and a memory. Respective interrupt addresses in the memory are assigned to the virtual machines. Upon occurrence on a device connected to the computer of an event pertaining to a given virtual machine during a period in which the given virtual machine is swapped out of operation, an interrupt message is written from the device to a respective interrupt address that is assigned to the given virtual machine in the memory. Upon activating the given virtual machine on a given core after writing of the interrupt message, a context of the given virtual machine is copied from the memory to the given core, and a hardware interrupt is automatically raised on the given core responsively to the interrupt message in the memory. | 02-14-2013 |
20130042242 | Interrupt Handling in a Virtual Machine Environment - A method for computing includes running a plurality of virtual machines on a computer having one or more cores and a memory. Upon occurrence of an event pertaining to a given virtual machine during a period in which the given virtual machine is unable to receive an interrupt, an interrupt message is written to a pre-assigned interrupt address in the memory. When the given virtual machine is able to receive the interrupt, after writing of the interrupt message, a context of the given virtual machine is copied from the memory to a given core on which the given virtual machine is running, and a hardware interrupt is automatically raised on the given core responsively to the interrupt message in the memory. | 02-14-2013 |
20130067193 | NETWORK INTERFACE CONTROLLER WITH FLEXIBLE MEMORY HANDLING - An input/output (I/O) device includes a host interface for connection to a host device having a memory, and a network interface, which is configured to transmit and receive, over a network, data packets associated with I/O operations directed to specified virtual addresses in the memory. Processing circuitry is configured to translate the virtual addresses into physical addresses using memory keys provided in conjunction with the I/O operations and to perform the I/O operations by accessing the physical addresses in the memory. At least one of the memory keys is an indirect memory key, which points to multiple direct memory keys, corresponding to multiple respective ranges of the virtual addresses, such that an I/O operation referencing the indirect memory key can cause the processing circuitry to access the memory in at least two of the multiple respective ranges. | 03-14-2013 |
20130077489 | CREDIT-BASED FLOW CONTROL FOR ETHERNET - A method for communication includes sending a pause frame from a first node to a second node over a communication link between the nodes. In response to the pause frame, one or more data frames are immediately transmitted from the second node to the first node upon receipt of the pause frame at the second node. | 03-28-2013 |
20130103777 | NETWORK INTERFACE CONTROLLER WITH CIRCULAR RECEIVE BUFFER - A method for communication includes allocating in a memory of a host device a contiguous, cyclical set of buffers for use by a transport service instance on a network interface controller (NIC). First and second indices point respectively to a first buffer in the set to which the NIC is to write and a second buffer in the set from which a client process running on the host device is to read. Upon receiving at the NIC a message directed to the transport service instance and containing data to be pushed to the memory, the data are written to the first buffer that is pointed to by the first index, and the first index is advanced cyclically through the set. The second index is advanced cyclically through the set when the data in the second buffer have been read by the client process. | 04-25-2013 |
20130315237 | Prioritized Handling of Incoming Packets by a Network Interface Controller - A network interface controller includes a host interface, which is configured to be coupled to a host processor having a host memory. A network interface is configured to receive data packets from a network, each data packet including a header, which includes header fields, and a payload including data. Packet processing circuitry is configured to process one or more of the header fields and at least a part of the data and to select, responsively at least to the one or more of the header fields, a location in the host memory. The circuitry writes the data to the selected location and upon determining that the processed data satisfies a predefined criterion, asserts an interrupt on the host processor so as to cause the host processor to read the data from the selected location in the host memory. | 11-28-2013 |
20140003441 | Responding to dynamically-connected transport requests | 01-02-2014 |
20140075436 | SYSTEM AND METHOD FOR ACCELERATING INPUT/OUTPUT ACCESS OPERATION ON A VIRTUAL MACHINE - A system and method for accelerating input/output (IO) access operation on a virtual machine, The method comprises providing a smart IO device that includes an unrestricted command queue (CQ) and a plurality of restricted CQs and allowing a guest domain to directly configure and control IO resources through a respective restricted CQ, the IO resources allocated to the guest domain. In preferred embodiments, the allocation of IO resources to each guest domain is performed by a privileged virtual switching element. In some embodiments, the smart IO device is a HCA and the privileged virtual switching element is a Hypervisor. | 03-13-2014 |
20140095753 | Network interface controller with direct connection to host memory - A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration. | 04-03-2014 |
20140122828 | Sharing address translation between CPU and peripheral devices - A method for memory access includes maintaining in a host memory, under control of a host operating system running on a central processing unit (CPU), respective address translation tables for multiple processes executed by the CPU. Upon receiving, in a peripheral device, a work item that is associated with a given process, having a respective address translation table in the host memory, and specifies a virtual memory address, the peripheral device translates the virtual memory address into a physical memory address by accessing the respective address translation table of the given process in the host memory. The work item is executed in the peripheral device by accessing data at the physical memory address in the host memory. | 05-01-2014 |
20140129741 | PCI-EXPRESS DEVICE SERVING MULTIPLE HOSTS - A method includes establishing in a peripheral device at least first and second communication links with respective first and second hosts. The first communication link is presented to the first host as the only communication link with the peripheral device, and the second communication link is presented to the second host as the only communication link with the peripheral device. The first and second hosts are served simultaneously by the peripheral device over the respective first and second communication links. | 05-08-2014 |
20140143454 | Reducing size of completion notifications - A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to write completion reports to the system memory, including first completion reports of a first data size and second completion reports of a second data size, which is smaller than the first data size. | 05-22-2014 |
20140143455 | Efficient delivery of completion notifications - A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to generate completion reports and to write a plurality of the completion reports to the system memory via the bus together in a single bus transaction. | 05-22-2014 |
20140185615 | SWITCH FABRIC SUPPORT FOR OVERLAY NETWORK FEATURES - A method for communication in a packet data network including a subnet containing multiple nodes having respective ports. The method includes assigning respective local identifiers to the ports in the subnet, such that each port receives a respective local identifier that is unique within the subnet to serve as an address for traffic within the subnet that is directed to the port. In addition to the local identifiers, respective port identifiers are assigned to the ports, such that at least one of the port identifiers is shared by a plurality of the ports, but not by all the ports, in the subnet. The plurality of the ports are addressed collectively using the at least one of the port identifiers. | 07-03-2014 |
20140185616 | Network interface controller supporting network virtualization - A network interface device includes a host interface for connection to a host processor having a memory. A network interface is configured to transmit and receive data packets over a data network, which supports multiple tenant networks overlaid on the data network. Processing circuitry is configured to receive, via the host interface, a work item submitted by a virtual machine running on the host processor, and to identify, responsively to the work item, a tenant network over which the virtual machine is authorized to communicate, wherein the work item specifies a message to be sent to a tenant destination address. The processing circuitry generates, in response to the work item, a data packet containing an encapsulation header that is associated with the tenant network, and to transmit the data packet over the data network to at least one data network address corresponding to the specified tenant destination address. | 07-03-2014 |
20140247832 | Responding to dynamically-connected transport requests - A method for communication, includes allocating, in a network interface controller (NIC) a single dynamically-connected (DC) initiator context for serving requests from an initiator process running on the initiator host to transmit data to multiple target processes running on one or more target nodes. The NIC transmits a first connect packet directed to a first target process and referencing the DC initiator context so as to open a first dynamic connection with the first target process. The NIC receives over the packet network, in response to the first connect packet, a first acknowledgment packet containing a first session identifier (ID). Following receipt of the first acknowledgment packet, the NIC transmits one or more first data packets containing the first session ID over the first dynamic connection from the NIC to the first target process. Dynamic connections with other target processes may subsequently be handled in similar fashion. | 09-04-2014 |
20150026368 | DIRECT MEMORY ACCESS TO STORAGE DEVICES - An interface device includes a first proxy interface configured to carry out first direct memory access (DMA) transactions initiated by an input/output (I/O) device and a second proxy interface configured to carry out second DMA transactions initiated by a storage drive. A buffer memory is coupled between the first and second proxy interfaces and configured to temporarily hold data transferred in the first and second DMA transactions. Control logic is configured to invoke the second DMA transactions in response to the first DMA transactions so as to cause the data to be transferred via the buffer between the I/O device and the storage drive. | 01-22-2015 |